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[/] [ao486/] [trunk/] [rtl/] [soc/] [sound/] [sound_opl2_operator.v] - Blame information for rev 2

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1 2 alfik
/*
2
 * Copyright (c) 2014, Aleksander Osman
3
 * All rights reserved.
4
 *
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions are met:
7
 *
8
 * * Redistributions of source code must retain the above copyright notice, this
9
 *   list of conditions and the following disclaimer.
10
 *
11
 * * Redistributions in binary form must reproduce the above copyright notice,
12
 *   this list of conditions and the following disclaimer in the documentation
13
 *   and/or other materials provided with the distribution.
14
 *
15
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
19
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22
 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
24
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25
 */
26
 
27
module sound_opl2_operator(
28
    input                   clk,
29
    input                   rst_n,
30
 
31
    input                   write_20h_35h,
32
    input                   write_40h_55h,
33
    input                   write_60h_75h,
34
    input                   write_80h_95h,
35
    input                   write_E0h_F5h,
36
 
37
    input           [7:0]   writedata,
38
 
39
    input           [16:0]  freq_and_octave,
40
    input           [3:0]   freq_high,
41
    input           [2:0]   octave,
42
    input           [2:0]   feedback,
43
 
44
    input                   vibrato_depth,
45
    input                   tremolo_depth,
46
 
47
    output                  wform_decrel_request,
48
    output          [7:0]   wform_decrel_address,
49
    input           [15:0]  wform_decrel_q,
50
 
51
    input                   waveform_select_enable,
52
 
53
    output reg      [15:0]  cval,
54
    input                   keyboard_split,
55
 
56
    output          [7:0]   attack_address,
57
    input           [19:0]  attack_value,
58
 
59
    input           [6:0]   prepare_cnt,
60
 
61
    input                   enable_normal,
62
    input                   enable_rythm,
63
    input                   disable_normal,
64
    input                   disable_percussion,
65
 
66
    output                  rythm_c1,
67
    output                  rythm_c2,
68
    output                  rythm_c3,
69
 
70
    input                   rythm_phasebit,
71
    input                   rythm_noisebit,
72
    input                   rythm_snarebit,
73
 
74
    //rythm_bassdrum, rythm_hihat, rythm_snare, rythm_tomtom, rythm_cymbal
75
    input                   rythm_hihat,
76
    input                   rythm_snare,
77
    input                   rythm_cymbal,
78
 
79
    input                   operator_a,
80
    input                   operator_b,
81
 
82
    input           [15:0]  modulator
83
);
84
 
85
//------------------------------------------------------------------------------ write awaiting
86
 
87
reg await_tremolo;
88
always @(posedge clk or negedge rst_n) begin
89
    if(rst_n == 1'b0)       await_tremolo <= 1'b0;
90
    else if(write_20h_35h)  await_tremolo <= writedata[7];
91
end
92
 
93
reg await_vibrato;
94
always @(posedge clk or negedge rst_n) begin
95
    if(rst_n == 1'b0)       await_vibrato <= 1'b0;
96
    else if(write_20h_35h)  await_vibrato <= writedata[6];
97
end
98
 
99
reg await_eg_type;
100
always @(posedge clk or negedge rst_n) begin
101
    if(rst_n == 1'b0)       await_eg_type <= 1'b1;
102
    else if(write_20h_35h)  await_eg_type <= writedata[5];
103
end
104
 
105
reg await_keyboard_scaling_rate;
106
always @(posedge clk or negedge rst_n) begin
107
    if(rst_n == 1'b0)       await_keyboard_scaling_rate <= 1'b0;
108
    else if(write_20h_35h)  await_keyboard_scaling_rate <= writedata[4];
109
end
110
 
111
reg [3:0] await_freq_multi;
112
always @(posedge clk or negedge rst_n) begin
113
    if(rst_n == 1'b0)       await_freq_multi <= 4'd0;
114
    else if(write_20h_35h)  await_freq_multi <= writedata[3:0];
115
end
116
 
117
reg [1:0] await_keyboard_scaling_level;
118
always @(posedge clk or negedge rst_n) begin
119
    if(rst_n == 1'b0)       await_keyboard_scaling_level <= 2'd0;
120
    else if(write_40h_55h)  await_keyboard_scaling_level <= writedata[7:6];
121
end
122
 
123
reg [5:0] await_total_level;
124
always @(posedge clk or negedge rst_n) begin
125
    if(rst_n == 1'b0)       await_total_level <= 6'd0;
126
    else if(write_40h_55h)  await_total_level <= writedata[5:0];
127
end
128
 
129
reg [3:0] await_attack_rate;
130
always @(posedge clk or negedge rst_n) begin
131
    if(rst_n == 1'b0)       await_attack_rate <= 4'd0;
132
    else if(write_60h_75h)  await_attack_rate <= writedata[7:4];
133
end
134
 
135
reg [3:0] await_decay_rate;
136
always @(posedge clk or negedge rst_n) begin
137
    if(rst_n == 1'b0)       await_decay_rate <= 4'd0;
138
    else if(write_60h_75h)  await_decay_rate <= writedata[3:0];
139
end
140
 
141
reg [3:0] await_sustain_level;
142
always @(posedge clk or negedge rst_n) begin
143
    if(rst_n == 1'b0)       await_sustain_level <= 4'd0;
144
    else if(write_80h_95h)  await_sustain_level <= writedata[7:4];
145
end
146
 
147
reg [3:0] await_release_rate;
148
always @(posedge clk or negedge rst_n) begin
149
    if(rst_n == 1'b0)       await_release_rate <= 4'd0;
150
    else if(write_80h_95h)  await_release_rate <= writedata[3:0];
151
end
152
 
153
reg [1:0] await_wave_select;
154
always @(posedge clk or negedge rst_n) begin
155
    if(rst_n == 1'b0)       await_wave_select <= 2'd0;
156
    else if(write_E0h_F5h)  await_wave_select <= writedata[1:0];
157
end
158
 
159
//------------------------------------------------------------------------------
160
 
161
wire prepare_cnt_load_regs      = prepare_cnt == 7'd2;
162
 
163
wire prepare_cnt_freq_1         = prepare_cnt == 7'd3;
164
wire prepare_cnt_freq_2         = prepare_cnt == 7'd4;
165
wire prepare_cnt_freq_3         = prepare_cnt == 7'd5;
166
wire prepare_cnt_freq_4         = prepare_cnt == 7'd6;
167
wire prepare_cnt_freq_5         = prepare_cnt == 7'd7;
168
wire prepare_cnt_freq_6         = prepare_cnt == 7'd8;
169
 
170
wire prepare_cnt_chg_release_1  = prepare_cnt == 7'd9;
171
wire prepare_cnt_chg_release_2  = prepare_cnt == 7'd10;
172
 
173
wire prepare_cnt_chg_decay_1    = prepare_cnt == 7'd11;
174
wire prepare_cnt_chg_decay_2    = prepare_cnt == 7'd12;
175
 
176
wire prepare_cnt_chg_attack_1   = prepare_cnt == 7'd13;
177
 
178
wire prepare_cnt_chg_enable_1   = prepare_cnt == 7'd14;
179
wire prepare_cnt_chg_enable_2   = prepare_cnt == 7'd15;
180
 
181
//
182
 
183
wire prepare_cnt_vibrato_1  = prepare_cnt == 7'd24;
184
wire prepare_cnt_vibrato_2  = prepare_cnt == 7'd25;
185
wire prepare_cnt_vibrato_3  = prepare_cnt == 7'd26;
186
wire prepare_cnt_vibrato_4  = prepare_cnt == 7'd27;
187
wire prepare_cnt_vibrato_5  = prepare_cnt == 7'd28;
188
wire prepare_cnt_vibrato_6  = prepare_cnt == 7'd29;
189
wire prepare_cnt_vibrato_7  = prepare_cnt == 7'd30;
190
wire prepare_cnt_vibrato_8  = prepare_cnt == 7'd31;
191
wire prepare_cnt_vibrato_9  = prepare_cnt == 7'd32;
192
wire prepare_cnt_vibrato_10 = prepare_cnt == 7'd33;
193
wire prepare_cnt_vibrato_11 = prepare_cnt == 7'd34;
194
 
195
wire prepare_cnt_tcount_1   = prepare_cnt == 7'd35;
196
wire prepare_cnt_tcount_2   = prepare_cnt == 7'd36;
197
wire prepare_cnt_tcount_3   = prepare_cnt == 7'd37;
198
//update wfpos, tcount, generator_pos, env_step
199
 
200
wire prepare_cnt_attack_1  = prepare_cnt == 7'd42 && state == S_ATTACK;
201
//wire prepare_cnt_attack_2  = prepare_cnt == 7'd43 && state == S_ATTACK;
202
//wire prepare_cnt_attack_3  = prepare_cnt == 7'd44 && state == S_ATTACK;
203
wire prepare_cnt_attack_4  = prepare_cnt == 7'd45 && state == S_ATTACK;
204
//wire prepare_cnt_attack_5  = prepare_cnt == 7'd46 && state == S_ATTACK;
205
//wire prepare_cnt_attack_6  = prepare_cnt == 7'd47 && state == S_ATTACK;
206
wire prepare_cnt_attack_7  = prepare_cnt == 7'd48 && state == S_ATTACK;
207
//wire prepare_cnt_attack_8  = prepare_cnt == 7'd49 && state == S_ATTACK;
208
//wire prepare_cnt_attack_9  = prepare_cnt == 7'd50 && state == S_ATTACK;
209
wire prepare_cnt_attack_10 = prepare_cnt == 7'd51 && state == S_ATTACK;
210
//wire prepare_cnt_attack_11 = prepare_cnt == 7'd52 && state == S_ATTACK;
211
//wire prepare_cnt_attack_12 = prepare_cnt == 7'd53 && state == S_ATTACK;
212
wire prepare_cnt_attack_13 = prepare_cnt == 7'd54 && state == S_ATTACK;
213
wire prepare_cnt_attack_14 = prepare_cnt == 7'd55 && state == S_ATTACK;
214
//wire prepare_cnt_attack_15 = prepare_cnt == 7'd56 && state == S_ATTACK;
215
//wire prepare_cnt_attack_16 = prepare_cnt == 7'd57 && state == S_ATTACK;
216
wire prepare_cnt_attack_17 = prepare_cnt == 7'd58 && state == S_ATTACK;
217
wire prepare_cnt_attack_18 = prepare_cnt == 7'd59 && state == S_ATTACK;
218
wire prepare_cnt_attack_19 = prepare_cnt == 7'd60 && state == S_ATTACK;
219
//wire prepare_cnt_attack_20 = prepare_cnt == 7'd61 && state == S_ATTACK;
220
//wire prepare_cnt_attack_21 = prepare_cnt == 7'd62 && state == S_ATTACK;
221
wire prepare_cnt_attack_22 = prepare_cnt == 7'd63 && state == S_ATTACK;
222
wire prepare_cnt_attack_23 = prepare_cnt == 7'd64 && state == S_ATTACK;
223
wire prepare_cnt_attack_24 = prepare_cnt == 7'd65 && state == S_ATTACK;
224
wire prepare_cnt_attack_25 = prepare_cnt == 7'd66 && state == S_ATTACK;
225
wire prepare_cnt_attack_26 = prepare_cnt == 7'd67 && state == S_ATTACK;
226
wire prepare_cnt_attack_27 = prepare_cnt == 7'd68 && state == S_ATTACK;
227
wire prepare_cnt_attack_28 = prepare_cnt == 7'd69 && state == S_ATTACK;
228
wire prepare_cnt_attack_29 = prepare_cnt == 7'd70 && state == S_ATTACK;
229
wire prepare_cnt_attack_30 = prepare_cnt == 7'd71 && state == S_ATTACK;
230
 
231
wire prepare_cnt_decay_1   = prepare_cnt == 7'd42 && state == S_DECAY;
232
//wire prepare_cnt_decay_2   = prepare_cnt == 7'd43 && state == S_DECAY;
233
//wire prepare_cnt_decay_3   = prepare_cnt == 7'd44 && state == S_DECAY;
234
wire prepare_cnt_decay_4   = prepare_cnt == 7'd45 && state == S_DECAY;
235
wire prepare_cnt_decay_5   = prepare_cnt == 7'd46 && state == S_DECAY;
236
 
237
wire prepare_cnt_release_1 = prepare_cnt == 7'd42 && (state == S_RELEASE || state == S_SUSTAIN_NOKEEP);
238
//wire prepare_cnt_release_2 = prepare_cnt == 7'd43 && (state == S_RELEASE || state == S_SUSTAIN_NOKEEP);
239
//wire prepare_cnt_release_3 = prepare_cnt == 7'd44 && (state == S_RELEASE || state == S_SUSTAIN_NOKEEP);
240
wire prepare_cnt_release_4 = prepare_cnt == 7'd45 && (state == S_RELEASE || state == S_SUSTAIN_NOKEEP);
241
wire prepare_cnt_release_5 = prepare_cnt == 7'd46 && (state == S_RELEASE || state == S_SUSTAIN_NOKEEP);
242
 
243
wire prepare_cnt_output_1  = (prepare_cnt == 7'd74 && operator_a) || (prepare_cnt == 7'd94 && operator_b);
244
wire prepare_cnt_output_2  = (prepare_cnt == 7'd75 && operator_a) || (prepare_cnt == 7'd95 && operator_b);
245
wire prepare_cnt_output_3  = (prepare_cnt == 7'd76 && operator_a) || (prepare_cnt == 7'd96 && operator_b);
246
wire prepare_cnt_output_4  = (prepare_cnt == 7'd77 && operator_a) || (prepare_cnt == 7'd97 && operator_b);
247
wire prepare_cnt_output_5  = (prepare_cnt == 7'd78 && operator_a) || (prepare_cnt == 7'd98 && operator_b);
248
//wire prepare_cnt_output_6  = (prepare_cnt == 7'd79 && operator_a) || (prepare_cnt == 7'd99 && operator_b);
249
//wire prepare_cnt_output_7  = (prepare_cnt == 7'd80 && operator_a) || (prepare_cnt == 7'd100 && operator_b);
250
wire prepare_cnt_output_8  = (prepare_cnt == 7'd81 && operator_a) || (prepare_cnt == 7'd101 && operator_b);
251
//wire prepare_cnt_output_9  = (prepare_cnt == 7'd82 && operator_a) || (prepare_cnt == 7'd102 && operator_b);
252
//wire prepare_cnt_output_10 = (prepare_cnt == 7'd83 && operator_a) || (prepare_cnt == 7'd103 && operator_b);
253
wire prepare_cnt_output_11 = (prepare_cnt == 7'd84 && operator_a) || (prepare_cnt == 7'd104 && operator_b);
254
//wire prepare_cnt_output_12 = (prepare_cnt == 7'd85 && operator_a) || (prepare_cnt == 7'd105 && operator_b);
255
wire prepare_cnt_output_13 = (prepare_cnt == 7'd86 && operator_a) || (prepare_cnt == 7'd106 && operator_b);
256
wire prepare_cnt_output_14 = (prepare_cnt == 7'd87 && operator_a) || (prepare_cnt == 7'd107 && operator_b);
257
wire prepare_cnt_output_15 = (prepare_cnt == 7'd88 && operator_a) || (prepare_cnt == 7'd108 && operator_b);
258
 
259
 
260
/*
261
 
262
ARC_TVS_KSR_MUL:
263
    change_keepsustain:     op_state, sus_keep (op_state, sus_keep)
264
    change_vibrato:         vibrato*, tremolo*
265
    change_frequency:       toff, tinc, vol, freq_high &
266
 
267
ARC_KSL_OUTLEV:
268
    change_frequency
269
 
270
ARC_ATTR_DECR:
271
    change_attackrate:      a0,a1,a2,a3, env_step_a, env_step_skip_a (attackrate, toff)
272
    change_decayrate:       decaymul, env_step_d (decayrate, toff)
273
 
274
ARC_SUSL_RELR:
275
    change_releaserate:     releasemul, env_step_r (releaserate, toff)
276
    change_sustainlevel:    sustain_level
277
 
278
ARC_FREQ_NUM:
279
    change_frequency op1
280
    change_frequency op2
281
 
282
ARC_KON_BNUM:
283
    enable_operator op1   / disable_operator op1 / enable_operator op1  / disable_operator op1
284
    change_frequency op1  / disable_operator op2 / enable_operator op2  / disable_operator op2
285
    enable_operator op2   /                      / change_frequency op1 / change_frequency op1
286
    change_frequency op2  /                      / change_frequency op2 / change_frequency op2
287
 
288
enable_operator:            tcount, op_state, act_state (act_state, wave_sel)
289
disable_operator:           op_state, act_state
290
 
291
ARC_FEEDBACK:
292
    change_feedback:        mfbi
293
 
294
ARC_WAVE_SEL:
295
    change_waveform:        cur_wmask, cur_wform (wave_sel)
296
 
297
*/
298
 
299
 
300
reg tremolo;
301
always @(posedge clk or negedge rst_n) begin
302
    if(rst_n == 1'b0)               tremolo <= 1'b0;
303
    else if(prepare_cnt_load_regs)  tremolo <= await_tremolo;
304
end
305
 
306
reg vibrato;
307
always @(posedge clk or negedge rst_n) begin
308
    if(rst_n == 1'b0)               vibrato <= 1'b0;
309
    else if(prepare_cnt_load_regs)  vibrato <= await_vibrato;
310
end
311
 
312
reg eg_type;
313
always @(posedge clk or negedge rst_n) begin
314
    if(rst_n == 1'b0)               eg_type <= 1'b1;
315
    else if(prepare_cnt_load_regs)  eg_type <= await_eg_type;
316
end
317
 
318
reg keyboard_scaling_rate;
319
always @(posedge clk or negedge rst_n) begin
320
    if(rst_n == 1'b0)               keyboard_scaling_rate <= 1'b0;
321
    else if(prepare_cnt_load_regs)  keyboard_scaling_rate <= await_keyboard_scaling_rate;
322
end
323
 
324
reg [3:0] freq_multi;
325
always @(posedge clk or negedge rst_n) begin
326
    if(rst_n == 1'b0)               freq_multi <= 4'd0;
327
    else if(prepare_cnt_load_regs)  freq_multi <= await_freq_multi;
328
end
329
 
330
reg [1:0] keyboard_scaling_level;
331
always @(posedge clk or negedge rst_n) begin
332
    if(rst_n == 1'b0)               keyboard_scaling_level <= 2'd0;
333
    else if(prepare_cnt_load_regs)  keyboard_scaling_level <= await_keyboard_scaling_level;
334
end
335
 
336
reg [5:0] total_level;
337
always @(posedge clk or negedge rst_n) begin
338
    if(rst_n == 1'b0)               total_level <= 6'd0;
339
    else if(prepare_cnt_load_regs)  total_level <= await_total_level;
340
end
341
 
342
reg [3:0] attack_rate;
343
always @(posedge clk or negedge rst_n) begin
344
    if(rst_n == 1'b0)               attack_rate <= 4'd0;
345
    else if(prepare_cnt_load_regs)  attack_rate <= await_attack_rate;
346
end
347
 
348
reg [3:0] decay_rate;
349
always @(posedge clk or negedge rst_n) begin
350
    if(rst_n == 1'b0)               decay_rate <= 4'd0;
351
    else if(prepare_cnt_load_regs)  decay_rate <= await_decay_rate;
352
end
353
 
354
reg [3:0] sustain_level;
355
always @(posedge clk or negedge rst_n) begin
356
    if(rst_n == 1'b0)               sustain_level <= 4'd0;
357
    else if(prepare_cnt_load_regs)  sustain_level <= await_sustain_level;
358
end
359
 
360
reg [3:0] release_rate;
361
always @(posedge clk or negedge rst_n) begin
362
    if(rst_n == 1'b0)               release_rate <= 4'd0;
363
    else if(prepare_cnt_load_regs)  release_rate <= await_release_rate;
364
end
365
 
366
reg [1:0] wave_select;
367
always @(posedge clk or negedge rst_n) begin
368
    if(rst_n == 1'b0)                                           wave_select <= 2'd0;
369
    else if(prepare_cnt_load_regs && waveform_select_enable)    wave_select <= await_wave_select;
370
end
371
 
372
//------------------------------------------------------------------------------ change_frequency
373
 
374
wire [3:0] freq_multi_final =
375
    (freq_multi == 4'd11)?  4'd10 :
376
    (freq_multi == 4'd13)?  4'd12 :
377
    (freq_multi == 4'd14)?  4'd15 :
378
                            freq_multi;
379
 
380
// f_INT * fixedpoint / (N * f_s)
381
// f_INT = 49715,903 Hz
382
// fixedpoint = 32'h00010000
383
// N = 1024
384
// f_s = 96000 Hz
385
 
386
// freq_multi * (32+1) * freq_and_octave
387
 
388
reg [22:0] tinc_prepare;
389
always @(posedge clk or negedge rst_n) begin
390
    if(rst_n == 1'b0)          tinc_prepare <= 23'd0;
391
    else if(prepare_cnt_freq_1) tinc_prepare <= { 5'd0, freq_and_octave } + { freq_and_octave, 5'd0 }; //(32+1) * freq_and_octave
392
end
393
 
394
reg [25:0] tinc;
395
always @(posedge clk or negedge rst_n) begin
396
    if(rst_n == 1'b0)                                                       tinc <= 26'd0;
397
    else if(prepare_cnt_freq_1)                                              tinc <= 26'd0;
398
    else if(prepare_cnt_freq_2 && freq_multi == 4'd0)                        tinc <= {  4'd0, tinc_prepare[22:1] }; // div2
399
    else if(prepare_cnt_freq_2 && freq_multi != 4'd0 && freq_multi_final[0]) tinc <= tinc + { 3'd0, tinc_prepare };
400
    else if(prepare_cnt_freq_3 && freq_multi != 4'd0 && freq_multi_final[1]) tinc <= tinc + { 2'd0, tinc_prepare, 1'd0 };
401
    else if(prepare_cnt_freq_4 && freq_multi != 4'd0 && freq_multi_final[2]) tinc <= tinc + { 1'd0, tinc_prepare, 2'd0 };
402
    else if(prepare_cnt_freq_5 && freq_multi != 4'd0 && freq_multi_final[3]) tinc <= tinc + {       tinc_prepare, 3'd0 };
403
end
404
 
405
wire [3:0] toff_next =
406
    (~(keyboard_scaling_rate))? { 2'b0, octave[2:1] } : { octave, (freq_high[3] & ~(keyboard_split)) | (freq_high[2] & keyboard_split) };
407
 
408
reg [3:0] toff;
409
always @(posedge clk or negedge rst_n) begin
410
    if(rst_n == 1'b0)          toff <= 4'd0;
411
    else if(prepare_cnt_freq_6) toff <= toff_next;
412
end
413
 
414
wire [5:0] kslev_prepare =
415
    (freq_high == 4'd15)?     6'd56 :
416
    (freq_high == 4'd14)?     6'd55 :
417
    (freq_high == 4'd13)?     6'd54 :
418
    (freq_high == 4'd12)?     6'd53 :
419
    (freq_high == 4'd11)?     6'd52 :
420
    (freq_high == 4'd10)?     6'd51 :
421
    (freq_high == 4'd9)?      6'd50 :
422
    (freq_high == 4'd8)?      6'd48 :
423
    (freq_high == 4'd7)?      6'd47 :
424
    (freq_high == 4'd6)?      6'd45 :
425
    (freq_high == 4'd5)?      6'd43 :
426
    (freq_high == 4'd4)?      6'd40 :
427
    (freq_high == 4'd3)?      6'd37 :
428
    (freq_high == 4'd2)?      6'd32 :
429
    (freq_high == 4'd1)?      6'd24 :
430
                              6'd0;
431
 
432
wire [2:0] kslev_oct = 3'd7 - octave;
433
wire [5:0] kslev_sub = { kslev_oct, 3'b0 };
434
 
435
wire [5:0] kslev = (kslev_sub > kslev_prepare)? 6'd0 : kslev_prepare - kslev_sub;
436
 
437
//total_level[5:0]
438
//keyboard_scaling_level[1:0]
439
 
440
wire [7:0] kslev_mult =
441
    (keyboard_scaling_level == 2'd0)?   8'd0 :
442
    (keyboard_scaling_level == 2'd1)?   { 1'd0, kslev, 1'd0 } :
443
    (keyboard_scaling_level == 2'd2)?   { 2'd0, kslev } :
444
                                        {       kslev, 2'd0 };
445
 
446
reg [8:0] volume_in;
447
always @(posedge clk or negedge rst_n) begin
448
    if(rst_n == 1'b0)           volume_in <= 9'd0;
449
    else if(prepare_cnt_freq_1)  volume_in <= { 1'b0, kslev_mult };
450
    else if(prepare_cnt_freq_2)  volume_in <= volume_in + { 1'b0, total_level, 2'd0 };
451
end
452
 
453
wire [16:0] volume_prepare =
454
    (volume_in[4:0] == 5'd0)?   { 1'b1, 16'h0000 } :
455
    (volume_in[4:0] == 5'd1)?   { 1'b0, 16'hFA83 } : //2^{-1/32}
456
    (volume_in[4:0] == 5'd2)?   { 1'b0, 16'hF525 } : //2^{-2/32}
457
    (volume_in[4:0] == 5'd3)?   { 1'b0, 16'hEFE4 } : //2^{-3/32}
458
    (volume_in[4:0] == 5'd4)?   { 1'b0, 16'hEAC0 } : //2^{-4/32}
459
    (volume_in[4:0] == 5'd5)?   { 1'b0, 16'hE5B9 } : //2^{-5/32}
460
    (volume_in[4:0] == 5'd6)?   { 1'b0, 16'hE0CC } : //2^{-6/32}
461
    (volume_in[4:0] == 5'd7)?   { 1'b0, 16'hDBFB } : //2^{-7/32}
462
    (volume_in[4:0] == 5'd8)?   { 1'b0, 16'hD744 } : //2^{-8/32}
463
    (volume_in[4:0] == 5'd9)?   { 1'b0, 16'hD2A8 } : //2^{-9/32}
464
    (volume_in[4:0] == 5'd10)?  { 1'b0, 16'hCE24 } : //2^{-10/32}
465
    (volume_in[4:0] == 5'd11)?  { 1'b0, 16'hC9B9 } : //2^{-11/32}
466
    (volume_in[4:0] == 5'd12)?  { 1'b0, 16'hC567 } : //2^{-12/32}
467
    (volume_in[4:0] == 5'd13)?  { 1'b0, 16'hC12C } : //2^{-13/32}
468
    (volume_in[4:0] == 5'd14)?  { 1'b0, 16'hBD08 } : //2^{-14/32}
469
    (volume_in[4:0] == 5'd15)?  { 1'b0, 16'hB8FB } : //2^{-15/32}
470
    (volume_in[4:0] == 5'd16)?  { 1'b0, 16'hB504 } : //2^{-16/32}
471
    (volume_in[4:0] == 5'd17)?  { 1'b0, 16'hB123 } : //2^{-17/32}
472
    (volume_in[4:0] == 5'd18)?  { 1'b0, 16'hAD58 } : //2^{-18/32}
473
    (volume_in[4:0] == 5'd19)?  { 1'b0, 16'hA9A1 } : //2^{-19/32}
474
    (volume_in[4:0] == 5'd20)?  { 1'b0, 16'hA5FE } : //2^{-20/32}
475
    (volume_in[4:0] == 5'd21)?  { 1'b0, 16'hA270 } : //2^{-21/32}
476
    (volume_in[4:0] == 5'd22)?  { 1'b0, 16'h9EF5 } : //2^{-22/32}
477
    (volume_in[4:0] == 5'd23)?  { 1'b0, 16'h9B8D } : //2^{-23/32}
478
    (volume_in[4:0] == 5'd24)?  { 1'b0, 16'h9837 } : //2^{-24/32}
479
    (volume_in[4:0] == 5'd25)?  { 1'b0, 16'h94F4 } : //2^{-25/32}
480
    (volume_in[4:0] == 5'd26)?  { 1'b0, 16'h91C3 } : //2^{-26/32}
481
    (volume_in[4:0] == 5'd27)?  { 1'b0, 16'h8EA4 } : //2^{-27/32}
482
    (volume_in[4:0] == 5'd28)?  { 1'b0, 16'h8B95 } : //2^{-28/32}
483
    (volume_in[4:0] == 5'd29)?  { 1'b0, 16'h8898 } : //2^{-29/32}
484
    (volume_in[4:0] == 5'd30)?  { 1'b0, 16'h85AA } : //2^{-30/32}
485
                                { 1'b0, 16'h82CD };  //2^{-31/32}
486
 
487
reg [16:0] volume_frac;
488
always @(posedge clk or negedge rst_n) begin
489
    if(rst_n == 1'b0)           volume_frac <= 17'd0;
490
    else if(prepare_cnt_freq_3)  volume_frac <= volume_prepare;
491
end
492
 
493
reg [3:0] volume_int;
494
always @(posedge clk or negedge rst_n) begin
495
    if(rst_n == 1'b0)           volume_int <= 4'd0;
496
    else if(prepare_cnt_freq_3)  volume_int <= volume_in[8:5];
497
end
498
 
499
//------------------------------------------------------------------------------ change_release, change_decay, waveform
500
 
501
assign wform_decrel_request = prepare_cnt_chg_release_1 || prepare_cnt_chg_decay_1;
502
 
503
assign wform_decrel_address = (prepare_cnt_chg_release_1)? { toff, release_rate } : (prepare_cnt_chg_decay_1)? { toff, decay_rate } : waveform_address;
504
 
505
//------------------------------------------------------------------------------ change_release
506
 
507
reg [16:0] release_mul;
508
always @(posedge clk or negedge rst_n) begin
509
    if(rst_n == 1'b0)               release_mul <= 17'h10000;
510
    else if(prepare_cnt_chg_release_2)   release_mul <= (release_rate == 4'd0)? 17'h10000 : { 1'b0, wform_decrel_q };
511
end
512
 
513
wire [6:0] release_steps = { 1'b0, release_rate, 2'b0 } + { 3'd0, toff };
514
 
515
wire [11:0] release_mask_next =
516
    (release_rate == 4'd0)?         12'h0 :
517
    (release_steps[6:2] >= 5'd12)?  12'h0 :
518
    (release_steps[6:2] == 5'd11)?  12'h001 :
519
    (release_steps[6:2] == 5'd10)?  12'h003 :
520
    (release_steps[6:2] == 5'd9)?   12'h007 :
521
    (release_steps[6:2] == 5'd8)?   12'h00F :
522
    (release_steps[6:2] == 5'd7)?   12'h01F :
523
    (release_steps[6:2] == 5'd6)?   12'h03F :
524
    (release_steps[6:2] == 5'd5)?   12'h07F :
525
    (release_steps[6:2] == 5'd4)?   12'h0FF :
526
    (release_steps[6:2] == 5'd3)?   12'h1FF :
527
    (release_steps[6:2] == 5'd2)?   12'h3FF :
528
    (release_steps[6:2] == 5'd1)?   12'h7FF :
529
                                    12'hFFF;
530
 
531
reg [11:0] release_mask;
532
always @(posedge clk or negedge rst_n) begin
533
    if(rst_n == 1'b0)               release_mask <= 12'd0;
534
    else if(prepare_cnt_chg_release_2)   release_mask <= release_mask_next;
535
end
536
 
537
//------------------------------------------------------------------------------ change_decay
538
 
539
reg [16:0] decay_mul;
540
always @(posedge clk or negedge rst_n) begin
541
    if(rst_n == 1'b0)           decay_mul <= 17'h10000;
542
    else if(prepare_cnt_chg_decay_2) decay_mul <= (decay_rate == 4'd0)? 17'h10000 : { 1'b0, wform_decrel_q };
543
end
544
 
545
wire [6:0] decay_steps = { 1'b0, decay_rate, 2'b0 } + { 3'd0, toff };
546
 
547
wire [11:0] decay_mask_next =
548
    (decay_rate == 4'd0)?           12'h0 :
549
    (decay_steps[6:2] >= 5'd12)?    12'h0 :
550
    (decay_steps[6:2] == 5'd11)?    12'h001 :
551
    (decay_steps[6:2] == 5'd10)?    12'h003 :
552
    (decay_steps[6:2] == 5'd9)?     12'h007 :
553
    (decay_steps[6:2] == 5'd8)?     12'h00F :
554
    (decay_steps[6:2] == 5'd7)?     12'h01F :
555
    (decay_steps[6:2] == 5'd6)?     12'h03F :
556
    (decay_steps[6:2] == 5'd5)?     12'h07F :
557
    (decay_steps[6:2] == 5'd4)?     12'h0FF :
558
    (decay_steps[6:2] == 5'd3)?     12'h1FF :
559
    (decay_steps[6:2] == 5'd2)?     12'h3FF :
560
    (decay_steps[6:2] == 5'd1)?     12'h7FF :
561
                                    12'hFFF;
562
 
563
reg [11:0] decay_mask;
564
always @(posedge clk or negedge rst_n) begin
565
    if(rst_n == 1'b0)                   decay_mask <= 12'd0;
566
    else if(prepare_cnt_chg_decay_2)    decay_mask <= decay_mask_next;
567
end
568
 
569
//------------------------------------------------------------------------------ change_attack
570
 
571
assign attack_address = { toff, attack_rate };
572
 
573
wire [6:0] attack_steps = { 1'b0, attack_rate, 2'b0 } + { 3'd0, toff };
574
 
575
wire [11:0] attack_mask_next =
576
    (attack_rate == 4'd0)?          12'h0 :
577
    (attack_steps[6:2] >= 5'd12)?   12'h0 :
578
    (attack_steps[6:2] == 5'd11)?   12'h001 :
579
    (attack_steps[6:2] == 5'd10)?   12'h003 :
580
    (attack_steps[6:2] == 5'd9)?    12'h007 :
581
    (attack_steps[6:2] == 5'd8)?    12'h00F :
582
    (attack_steps[6:2] == 5'd7)?    12'h01F :
583
    (attack_steps[6:2] == 5'd6)?    12'h03F :
584
    (attack_steps[6:2] == 5'd5)?    12'h07F :
585
    (attack_steps[6:2] == 5'd4)?    12'h0FF :
586
    (attack_steps[6:2] == 5'd3)?    12'h1FF :
587
    (attack_steps[6:2] == 5'd2)?    12'h3FF :
588
    (attack_steps[6:2] == 5'd1)?    12'h7FF :
589
                                    12'hFFF;
590
 
591
reg [11:0] attack_mask;
592
always @(posedge clk or negedge rst_n) begin
593
    if(rst_n == 1'b0)               attack_mask <= 12'd0;
594
    else if(prepare_cnt_chg_attack_1)    attack_mask <= attack_mask_next;
595
end
596
 
597
wire [7:0] attack_skip_mask_next =
598
    (attack_mask_next > 12'd48)?        8'hFF :
599
    (attack_mask_next[1:0] == 2'd0)?    8'hAA :
600
    (attack_mask_next[1:0] == 2'd1)?    8'hBA :
601
    (attack_mask_next[1:0] == 2'd2)?    8'hEE :
602
                                        8'hFE;
603
 
604
reg [7:0] attack_skip_mask;
605
always @(posedge clk or negedge rst_n) begin
606
    if(rst_n == 1'b0)                   attack_skip_mask <= 8'd0;
607
    else if(prepare_cnt_chg_attack_1)   attack_skip_mask <= attack_skip_mask_next;
608
end
609
 
610
//------------------------------------------------------------------------------ change_enable / change_disable : react everytime
611
 
612
reg active_normal;
613
always @(posedge clk or negedge rst_n) begin
614
    if(rst_n == 1'b0)                                               active_normal <= 1'b0;
615
    else if(~(active_normal) && ~(active_rythm) && enable_normal)   active_normal <= 1'b1;
616
    else if(active_normal && disable_normal)                        active_normal <= 1'b0;
617
end
618
 
619
reg active_rythm;
620
always @(posedge clk or negedge rst_n) begin
621
    if(rst_n == 1'b0)                                               active_rythm <= 1'b0;
622
    else if(~(active_normal) && ~(active_rythm) && enable_rythm)    active_rythm <= 1'b1;
623
    else if(active_rythm && disable_percussion)                     active_rythm <= 1'b0;
624
end
625
 
626
localparam [1:0] ACTIVE_IDLE        = 2'd0;
627
localparam [1:0] ACTIVE_TO_RELEASE  = 2'd1;
628
localparam [1:0] ACTIVE_TO_ATTACK   = 2'd2;
629
 
630
reg [1:0] active_on_next_sample;
631
always @(posedge clk or negedge rst_n) begin
632
    if(rst_n == 1'b0)                                                                   active_on_next_sample <= ACTIVE_IDLE;
633
    else if(~(active_normal) && ~(active_rythm) && (enable_normal || enable_rythm))     active_on_next_sample <= ACTIVE_TO_ATTACK;
634
    else if((active_normal && disable_normal) || (active_rythm && disable_percussion))  active_on_next_sample <= ACTIVE_TO_RELEASE;
635
    else if(prepare_cnt_chg_enable_2)                                                   active_on_next_sample <= ACTIVE_IDLE;
636
end
637
 
638
//------------------------------------------------------------------------------ state
639
 
640
localparam [2:0] S_OFF              = 3'd0;
641
localparam [2:0] S_ATTACK           = 3'd1;
642
localparam [2:0] S_DECAY            = 3'd2;
643
localparam [2:0] S_SUSTAIN          = 3'd3;
644
localparam [2:0] S_SUSTAIN_NOKEEP   = 3'd4;
645
localparam [2:0] S_RELEASE          = 3'd5;
646
 
647
reg [2:0] state;
648
always @(posedge clk or negedge rst_n) begin
649
    if(rst_n == 1'b0)                                                                                   state <= S_OFF;
650
 
651
    else if(prepare_cnt_chg_enable_1 && active_on_next_sample == ACTIVE_TO_ATTACK)                      state <= S_ATTACK;
652
    else if(prepare_cnt_chg_enable_1 && active_on_next_sample == ACTIVE_TO_RELEASE && state != S_OFF)   state <= S_RELEASE;
653
 
654
    else if(prepare_cnt_chg_enable_1 && state == S_SUSTAIN        && eg_type == 1'b0)                   state <= S_SUSTAIN_NOKEEP;
655
    else if(prepare_cnt_chg_enable_1 && state == S_SUSTAIN_NOKEEP && eg_type == 1'b1)                   state <= S_SUSTAIN;
656
 
657
    //attack
658
    else if(attack_step_finished)                                                                       state <= S_DECAY;
659
 
660
    //decay
661
    else if(decay_step_finish_to_sustain)                                                               state <= S_SUSTAIN;
662
    else if(decay_step_finish_to_sustain_no_keep)                                                       state <= S_SUSTAIN_NOKEEP;
663
 
664
    //release
665
    else if(state == S_RELEASE && release_step_finish)                                                  state <= S_OFF;
666
end
667
 
668
//------------------------------------------------------------------------------ rythm data between operators
669
 
670
assign rythm_c1 = (tcount[18] ^ tcount[23]) | tcount[19];  //(c1 & 0x88) ^ ((c1<<5) & 0x80)
671
assign rythm_c2 = tcount[24];
672
assign rythm_c3 = tcount[21] ^ tcount[19]; //((c3 ^ (c3<<2)) & 0x20)
673
 
674
//------------------------------------------------------------------------------ vibrato
675
 
676
// (f_INT/8192) * (8/f_s) * LFO_fixedpoint = 8484
677
// ~6,1 Hz
678
 
679
reg [26:0] vibrato_pos;
680
always @(posedge clk or negedge rst_n) begin
681
    if(rst_n == 1'b0)               vibrato_pos <= 27'd0;
682
    else if(prepare_cnt_vibrato_1)  vibrato_pos <= vibrato_pos + 27'd8484;
683
end
684
 
685
wire vibrato_table_8 = vibrato_depth && (vibrato_pos[26:24] == 3'd0 || vibrato_pos[26:24] == 3'd4);
686
wire vibrato_table_4 =
687
    (vibrato_depth == 1'b0 && (vibrato_pos[26:24] == 3'd0 || vibrato_pos[26:24] == 3'd4)) ||
688
    (vibrato_depth == 1'b1 && (vibrato_pos[26:24] == 3'd1 || vibrato_pos[26:24] == 3'd3 || vibrato_pos[26:24] == 3'd5 || vibrato_pos[26:24] == 3'd7));
689
wire vibrato_table_2 =
690
    (vibrato_depth == 1'b0 && (vibrato_pos[26:24] == 3'd1 || vibrato_pos[26:24] == 3'd3 || vibrato_pos[26:24] == 3'd5 || vibrato_pos[26:24] == 3'd7));
691
 
692
wire [9:0] vibrato_mult =
693
    (vibrato_table_8 && freq_high[3:1] == 3'd1)?                                10'd91 :  //1
694
    (vibrato_table_8 && freq_high[3:1] == 3'd2)?                                10'd183 : //2
695
    (vibrato_table_8 && freq_high[3:1] == 3'd3)?                                10'd275 : //3
696
    (vibrato_table_8 && freq_high[3:1] == 3'd4)?                                10'd367 : //4
697
    (vibrato_table_8 && freq_high[3:1] == 3'd5)?                                10'd458 : //5
698
    (vibrato_table_8 && freq_high[3:1] == 3'd6)?                                10'd550 : //6
699
    (vibrato_table_8 && freq_high[3:1] == 3'd7)?                                10'd642 : //7
700
    (vibrato_table_4 && (freq_high[3:1] == 3'd2 || freq_high[3:1] == 3'd3))?    10'd91 :  //1
701
    (vibrato_table_4 && (freq_high[3:1] == 3'd4 || freq_high[3:1] == 3'd5))?    10'd183 : //2
702
    (vibrato_table_4 && (freq_high[3:1] == 3'd6 || freq_high[3:1] == 3'd7))?    10'd275 : //3
703
    (vibrato_table_2 && freq_high[3:1] >= 3'd4)?                                10'd91 :  //1
704
                                                                                10'd0;
705
 
706
//vibrato_pos[26:24]
707
//freq_high[3:1]
708
//vibrato_depth[0]
709
 
710
//tinc*(lut*high/8)*fixed*70/50000)/fixed
711
 
712
wire vibrato_sign = vibrato_pos[26:24] == 3'd3 || vibrato_pos[26:24] == 3'd4 || vibrato_pos[26:24] == 3'd5;
713
 
714
reg [35:0] tinc_vibrato;
715
always @(posedge clk or negedge rst_n) begin
716
    if(rst_n == 1'b0)                                   tinc_vibrato <= 36'd0;
717
    else if(prepare_cnt_vibrato_1)                      tinc_vibrato <= 36'd0;
718
    else if(prepare_cnt_vibrato_2  && vibrato_mult[0])  tinc_vibrato <= tinc_vibrato + { 10'd0, tinc };
719
    else if(prepare_cnt_vibrato_3  && vibrato_mult[1])  tinc_vibrato <= tinc_vibrato + { 9'd0,  tinc, 1'b0 };
720
    else if(prepare_cnt_vibrato_4  && vibrato_mult[2])  tinc_vibrato <= tinc_vibrato + { 8'd0,  tinc, 2'b0 };
721
    else if(prepare_cnt_vibrato_5  && vibrato_mult[3])  tinc_vibrato <= tinc_vibrato + { 7'd0,  tinc, 3'b0 };
722
    else if(prepare_cnt_vibrato_6  && vibrato_mult[4])  tinc_vibrato <= tinc_vibrato + { 6'd0,  tinc, 4'b0 };
723
    else if(prepare_cnt_vibrato_7  && vibrato_mult[5])  tinc_vibrato <= tinc_vibrato + { 5'd0,  tinc, 5'b0 };
724
    else if(prepare_cnt_vibrato_8  && vibrato_mult[6])  tinc_vibrato <= tinc_vibrato + { 4'd0,  tinc, 6'b0 };
725
    else if(prepare_cnt_vibrato_9  && vibrato_mult[7])  tinc_vibrato <= tinc_vibrato + { 3'd0,  tinc, 7'b0 };
726
    else if(prepare_cnt_vibrato_10 && vibrato_mult[8])  tinc_vibrato <= tinc_vibrato + { 2'd0,  tinc, 8'b0 };
727
    else if(prepare_cnt_vibrato_11 && vibrato_mult[9])  tinc_vibrato <= tinc_vibrato + { 1'd0,  tinc, 9'b0 };
728
end
729
 
730
//------------------------------------------------------------------------------
731
 
732
reg [25:0] tcount;
733
always @(posedge clk or negedge rst_n) begin
734
    if(rst_n == 1'b0)                                                               tcount <= 26'd0;
735
    else if(prepare_cnt_chg_enable_1 && active_on_next_sample == ACTIVE_TO_ATTACK)  tcount <= 26'd0;
736
 
737
    else if(prepare_cnt_tcount_2 && vibrato && ~(vibrato_sign))                     tcount <= tcount + { 6'd0, tinc_vibrato[35:16] };
738
    else if(prepare_cnt_tcount_2 && vibrato && vibrato_sign)                        tcount <= tcount - { 6'd0, tinc_vibrato[35:16] };
739
    else if(prepare_cnt_tcount_3)                                                   tcount <= tcount + tinc;
740
end
741
 
742
wire [25:0] wfpos_next =
743
                                                                                //(phasebit<<8) | (0x34<<(phasebit ^ (noisebit<<1)))
744
    (rythm_hihat  && active_rythm && ~(rythm_phasebit) && ~(rythm_noisebit))?   { 2'b0, 8'h34, 16'd0 }:
745
    (rythm_hihat  && active_rythm && ~(rythm_phasebit) && rythm_noisebit)?      { 8'h34, 2'b0, 16'd0 } :
746
    (rythm_hihat  && active_rythm && rythm_phasebit    && ~(rythm_noisebit))?   { 8'h80 | 8'h34, 2'b0, 16'd0 } :
747
    (rythm_hihat  && active_rythm && rythm_phasebit    && rythm_noisebit)?      { 8'h80 | 8'h0D, 2'b0, 16'd0 } :
748
                                                                                //((1+snare_phase_bit) ^ noisebit)<<8
749
    (rythm_snare  && active_rythm && ~(rythm_snarebit) && ~(rythm_noisebit))?   { 2'b01, 8'd0, 16'd0 } :
750
    (rythm_snare  && active_rythm && ~(rythm_snarebit) && rythm_noisebit)?      { 2'b00, 8'd0, 16'd0 } :
751
    (rythm_snare  && active_rythm && rythm_snarebit    && ~(rythm_noisebit))?   { 2'b10, 8'd0, 16'd0 } :
752
    (rythm_snare  && active_rythm && rythm_snarebit    && rythm_noisebit)?      { 2'b11, 8'd0, 16'd0 } :
753
                                                                                //(1+phasebit)<<8
754
    (rythm_cymbal && active_rythm && ~(rythm_phasebit))?                        { 2'b01, 8'd0, 16'd0 } :
755
    (rythm_cymbal && active_rythm && rythm_phasebit)?                           { 2'b11, 8'd0, 16'd0 } :
756
                                                                                tcount;
757
 
758
reg [25:0] wfpos;
759
always @(posedge clk or negedge rst_n) begin
760
    if(rst_n == 1'b0)               wfpos <= 26'd0;
761
    else if(prepare_cnt_tcount_1)   wfpos <= wfpos_next;
762
end
763
 
764
//------------------------------------------------------------------------------ generator_pos
765
 
766
reg [16:0] generator_pos;
767
always @(posedge clk or negedge rst_n) begin
768
    if(rst_n == 1'b0)                                   generator_pos <= 17'd0;
769
    else if(prepare_cnt_tcount_1 && generator_pos[16])  generator_pos <= { 1'b0, generator_pos[15:0] };
770
    else if(prepare_cnt_tcount_2)                       generator_pos <= generator_pos + 17'd33939; //f_INT / f_s * fixedpoint
771
end
772
 
773
wire generator_active = generator_pos[16];
774
 
775
reg [11:0] env_step;
776
always @(posedge clk or negedge rst_n) begin
777
    if(rst_n == 1'b0)                                                   env_step <= 12'd0;
778
    else if(prepare_cnt_tcount_3 && state != S_OFF && generator_active) env_step <= env_step + 12'd1; //for attack,decay,release,sustain
779
end
780
 
781
//------------------------------------------------------------------------------ operate on attack
782
 
783
reg [19:0] attack_sum;
784
always @(posedge clk or negedge rst_n) begin
785
    if(rst_n == 1'b0)               attack_sum <= 20'd0;
786
    else if(prepare_cnt_attack_4)   attack_sum <= mult_result[35:16];                   //amp^2
787
    else if(prepare_cnt_attack_10)  attack_sum <= mult_result[35:16];                   //(3)
788
    else if(prepare_cnt_attack_14)  attack_sum <= attack_sum + mult_result_reg[35:16];  //(2)
789
    else if(prepare_cnt_attack_17)  attack_sum <= attack_sum + mult_result_reg[35:16];  //(1)
790
    else if(prepare_cnt_attack_18)  attack_sum <= attack_sum + 20'd154;                 //0.0377/16 *fixedpoint
791
end
792
 
793
reg [19:0] attack_amp;
794
always @(posedge clk or negedge rst_n) begin
795
    if(rst_n == 1'b0)                                   attack_amp <= 20'd0;
796
    else if(prepare_cnt_attack_22)                      attack_amp <= mult_result[35:16];
797
    else if(prepare_cnt_attack_23 && attack_value[16])  attack_amp <= attack_amp + { attack_sum[18:0], 1'b0 };
798
    else if(prepare_cnt_attack_24 && attack_value[17])  attack_amp <= attack_amp + { attack_sum[17:0], 2'b0 };
799
    else if(prepare_cnt_attack_25 && attack_value[18])  attack_amp <= attack_amp + { attack_sum[16:0], 3'b0 };
800
    else if(prepare_cnt_attack_26 && attack_value[19])  attack_amp <= attack_amp + { attack_sum[15:0], 4'b0 };
801
end
802
 
803
//
804
 
805
wire attack_step_active_1 = prepare_cnt_attack_29 && generator_active && (env_step & attack_mask) == 12'd0;
806
wire attack_step_active_2 = prepare_cnt_attack_30 && generator_active && (env_step & attack_mask) == 12'd0;
807
 
808
wire attack_step_finished = attack_step_active_2 && (amp >= 20'd65536 || attack_steps >= 7'd62);
809
wire attack_step_update   = attack_step_active_2 && (attack_skip_pos & attack_skip_mask) != 8'd0;
810
 
811
reg [7:0] attack_skip_pos;
812
always @(posedge clk or negedge rst_n) begin
813
    if(rst_n == 1'b0)                                           attack_skip_pos <= 8'd0;
814
    else if(attack_step_active_1 && attack_skip_pos == 8'd0)    attack_skip_pos <= 8'd1;
815
    else if(attack_step_active_1)                               attack_skip_pos <= { attack_skip_pos[6:0], attack_skip_pos[7] };
816
end
817
 
818
//------------------------------------------------------------------------------ operate on decay
819
 
820
wire [16:0] sustain_amp =
821
    (sustain_level == 4'd0)?    17'h10000 :
822
    (sustain_level == 4'd1)?    17'h0B504 :
823
    (sustain_level == 4'd2)?    17'h08000 :
824
    (sustain_level == 4'd3)?    17'h05A82 :
825
    (sustain_level == 4'd4)?    17'h04000 :
826
    (sustain_level == 4'd5)?    17'h02D41 :
827
    (sustain_level == 4'd6)?    17'h02000 :
828
    (sustain_level == 4'd7)?    17'h016A0 :
829
    (sustain_level == 4'd8)?    17'h01000 :
830
    (sustain_level == 4'd9)?    17'h00B50 :
831
    (sustain_level == 4'd10)?   17'h00800 :
832
    (sustain_level == 4'd11)?   17'h005A8 :
833
    (sustain_level == 4'd12)?   17'h00400 :
834
    (sustain_level == 4'd13)?   17'h002D4 :
835
    (sustain_level == 4'd14)?   17'h00200 :
836
                                17'h00000;
837
 
838
wire decay_step_active = prepare_cnt_decay_5 && generator_active && (env_step & decay_mask) == 12'd0;
839
 
840
wire decay_step_finish_to_sustain           = decay_step_active && amp <= { 3'b0, sustain_amp } && eg_type;
841
wire decay_step_finish_to_sustain_no_keep   = decay_step_active && amp <= { 3'b0, sustain_amp } && ~(eg_type);
842
 
843
//------------------------------------------------------------------------------ operate on release
844
 
845
wire release_step_active = prepare_cnt_release_5 && generator_active && (env_step & release_mask) == 12'd0;
846
wire release_step_finish = release_step_active && amp <= 20'd1;
847
 
848
//------------------------------------------------------------------------------ multiply unit
849
 
850
reg [17:0] mult_a;
851
always @(posedge clk or negedge rst_n) begin
852
    if(rst_n == 1'b0)               mult_a <= 18'd0;
853
 
854
    //attack
855
    else if(prepare_cnt_attack_1)   mult_a <= { 1'b0, amp[16:0] };
856
    else if(prepare_cnt_attack_4)   mult_a <= mult_result[33:16]; //amp^2
857
    else if(prepare_cnt_attack_7)   mult_a <= mult_result[33:16]; //amp^3
858
    else if(prepare_cnt_attack_10)  mult_a <= { 1'b0, attack_sum[16:0] };
859
    else if(prepare_cnt_attack_13)  mult_a <= { 1'b0, amp[16:0] };
860
    else if(prepare_cnt_attack_19)  mult_a <= { 2'b0, attack_value[15:0] };
861
 
862
    //decay
863
    else if(prepare_cnt_decay_1)    mult_a <= { 1'b0, amp[16:0] };
864
 
865
    //release
866
    else if(prepare_cnt_release_1)  mult_a <= { 1'b0, amp[16:0] };
867
 
868
    //output
869
    else if(prepare_cnt_output_5)   mult_a <= { waveform_value[16], waveform_value };
870
    else if(prepare_cnt_output_8)   mult_a <= mult_result[33:16];
871
    else if(prepare_cnt_output_11)  mult_a <= mult_result[33:16];
872
end
873
 
874
reg [17:0] mult_b;
875
always @(posedge clk or negedge rst_n) begin
876
    if(rst_n == 1'b0)               mult_b <= 18'd0;
877
 
878
    //attack
879
    else if(prepare_cnt_attack_1)   mult_b <= { 1'b0, amp[16:0] };
880
    else if(prepare_cnt_attack_7)   mult_b <= 18'd30392; //7.42/16 *fixedpoint
881
    else if(prepare_cnt_attack_10)  mult_b <= 18'h2E6E2; //-17.57/16 *fixedpoint
882
    else if(prepare_cnt_attack_13)  mult_b <= 18'd43950; //10.73/16 *fixedpoint
883
    else if(prepare_cnt_attack_19)  mult_b <= { 1'b0, attack_sum[16:0] };
884
 
885
    //decay
886
    else if(prepare_cnt_decay_1)    mult_b <= { 1'b0, decay_mul };
887
 
888
    //release
889
    else if(prepare_cnt_release_1)  mult_b <= { 1'b0, release_mul };
890
 
891
    //output
892
    else if(prepare_cnt_output_5)   mult_b <= { 1'b0, volume_frac };
893
    else if(prepare_cnt_output_8)   mult_b <= { 1'b0, step_amp };
894
    else if(prepare_cnt_output_11)  mult_b <= { 1'b0, tremolo_coeff };
895
end
896
 
897
wire [35:0] mult_result;
898
 
899
simple_mult #(
900
    .widtha (18),
901
    .widthb (18),
902
    .widthp (36)
903
)
904
operator_mult_inst (
905
    .clk    (clk),
906
 
907
    .a      (mult_a),      //input [17:0]
908
    .b      (mult_b),      //input [17:0]
909
 
910
    .out    (mult_result)  //output [35:0]
911
);
912
 
913
reg [35:0] mult_result_reg;
914
always @(posedge clk or negedge rst_n) begin
915
    if(rst_n == 1'b0)   mult_result_reg <= 36'd0;
916
    else                mult_result_reg <= mult_result;
917
end
918
 
919
reg [16:0] step_amp;
920
always @(posedge clk or negedge rst_n) begin
921
    if(rst_n == 1'b0)                       step_amp <= 17'd0;
922
 
923
    else if(attack_step_finished)           step_amp <= 17'd65536;
924
    else if(attack_step_update)             step_amp <= amp[16:0];
925
 
926
    else if(decay_step_finish_to_sustain)   step_amp <= sustain_amp;
927
    else if(decay_step_active)              step_amp <= amp[16:0];
928
 
929
    else if(release_step_finish)            step_amp <= 17'd0;
930
    else if(release_step_active)            step_amp <= amp[16:0];
931
end
932
 
933
reg [19:0] amp;
934
always @(posedge clk or negedge rst_n) begin
935
    if(rst_n == 1'b0)                                           amp <= 20'd0;
936
 
937
    //attack
938
    else if(prepare_cnt_attack_27)                              amp <= amp + attack_amp;
939
    else if(prepare_cnt_attack_28 && amp > 20'd65536)           amp <= 20'd65537;
940
    else if(attack_step_finished)                               amp <= 20'd65536;
941
 
942
    //decay
943
    else if(prepare_cnt_decay_4 && amp > { 3'b0, sustain_amp }) amp <= mult_result[35:16];
944
    else if(decay_step_finish_to_sustain)                       amp <= { 3'b0, sustain_amp };
945
 
946
    //release
947
    else if(prepare_cnt_release_4 && amp > 20'd1)               amp <= mult_result[35:16];
948
    else if(release_step_finish)                                amp <= 20'd0;
949
end
950
 
951
//------------------------------------------------------------------------------ waveform
952
 
953
//mfbi: *2^(feedback+8)
954
//(lastcval + cval)*2^(feedback+7)
955
 
956
//input [2:0]   feedback,
957
//input [15:0]  modulator,
958
//      [25:0]  wfpos
959
 
960
wire [16:0] waveform_wfpos_plus_modulator = { 6'd0, wfpos[25:16] } + modulator;
961
wire [16:0] waveform_feedback_sum         = cval_last + cval;
962
wire [25:0] waveform_feedback_modulator =
963
    (feedback == 3'd1)?     { 2'b0, waveform_feedback_sum[15:0], 8'd0 } :
964
    (feedback == 3'd2)?     { 1'b0, waveform_feedback_sum[15:0], 9'd0 } :
965
    (feedback == 3'd3)?     {       waveform_feedback_sum[15:0], 10'd0 } :
966
    (feedback == 3'd4)?     {       waveform_feedback_sum[14:0], 11'd0 } :
967
    (feedback == 3'd5)?     {       waveform_feedback_sum[13:0], 12'd0 } :
968
    (feedback == 3'd6)?     {       waveform_feedback_sum[12:0], 13'd0 } :
969
                            {       waveform_feedback_sum[11:0], 14'd0 };
970
 
971
reg [25:0] waveform_feedback_modulator_reg;
972
always @(posedge clk or negedge rst_n) begin
973
    if(rst_n == 1'b0)   waveform_feedback_modulator_reg <= 26'd0;
974
    else                waveform_feedback_modulator_reg <= waveform_feedback_modulator;
975
end
976
 
977
wire [26:0] waveform_wfpos_plus_feedback = wfpos + waveform_feedback_modulator_reg;
978
 
979
reg [9:0] waveform_counter;
980
always @(posedge clk or negedge rst_n) begin
981
    if(rst_n == 1'b0)                                   waveform_counter <= 10'd0;
982
    else if(prepare_cnt_output_1 && feedback == 3'd0)   waveform_counter <= waveform_wfpos_plus_modulator[9:0];
983
    else if(prepare_cnt_output_1)                       waveform_counter <= waveform_wfpos_plus_feedback[25:16];
984
end
985
 
986
wire waveform_counter_reverse = (waveform_counter >= 10'd256 && waveform_counter <= 10'd511) || waveform_counter >= 10'd768;
987
 
988
reg [7:0] waveform_address;
989
always @(posedge clk or negedge rst_n) begin
990
    if(rst_n == 1'b0)                                                                   waveform_address <= 8'd0;
991
    else if(prepare_cnt_output_2 && wave_select == 2'd1 && waveform_counter >= 10'd512) waveform_address <= 8'd0;
992
    else if(prepare_cnt_output_2 && wave_select == 2'd3 && waveform_counter_reverse)    waveform_address <= 8'd0;
993
    else if(prepare_cnt_output_2 && waveform_counter_reverse)                           waveform_address <= 8'd255 - waveform_counter[7:0];
994
    else if(prepare_cnt_output_2)                                                       waveform_address <= waveform_counter[7:0];
995
end
996
 
997
wire [15:0] waveform_q_negative = -wform_decrel_q;
998
 
999
reg [16:0] waveform_value;
1000
always @(posedge clk or negedge rst_n) begin
1001
    if(rst_n == 1'b0)                                                                   waveform_value <= 17'd0;
1002
    else if(prepare_cnt_output_4 && wave_select == 2'd0 && waveform_counter >= 10'd512) waveform_value <= { 1'b1, waveform_q_negative };
1003
    else if(prepare_cnt_output_4)                                                       waveform_value <= { 1'b0, wform_decrel_q };
1004
end
1005
 
1006
//------------------------------------------------------------------------------ tremolo
1007
 
1008
//TREMTAB_SIZE * TREM_FREQ * FIXED_LFO / f_s = 34270
1009
reg [29:0] tremolo_pos;
1010
always @(posedge clk or negedge rst_n) begin
1011
    if(rst_n == 1'b0)                                               tremolo_pos <= 30'd0;
1012
    else if(prepare_cnt_output_1)                                   tremolo_pos <= tremolo_pos + 30'd34270;
1013
    else if(prepare_cnt_output_2 && tremolo_pos[29:24] == 6'd53)    tremolo_pos <= { 6'd0, tremolo_pos[23:0] };
1014
end
1015
 
1016
wire [6:0] tremolo_idx =
1017
    (tremolo_depth    && tremolo_pos[29:24] <= 6'd13)?      7'd13 - { 1'b0, tremolo_pos[29:24] } :
1018
    (tremolo_depth    && tremolo_pos[29:24] <= 6'd40)?      { 1'b0, tremolo_pos[29:24] } - 7'd14 :
1019
    (tremolo_depth    && tremolo_pos[29:24] <= 6'd52)?      7'd66 - { 1'b0, tremolo_pos[29:24] } :
1020
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd1)?       7'd3 :
1021
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd5)?       7'd2 :
1022
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd9)?       7'd1 :
1023
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd17)?      7'd0 :
1024
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd21)?      7'd1 :
1025
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd25)?      7'd2 :
1026
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd29)?      7'd3 :
1027
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd33)?      7'd4 :
1028
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd37)?      7'd5 :
1029
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd42)?      7'd6 :
1030
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd46)?      7'd5 :
1031
    (~(tremolo_depth) && tremolo_pos[29:24] <= 6'd50)?      7'd4 :
1032
                                                            7'd3;
1033
 
1034
wire [16:0] tremolo_48db =
1035
    (tremolo_idx[4:0] == 5'd26)?    17'h9308 :
1036
    (tremolo_idx[4:0] == 5'd25)?    17'h9633 :
1037
    (tremolo_idx[4:0] == 5'd24)?    17'h9970 :
1038
    (tremolo_idx[4:0] == 5'd23)?    17'h9CBF :
1039
    (tremolo_idx[4:0] == 5'd22)?    17'hA020 :
1040
    (tremolo_idx[4:0] == 5'd21)?    17'hA394 :
1041
    (tremolo_idx[4:0] == 5'd20)?    17'hA71B :
1042
    (tremolo_idx[4:0] == 5'd19)?    17'hAAB5 :
1043
    (tremolo_idx[4:0] == 5'd18)?    17'hAE63 :
1044
    (tremolo_idx[4:0] == 5'd17)?    17'hB225 :
1045
    (tremolo_idx[4:0] == 5'd16)?    17'hB5FC :
1046
    (tremolo_idx[4:0] == 5'd15)?    17'hB9E8 :
1047
    (tremolo_idx[4:0] == 5'd14)?    17'hBDEA :
1048
    (tremolo_idx[4:0] == 5'd13)?    17'hC203 :
1049
    (tremolo_idx[4:0] == 5'd12)?    17'hC631 :
1050
    (tremolo_idx[4:0] == 5'd11)?    17'hCA77 :
1051
    (tremolo_idx[4:0] == 5'd10)?    17'hCED4 :
1052
    (tremolo_idx[4:0] == 5'd9)?     17'hD34A :
1053
    (tremolo_idx[4:0] == 5'd8)?     17'hD7D8 :
1054
    (tremolo_idx[4:0] == 5'd7)?     17'hDC7F :
1055
    (tremolo_idx[4:0] == 5'd6)?     17'hE140 :
1056
    (tremolo_idx[4:0] == 5'd5)?     17'hE61B :
1057
    (tremolo_idx[4:0] == 5'd4)?     17'hEB10 :
1058
    (tremolo_idx[4:0] == 5'd3)?     17'hF022 :
1059
    (tremolo_idx[4:0] == 5'd2)?     17'hF54F :
1060
    (tremolo_idx[4:0] == 5'd1)?     17'hFA99 :
1061
                                    17'h10000;
1062
 
1063
wire [16:0] tremolo_12db =
1064
    (tremolo_idx[4:0] == 5'd6)?     17'hDEDC :
1065
    (tremolo_idx[4:0] == 5'd5)?     17'hE411 :
1066
    (tremolo_idx[4:0] == 5'd4)?     17'hE966 :
1067
    (tremolo_idx[4:0] == 5'd3)?     17'hEEDB :
1068
    (tremolo_idx[4:0] == 5'd2)?     17'hF470 :
1069
    (tremolo_idx[4:0] == 5'd1)?     17'hFA27 :
1070
                                    17'h10000;
1071
 
1072
reg [16:0] tremolo_coeff;
1073
always @(posedge clk or negedge rst_n) begin
1074
    if(rst_n == 1'b0)                               tremolo_coeff <= 17'd0;
1075
    else if(prepare_cnt_output_3 && ~(tremolo))     tremolo_coeff <= 17'h10000;
1076
    else if(prepare_cnt_output_3 && tremolo_depth)  tremolo_coeff <= tremolo_48db;
1077
    else if(prepare_cnt_output_3)                   tremolo_coeff <= tremolo_12db;
1078
end
1079
 
1080
//------------------------------------------------------------------------------
1081
 
1082
wire [15:0] cval_shifted =
1083
    (volume_int == 4'd1)?   { 1'b0,  cval[15:1] } :
1084
    (volume_int == 4'd2)?   { 2'b0,  cval[15:2] } :
1085
    (volume_int == 4'd3)?   { 3'b0,  cval[15:3] } :
1086
    (volume_int == 4'd4)?   { 4'b0,  cval[15:4] } :
1087
    (volume_int == 4'd5)?   { 5'b0,  cval[15:5] } :
1088
    (volume_int == 4'd6)?   { 6'b0,  cval[15:6] } :
1089
    (volume_int == 4'd7)?   { 7'b0,  cval[15:7] } :
1090
    (volume_int == 4'd8)?   { 8'b0,  cval[15:8] } :
1091
    (volume_int == 4'd9)?   { 9'b0,  cval[15:9] } :
1092
    (volume_int == 4'd10)?  { 10'b0, cval[15:10] } :
1093
    (volume_int == 4'd11)?  { 11'b0, cval[15:11] } :
1094
    (volume_int == 4'd12)?  { 12'b0, cval[15:12] } :
1095
    (volume_int == 4'd13)?  { 13'b0, cval[15:13] } :
1096
                                     cval;
1097
 
1098
reg [15:0] cval_last;
1099
always @(posedge clk or negedge rst_n) begin
1100
    if(rst_n == 1'b0)               cval_last <= 16'd0;
1101
    else if(prepare_cnt_output_13)  cval_last <= cval;
1102
end
1103
 
1104
always @(posedge clk or negedge rst_n) begin
1105
    if(rst_n == 1'b0)               cval <= 16'd0;
1106
    else if(prepare_cnt_output_14)  cval <= mult_result[33:18];
1107
    else if(prepare_cnt_output_15)  cval <= (state == S_OFF)? 16'd0 : cval_shifted;
1108
end
1109
 
1110
//------------------------------------------------------------------------------
1111
 
1112
// synthesis translate_off
1113
wire _unused_ok = &{ 1'b0,
1114
    release_steps[1:0], decay_steps[1:0], mult_result_reg[15:0],
1115
    waveform_wfpos_plus_modulator[16:10], waveform_feedback_sum[16],
1116
    waveform_wfpos_plus_feedback[26], waveform_wfpos_plus_feedback[15:0],
1117
    tremolo_idx[6:5],
1118
    1'b0 };
1119
// synthesis translate_on
1120
 
1121
//------------------------------------------------------------------------------
1122
 
1123
endmodule

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