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alfik |
# TCL File Generated by Component Editor 13.1
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# Fri Jan 17 20:02:44 CET 2014
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# DO NOT MODIFY
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#
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# vga "vga" v1.0
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# 2014.01.17.20:02:44
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#
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#
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#
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# request TCL package from ACDS 13.1
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#
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package require -exact qsys 13.1
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#
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# module vga
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME vga
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP ao486
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME vga
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property ANALYZE_HDL AUTO
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL vga
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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add_fileset_file vga.v VERILOG PATH vga.v TOP_LEVEL_FILE
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point sys
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#
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add_interface sys avalon end
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set_interface_property sys addressUnits WORDS
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set_interface_property sys associatedClock clock_sink
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set_interface_property sys associatedReset reset_sink
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set_interface_property sys bitsPerSymbol 8
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set_interface_property sys burstOnBurstBoundariesOnly false
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set_interface_property sys burstcountUnits WORDS
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set_interface_property sys explicitAddressSpan 0
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set_interface_property sys holdTime 0
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set_interface_property sys linewrapBursts false
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set_interface_property sys maximumPendingReadTransactions 0
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set_interface_property sys readLatency 0
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set_interface_property sys readWaitTime 1
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set_interface_property sys setupTime 0
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set_interface_property sys timingUnits Cycles
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set_interface_property sys writeWaitTime 0
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set_interface_property sys ENABLED true
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set_interface_property sys EXPORT_OF ""
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set_interface_property sys PORT_NAME_MAP ""
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set_interface_property sys CMSIS_SVD_VARIABLES ""
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set_interface_property sys SVD_ADDRESS_GROUP ""
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add_interface_port sys sys_address address Input 8
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add_interface_port sys sys_read read Input 1
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add_interface_port sys sys_readdata readdata Output 32
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add_interface_port sys sys_write write Input 1
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add_interface_port sys sys_writedata writedata Input 32
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set_interface_assignment sys embeddedsw.configuration.isFlash 0
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set_interface_assignment sys embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment sys embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment sys embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point io_b
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#
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add_interface io_b avalon end
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set_interface_property io_b addressUnits WORDS
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set_interface_property io_b associatedClock clock_sink
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set_interface_property io_b associatedReset reset_sink
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set_interface_property io_b bitsPerSymbol 8
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set_interface_property io_b burstOnBurstBoundariesOnly false
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set_interface_property io_b burstcountUnits WORDS
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set_interface_property io_b explicitAddressSpan 0
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set_interface_property io_b holdTime 0
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set_interface_property io_b linewrapBursts false
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set_interface_property io_b maximumPendingReadTransactions 0
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set_interface_property io_b readLatency 0
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set_interface_property io_b readWaitTime 1
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set_interface_property io_b setupTime 0
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set_interface_property io_b timingUnits Cycles
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set_interface_property io_b writeWaitTime 0
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set_interface_property io_b ENABLED true
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set_interface_property io_b EXPORT_OF ""
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set_interface_property io_b PORT_NAME_MAP ""
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set_interface_property io_b CMSIS_SVD_VARIABLES ""
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set_interface_property io_b SVD_ADDRESS_GROUP ""
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add_interface_port io_b io_b_address address Input 4
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add_interface_port io_b io_b_read read Input 1
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add_interface_port io_b io_b_readdata readdata Output 8
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add_interface_port io_b io_b_write write Input 1
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add_interface_port io_b io_b_writedata writedata Input 8
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set_interface_assignment io_b embeddedsw.configuration.isFlash 0
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set_interface_assignment io_b embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment io_b embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment io_b embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point io_c
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#
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add_interface io_c avalon end
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set_interface_property io_c addressUnits WORDS
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set_interface_property io_c associatedClock clock_sink
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set_interface_property io_c associatedReset reset_sink
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set_interface_property io_c bitsPerSymbol 8
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set_interface_property io_c burstOnBurstBoundariesOnly false
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set_interface_property io_c burstcountUnits WORDS
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set_interface_property io_c explicitAddressSpan 0
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set_interface_property io_c holdTime 0
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set_interface_property io_c linewrapBursts false
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set_interface_property io_c maximumPendingReadTransactions 0
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set_interface_property io_c readLatency 0
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set_interface_property io_c readWaitTime 1
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set_interface_property io_c setupTime 0
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set_interface_property io_c timingUnits Cycles
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set_interface_property io_c writeWaitTime 0
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set_interface_property io_c ENABLED true
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set_interface_property io_c EXPORT_OF ""
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set_interface_property io_c PORT_NAME_MAP ""
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set_interface_property io_c CMSIS_SVD_VARIABLES ""
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set_interface_property io_c SVD_ADDRESS_GROUP ""
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add_interface_port io_c io_c_address address Input 4
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add_interface_port io_c io_c_read read Input 1
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add_interface_port io_c io_c_readdata readdata Output 8
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add_interface_port io_c io_c_write write Input 1
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add_interface_port io_c io_c_writedata writedata Input 8
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set_interface_assignment io_c embeddedsw.configuration.isFlash 0
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set_interface_assignment io_c embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment io_c embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment io_c embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point io_d
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#
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add_interface io_d avalon end
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set_interface_property io_d addressUnits WORDS
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set_interface_property io_d associatedClock clock_sink
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set_interface_property io_d associatedReset reset_sink
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set_interface_property io_d bitsPerSymbol 8
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set_interface_property io_d burstOnBurstBoundariesOnly false
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set_interface_property io_d burstcountUnits WORDS
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set_interface_property io_d explicitAddressSpan 0
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set_interface_property io_d holdTime 0
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set_interface_property io_d linewrapBursts false
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set_interface_property io_d maximumPendingReadTransactions 0
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set_interface_property io_d readLatency 0
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set_interface_property io_d readWaitTime 1
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set_interface_property io_d setupTime 0
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set_interface_property io_d timingUnits Cycles
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set_interface_property io_d writeWaitTime 0
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set_interface_property io_d ENABLED true
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set_interface_property io_d EXPORT_OF ""
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set_interface_property io_d PORT_NAME_MAP ""
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set_interface_property io_d CMSIS_SVD_VARIABLES ""
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set_interface_property io_d SVD_ADDRESS_GROUP ""
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add_interface_port io_d io_d_address address Input 4
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add_interface_port io_d io_d_read read Input 1
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add_interface_port io_d io_d_readdata readdata Output 8
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add_interface_port io_d io_d_write write Input 1
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add_interface_port io_d io_d_writedata writedata Input 8
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set_interface_assignment io_d embeddedsw.configuration.isFlash 0
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set_interface_assignment io_d embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment io_d embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment io_d embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point mem
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#
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add_interface mem avalon end
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set_interface_property mem addressUnits WORDS
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set_interface_property mem associatedClock clock_sink
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set_interface_property mem associatedReset reset_sink
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set_interface_property mem bitsPerSymbol 8
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set_interface_property mem burstOnBurstBoundariesOnly false
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set_interface_property mem burstcountUnits WORDS
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set_interface_property mem explicitAddressSpan 0
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set_interface_property mem holdTime 0
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set_interface_property mem linewrapBursts false
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set_interface_property mem maximumPendingReadTransactions 0
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set_interface_property mem readLatency 0
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set_interface_property mem readWaitTime 1
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set_interface_property mem setupTime 0
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set_interface_property mem timingUnits Cycles
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set_interface_property mem writeWaitTime 0
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set_interface_property mem ENABLED true
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set_interface_property mem EXPORT_OF ""
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set_interface_property mem PORT_NAME_MAP ""
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set_interface_property mem CMSIS_SVD_VARIABLES ""
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set_interface_property mem SVD_ADDRESS_GROUP ""
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add_interface_port mem mem_address address Input 17
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add_interface_port mem mem_read read Input 1
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add_interface_port mem mem_readdata readdata Output 8
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add_interface_port mem mem_write write Input 1
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add_interface_port mem mem_writedata writedata Input 8
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set_interface_assignment mem embeddedsw.configuration.isFlash 0
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set_interface_assignment mem embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment mem embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment mem embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk_26 clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_n reset_n Input 1
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#
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# connection point export_vga
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| 266 |
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#
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add_interface export_vga conduit end
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set_interface_property export_vga associatedClock clock_sink
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set_interface_property export_vga associatedReset reset_sink
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| 270 |
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set_interface_property export_vga ENABLED true
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set_interface_property export_vga EXPORT_OF ""
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set_interface_property export_vga PORT_NAME_MAP ""
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| 273 |
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set_interface_property export_vga CMSIS_SVD_VARIABLES ""
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set_interface_property export_vga SVD_ADDRESS_GROUP ""
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add_interface_port export_vga vga_clock export Output 1
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add_interface_port export_vga vga_sync_n export Output 1
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| 278 |
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add_interface_port export_vga vga_blank_n export Output 1
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| 279 |
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add_interface_port export_vga vga_horiz_sync export Output 1
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| 280 |
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add_interface_port export_vga vga_vert_sync export Output 1
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| 281 |
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add_interface_port export_vga vga_r export Output 8
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| 282 |
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add_interface_port export_vga vga_g export Output 8
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| 283 |
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add_interface_port export_vga vga_b export Output 8
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