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[/] [ao486/] [trunk/] [sim/] [iverilog/] [floppy/] [tb_floppy.v] - Blame information for rev 2

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`timescale 1 ps / 1 ps
 
module tb_floppy();
 
reg clk;
reg rst_n;
 
wire        dma_floppy_req;
reg         dma_floppy_ack                  = 1'b0;
reg         dma_floppy_terminal             = 1'b0;
reg  [7:0]  dma_floppy_readdata             = 8'd0;
wire [7:0]  dma_floppy_writedata;
 
//irq
wire        interrupt;
 
//avalon slave
reg  [2:0]  io_address                      = 3'd0;
reg         io_read                         = 1'b0;
wire [7:0]  io_readdata;
reg         io_write                        = 1'b0;
reg  [7:0]  io_writedata                    = 8'd0;
 
//ide shared port 0x3F6
wire       ide_3f6_read;
reg  [7:0] ide_3f6_readdata                 = 8'd0;
wire       ide_3f6_write;
wire [7:0] ide_3f6_writedata;
 
//master to control sd
wire [31:0] sd_master_address;
reg         sd_master_waitrequest           = 1'b0;
wire        sd_master_read;
reg         sd_master_readdatavalid         = 1'b0;
reg  [31:0] sd_master_readdata              = 32'd0;
wire        sd_master_write;
wire [31:0] sd_master_writedata;
 
//slave for sd
reg  [8:0]  sd_slave_address                = 9'd0;
reg         sd_slave_read                   = 1'b0;
wire [7:0]  sd_slave_readdata;
reg         sd_slave_write                  = 1'b0;
reg  [7:0]  sd_slave_writedata              = 8'd0;
 
//slave for management
reg  [3:0]  mgmt_address                    = 4'd0;
reg         mgmt_read                       = 1'b0;
wire [31:0] mgmt_readdata;
reg         mgmt_write                      = 1'b0;
reg  [31:0] mgmt_writedata                  = 32'd0;
 
 
floppy floppy_inst(
    .clk                        (clk),
    .rst_n                      (rst_n),
 
    //dma
    .dma_floppy_req             (dma_floppy_req),         //output
    .dma_floppy_ack             (dma_floppy_ack),         //input
    .dma_floppy_terminal        (dma_floppy_terminal),    //input
    .dma_floppy_readdata        (dma_floppy_readdata),    //input [7:0]
    .dma_floppy_writedata       (dma_floppy_writedata),   //output [7:0]
 
    //irq
    .interrupt                  (interrupt),              //output
 
    //avalon slave
    .io_address                 (io_address),     //input [2:0]
    .io_read                    (io_read),        //input
    .io_readdata                (io_readdata),    //output [7:0]
    .io_write                   (io_write),       //input
    .io_writedata               (io_writedata),   //input [7:0]
 
    //ide shared port 0x3F6
    .ide_3f6_read               (ide_3f6_read),           //output
    .ide_3f6_readdata           (ide_3f6_readdata),       //input [7:0]
    .ide_3f6_write              (ide_3f6_write),          //output
    .ide_3f6_writedata          (ide_3f6_writedata),      //output [7:0]
 
    //master to control sd
    .sd_master_address          (sd_master_address),          //output [31:0]
    .sd_master_waitrequest      (sd_master_waitrequest),      //input
    .sd_master_read             (sd_master_read),             //output
    .sd_master_readdatavalid    (sd_master_readdatavalid),    //input
    .sd_master_readdata         (sd_master_readdata),         //input [31:0]
    .sd_master_write            (sd_master_write),            //output
    .sd_master_writedata        (sd_master_writedata),        //output [31:0]
 
    //slave for sd
    .sd_slave_address           (sd_slave_address),           //input [8:0]
    .sd_slave_read              (sd_slave_read),              //input
    .sd_slave_readdata          (sd_slave_readdata),          //output [7:0]
    .sd_slave_write             (sd_slave_write),             //input
    .sd_slave_writedata         (sd_slave_writedata),         //input [7:0]
 
    //slave for management
    .mgmt_address               (mgmt_address),           //input [3:0]
    .mgmt_read                  (mgmt_read),              //input
    .mgmt_readdata              (mgmt_readdata),          //output [31:0]
    .mgmt_write                 (mgmt_write),             //input
    .mgmt_writedata             (mgmt_writedata)          //input [31:0]
);
 
 
initial begin
    clk = 1'b0;
    forever #5 clk = ~clk;
end
 
`define WRITE_MGMT(addr, data)  \
    mgmt_write        = 1'b1;   \
    mgmt_address      = addr;   \
    mgmt_writedata    = data;   \
    #10;                        \
    mgmt_write        = 1'b0;
 
`define WRITE_IO(addr, data)  \
    io_write        = 1'b1;   \
    io_address      = addr;   \
    io_writedata    = data;   \
    #10;                      \
    io_write        = 1'b0;
 
`define READ_IO(addr)        \
    io_read         = 1'b1;  \
    io_address      = addr;  \
    #10;                     \
    io_read         = 1'b0;
 
//------------------------------------------------------------------------------ read data
/*
integer read_count = 0;
 
always @(posedge clk) begin
    if(sd_master_address == 32'd4 && sd_master_read) begin
        sd_master_readdatavalid <= 1'b1;
        sd_master_readdata <= 3'd1;
    end
    else if(sd_master_address == 32'd12 && sd_master_write && sd_master_writedata == 32'd2) begin
        #22;
 
        for(read_count=0; read_count < 512; read_count = read_count+1) begin
            sd_slave_address = read_count;
            sd_slave_write   = 1;
            sd_slave_writedata = read_count;
            #10;
        end
 
        sd_slave_address = 0;
        sd_slave_write   = 0;
        sd_slave_writedata = 0;
    end
    else begin
        sd_master_readdatavalid <= 1'b0;
        sd_master_readdata <= 3'd0;
    end
end
 
integer dma_count = 0;
 
always @(posedge clk) begin
    if(dma_floppy_req) begin
        dma_floppy_ack <= 1'b1;
        dma_count = dma_count + 1;
    end
    else begin
        dma_floppy_ack <= 1'b0;
    end
 
    if(dma_count == 1000) begin
        dma_floppy_terminal <= 1'b1;
 
        #10001;
        dma_count = 0;
 
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
    end
    else begin
        dma_floppy_terminal <= 1'b0;
    end
end
*/
 
//------------------------------------------------------------------------------ write data
 
/*
integer read_count = 0;
 
always @(posedge clk) begin
    if(sd_master_address == 32'd4 && sd_master_read) begin
        sd_master_readdatavalid <= 1'b1;
        sd_master_readdata <= 3'd1;
    end
    else if(sd_master_address == 32'd12 && sd_master_write && sd_master_writedata == 32'd3) begin
        #22;
 
        for(read_count=0; read_count < 512; read_count = read_count+1) begin
            sd_slave_address = read_count;
            sd_slave_read   = 1;
            #10;
        end
 
        sd_slave_address = 0;
        sd_slave_read   = 0;
        sd_slave_writedata = 0;
    end
    else begin
        sd_master_readdatavalid <= 1'b0;
        sd_master_readdata <= 3'd0;
    end
end
 
integer dma_count = 0;
 
always @(posedge clk) begin
    if(dma_floppy_req) begin
        dma_floppy_ack <= 1'b1;
        dma_floppy_readdata <= dma_count;
        dma_count = dma_count + 1;
    end
    else begin
        dma_floppy_ack <= 1'b0;
    end
 
    if(dma_count == 1000) begin
        dma_floppy_terminal <= 1'b1;
 
 
        #10001;
        dma_count = 0;
 
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
 
    end
    else begin
        dma_floppy_terminal <= 1'b0;
    end
end
*/
 
//------------------------------------------------------------------------------ format
 
integer read_count = 0;
 
always @(posedge clk) begin
    if(sd_master_address == 32'd4 && sd_master_read) begin
        sd_master_readdatavalid <= 1'b1;
        sd_master_readdata <= 3'd1;
    end
    else if(sd_master_address == 32'd12 && sd_master_write && sd_master_writedata == 32'd3) begin
        #22;
 
        for(read_count=0; read_count < 512; read_count = read_count+1) begin
            sd_slave_address = read_count;
            sd_slave_read   = 1;
            #10;
        end
 
        sd_slave_address = 0;
        sd_slave_read   = 0;
        sd_slave_writedata = 0;
    end
    else begin
        sd_master_readdatavalid <= 1'b0;
        sd_master_readdata <= 3'd0;
    end
end
 
 
integer dma_count = 0;
 
always @(posedge clk) begin
    if(dma_floppy_req) begin
        dma_floppy_ack <= 1'b1;
        dma_floppy_readdata <=
            ((dma_count % 4) == 0)?     8'd30 : //cylinder
            ((dma_count % 4) == 1)?     8'd01 : //head
            ((dma_count % 4) == 2)?     8'd12 : //sector
                                        8'd02;  //N
        dma_count = dma_count + 1;
    end
    else begin
        dma_floppy_ack <= 1'b0;
    end
 
    if(dma_count == 8) begin
        #11;
        dma_floppy_terminal <= 1'b1;
        dma_floppy_ack = 1'b0;
 
        #10001;
        dma_count = 0;
 
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
        `READ_IO(4'h5)
 
    end
    else begin
        dma_floppy_terminal <= 1'b0;
    end
end
 
integer finished = 0;
 
reg [255:0] dumpfile_name;
initial begin
    if( $value$plusargs("dumpfile=%s", dumpfile_name) == 0 ) begin
        dumpfile_name = "default.vcd";
    end
 
    $dumpfile(dumpfile_name);
    $dumpvars(0);
    $dumpon();
 
    $display("START");
 
    rst_n = 1'b0;
    #10 rst_n = 1'b1;
 
    //initialize drive
    // 0x00.[0]:      media present
    // 0x01.[0]:      media writeprotect
    // 0x02.[7:0]:    media cylinders
    // 0x03.[7:0]:    media sectors per track
    // 0x04.[31:0]:   media total sector count
    // 0x05.[1:0]:    media heads
    // 0x06.[31:0]:   media sd base
    // 0x07.[15:0]:   media wait cycles
    // 0x08.[15:0]:   media wait rate 0
    // 0x09.[15:0]:   media wait rate 1
    // 0x0A.[15:0]:   media wait rate 2
    // 0x0B.[15:0]:   media wait rate 3
    // 0x0C.[7:0]:    media type: 8'h20 none; 8'h00 old; 8'hC0 720k; 8'h80 1_44M; 8'h40 2_88M
 
    `WRITE_MGMT(4'h0, 1)
    `WRITE_MGMT(4'h1, 0)
    `WRITE_MGMT(4'h2, 80)
    `WRITE_MGMT(4'h3, 18)
    `WRITE_MGMT(4'h4, 2880)
    `WRITE_MGMT(4'h5, 2)
    `WRITE_MGMT(4'h6, 32'h0A0B0C0D)
    `WRITE_MGMT(4'h7, 200)
    `WRITE_MGMT(4'h8, 1000)
    `WRITE_MGMT(4'h9, 1666)
    `WRITE_MGMT(4'hA, 2000)
    `WRITE_MGMT(4'hB, 500)
    `WRITE_MGMT(4'hC, 8'h80)
 
    #10;
 
    //enable motor
    `WRITE_IO(3'd2, 8'h1C)
 
    //------------------------------------------------------------------------------ read data
    /*
    //cmd: READ
    `WRITE_IO(3'd5, 8'hC6)
    `WRITE_IO(3'd5, 8'h04)
    `WRITE_IO(3'd5, 8'h12) //C
    `WRITE_IO(3'd5, 8'h01) //H
    `WRITE_IO(3'd5, 8'h05) //R
    `WRITE_IO(3'd5, 8'h02) //N
    `WRITE_IO(3'd5, 8'h08) //EOT
    `WRITE_IO(3'd5, 8'hFF) //GPL
    `WRITE_IO(3'd5, 8'hFF) //DTL
    */
 
    //------------------------------------------------------------------------------ write data
    /*
    //cmd: WRITE
    `WRITE_IO(3'd5, 8'hC5)
    `WRITE_IO(3'd5, 8'h04)
    `WRITE_IO(3'd5, 8'h12) //C
    `WRITE_IO(3'd5, 8'h01) //H
    `WRITE_IO(3'd5, 8'h05) //R
    `WRITE_IO(3'd5, 8'h02) //N
    `WRITE_IO(3'd5, 8'h08) //EOT
    `WRITE_IO(3'd5, 8'hFF) //GPL
    `WRITE_IO(3'd5, 8'hFF) //DTL
    */
 
    //------------------------------------------------------------------------------ format
    //cmd: FORMAT
    `WRITE_IO(3'd5, 8'h4D)
    `WRITE_IO(3'd5, 8'h04)
    `WRITE_IO(3'd5, 8'h02) //N
    `WRITE_IO(3'd5, 8'd18) //SC
    `WRITE_IO(3'd5, 8'hFF) //GPL
    `WRITE_IO(3'd5, 8'hAB) //D
 
    while(finished == 0) begin
        if($time > 100000) $finish_and_return(-1);
        #10;
 
        //$dumpflush();
    end
 
    #60;
 
    $dumpoff();
    $finish_and_return(0);
end
 
endmodule

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[/] [ao486/] [trunk/] [sim/] [iverilog/] [floppy/] [tb_floppy.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik
2			`timescale 1 ps / 1 ps
3
4			`module tb_floppy();`
5
6			`reg clk;`
7			`reg rst_n;`
8
9			`wire dma_floppy_req;`
10			`reg dma_floppy_ack = 1'b0;`
11			`reg dma_floppy_terminal = 1'b0;`
12			`reg [7:0] dma_floppy_readdata = 8'd0;`
13			`wire [7:0] dma_floppy_writedata;`
14
15			`//irq`
16			`wire interrupt;`
17
18			`//avalon slave`
19			`reg [2:0] io_address = 3'd0;`
20			`reg io_read = 1'b0;`
21			`wire [7:0] io_readdata;`
22			`reg io_write = 1'b0;`
23			`reg [7:0] io_writedata = 8'd0;`
24
25			`//ide shared port 0x3F6`
26			`wire ide_3f6_read;`
27			`reg [7:0] ide_3f6_readdata = 8'd0;`
28			`wire ide_3f6_write;`
29			`wire [7:0] ide_3f6_writedata;`
30
31			`//master to control sd`
32			`wire [31:0] sd_master_address;`
33			`reg sd_master_waitrequest = 1'b0;`
34			`wire sd_master_read;`
35			`reg sd_master_readdatavalid = 1'b0;`
36			`reg [31:0] sd_master_readdata = 32'd0;`
37			`wire sd_master_write;`
38			`wire [31:0] sd_master_writedata;`
39
40			`//slave for sd`
41			`reg [8:0] sd_slave_address = 9'd0;`
42			`reg sd_slave_read = 1'b0;`
43			`wire [7:0] sd_slave_readdata;`
44			`reg sd_slave_write = 1'b0;`
45			`reg [7:0] sd_slave_writedata = 8'd0;`
46
47			`//slave for management`
48			`reg [3:0] mgmt_address = 4'd0;`
49			`reg mgmt_read = 1'b0;`
50			`wire [31:0] mgmt_readdata;`
51			`reg mgmt_write = 1'b0;`
52			`reg [31:0] mgmt_writedata = 32'd0;`
53
54
55			`floppy floppy_inst(`
56			`.clk (clk),`
57			`.rst_n (rst_n),`
58
59			`//dma`
60			`.dma_floppy_req (dma_floppy_req), //output`
61			`.dma_floppy_ack (dma_floppy_ack), //input`
62			`.dma_floppy_terminal (dma_floppy_terminal), //input`
63			`.dma_floppy_readdata (dma_floppy_readdata), //input [7:0]`
64			`.dma_floppy_writedata (dma_floppy_writedata), //output [7:0]`
65
66			`//irq`
67			`.interrupt (interrupt), //output`
68
69			`//avalon slave`
70			`.io_address (io_address), //input [2:0]`
71			`.io_read (io_read), //input`
72			`.io_readdata (io_readdata), //output [7:0]`
73			`.io_write (io_write), //input`
74			`.io_writedata (io_writedata), //input [7:0]`
75
76			`//ide shared port 0x3F6`
77			`.ide_3f6_read (ide_3f6_read), //output`
78			`.ide_3f6_readdata (ide_3f6_readdata), //input [7:0]`
79			`.ide_3f6_write (ide_3f6_write), //output`
80			`.ide_3f6_writedata (ide_3f6_writedata), //output [7:0]`
81
82			`//master to control sd`
83			`.sd_master_address (sd_master_address), //output [31:0]`
84			`.sd_master_waitrequest (sd_master_waitrequest), //input`
85			`.sd_master_read (sd_master_read), //output`
86			`.sd_master_readdatavalid (sd_master_readdatavalid), //input`
87			`.sd_master_readdata (sd_master_readdata), //input [31:0]`
88			`.sd_master_write (sd_master_write), //output`
89			`.sd_master_writedata (sd_master_writedata), //output [31:0]`
90
91			`//slave for sd`
92			`.sd_slave_address (sd_slave_address), //input [8:0]`
93			`.sd_slave_read (sd_slave_read), //input`
94			`.sd_slave_readdata (sd_slave_readdata), //output [7:0]`
95			`.sd_slave_write (sd_slave_write), //input`
96			`.sd_slave_writedata (sd_slave_writedata), //input [7:0]`
97
98			`//slave for management`
99			`.mgmt_address (mgmt_address), //input [3:0]`
100			`.mgmt_read (mgmt_read), //input`
101			`.mgmt_readdata (mgmt_readdata), //output [31:0]`
102			`.mgmt_write (mgmt_write), //input`
103			`.mgmt_writedata (mgmt_writedata) //input [31:0]`
104			`);`
105
106
107			`initial begin`
108			`clk = 1'b0;`
109			`forever #5 clk = ~clk;`
110			`end`
111
112			`define WRITE_MGMT(addr, data) \
113			`mgmt_write = 1'b1; \`
114			`mgmt_address = addr; \`
115			`mgmt_writedata = data; \`
116			`#10; \`
117			`mgmt_write = 1'b0;`
118
119			`define WRITE_IO(addr, data) \
120			`io_write = 1'b1; \`
121			`io_address = addr; \`
122			`io_writedata = data; \`
123			`#10; \`
124			`io_write = 1'b0;`
125
126			`define READ_IO(addr) \
127			`io_read = 1'b1; \`
128			`io_address = addr; \`
129			`#10; \`
130			`io_read = 1'b0;`
131
132			`//------------------------------------------------------------------------------ read data`
133			`/*`
134			`integer read_count = 0;`
135
136			`always @(posedge clk) begin`
137			`if(sd_master_address == 32'd4 && sd_master_read) begin`
138			`sd_master_readdatavalid <= 1'b1;`
139			`sd_master_readdata <= 3'd1;`
140			`end`
141			`else if(sd_master_address == 32'd12 && sd_master_write && sd_master_writedata == 32'd2) begin`
142			`#22;`
143
144			`for(read_count=0; read_count < 512; read_count = read_count+1) begin`
145			`sd_slave_address = read_count;`
146			`sd_slave_write = 1;`
147			`sd_slave_writedata = read_count;`
148			`#10;`
149			`end`
150
151			`sd_slave_address = 0;`
152			`sd_slave_write = 0;`
153			`sd_slave_writedata = 0;`
154			`end`
155			`else begin`
156			`sd_master_readdatavalid <= 1'b0;`
157			`sd_master_readdata <= 3'd0;`
158			`end`
159			`end`
160
161			`integer dma_count = 0;`
162
163			`always @(posedge clk) begin`
164			`if(dma_floppy_req) begin`
165			`dma_floppy_ack <= 1'b1;`
166			`dma_count = dma_count + 1;`
167			`end`
168			`else begin`
169			`dma_floppy_ack <= 1'b0;`
170			`end`
171
172			`if(dma_count == 1000) begin`
173			`dma_floppy_terminal <= 1'b1;`
174
175			`#10001;`
176			`dma_count = 0;`
177
178			`READ_IO(4'h5)
179			`READ_IO(4'h5)
180			`READ_IO(4'h5)
181			`READ_IO(4'h5)
182			`READ_IO(4'h5)
183			`READ_IO(4'h5)
184			`READ_IO(4'h5)
185			`end`
186			`else begin`
187			`dma_floppy_terminal <= 1'b0;`
188			`end`
189			`end`
190			`*/`
191
192			`//------------------------------------------------------------------------------ write data`
193
194			`/*`
195			`integer read_count = 0;`
196
197			`always @(posedge clk) begin`
198			`if(sd_master_address == 32'd4 && sd_master_read) begin`
199			`sd_master_readdatavalid <= 1'b1;`
200			`sd_master_readdata <= 3'd1;`
201			`end`
202			`else if(sd_master_address == 32'd12 && sd_master_write && sd_master_writedata == 32'd3) begin`
203			`#22;`
204
205			`for(read_count=0; read_count < 512; read_count = read_count+1) begin`
206			`sd_slave_address = read_count;`
207			`sd_slave_read = 1;`
208			`#10;`
209			`end`
210
211			`sd_slave_address = 0;`
212			`sd_slave_read = 0;`
213			`sd_slave_writedata = 0;`
214			`end`
215			`else begin`
216			`sd_master_readdatavalid <= 1'b0;`
217			`sd_master_readdata <= 3'd0;`
218			`end`
219			`end`
220
221			`integer dma_count = 0;`
222
223			`always @(posedge clk) begin`
224			`if(dma_floppy_req) begin`
225			`dma_floppy_ack <= 1'b1;`
226			`dma_floppy_readdata <= dma_count;`
227			`dma_count = dma_count + 1;`
228			`end`
229			`else begin`
230			`dma_floppy_ack <= 1'b0;`
231			`end`
232
233			`if(dma_count == 1000) begin`
234			`dma_floppy_terminal <= 1'b1;`
235
236
237			`#10001;`
238			`dma_count = 0;`
239
240			`READ_IO(4'h5)
241			`READ_IO(4'h5)
242			`READ_IO(4'h5)
243			`READ_IO(4'h5)
244			`READ_IO(4'h5)
245			`READ_IO(4'h5)
246			`READ_IO(4'h5)
247
248			`end`
249			`else begin`
250			`dma_floppy_terminal <= 1'b0;`
251			`end`
252			`end`
253			`*/`
254
255			`//------------------------------------------------------------------------------ format`
256
257			`integer read_count = 0;`
258
259			`always @(posedge clk) begin`
260			`if(sd_master_address == 32'd4 && sd_master_read) begin`
261			`sd_master_readdatavalid <= 1'b1;`
262			`sd_master_readdata <= 3'd1;`
263			`end`
264			`else if(sd_master_address == 32'd12 && sd_master_write && sd_master_writedata == 32'd3) begin`
265			`#22;`
266
267			`for(read_count=0; read_count < 512; read_count = read_count+1) begin`
268			`sd_slave_address = read_count;`
269			`sd_slave_read = 1;`
270			`#10;`
271			`end`
272
273			`sd_slave_address = 0;`
274			`sd_slave_read = 0;`
275			`sd_slave_writedata = 0;`
276			`end`
277			`else begin`
278			`sd_master_readdatavalid <= 1'b0;`
279			`sd_master_readdata <= 3'd0;`
280			`end`
281			`end`
282
283
284			`integer dma_count = 0;`
285
286			`always @(posedge clk) begin`
287			`if(dma_floppy_req) begin`
288			`dma_floppy_ack <= 1'b1;`
289			`dma_floppy_readdata <=`
290			`((dma_count % 4) == 0)? 8'd30 : //cylinder`
291			`((dma_count % 4) == 1)? 8'd01 : //head`
292			`((dma_count % 4) == 2)? 8'd12 : //sector`
293			`8'd02; //N`
294			`dma_count = dma_count + 1;`
295			`end`
296			`else begin`
297			`dma_floppy_ack <= 1'b0;`
298			`end`
299
300			`if(dma_count == 8) begin`
301			`#11;`
302			`dma_floppy_terminal <= 1'b1;`
303			`dma_floppy_ack = 1'b0;`
304
305			`#10001;`
306			`dma_count = 0;`
307
308			`READ_IO(4'h5)
309			`READ_IO(4'h5)
310			`READ_IO(4'h5)
311			`READ_IO(4'h5)
312			`READ_IO(4'h5)
313			`READ_IO(4'h5)
314			`READ_IO(4'h5)
315
316			`end`
317			`else begin`
318			`dma_floppy_terminal <= 1'b0;`
319			`end`
320			`end`
321
322			`integer finished = 0;`
323
324			`reg [255:0] dumpfile_name;`
325			`initial begin`
326			`if( $value$plusargs("dumpfile=%s", dumpfile_name) == 0 ) begin`
327			`dumpfile_name = "default.vcd";`
328			`end`
329
330			`$dumpfile(dumpfile_name);`
331			`$dumpvars(0);`
332			`$dumpon();`
333
334			`$display("START");`
335
336			`rst_n = 1'b0;`
337			`#10 rst_n = 1'b1;`
338
339			`//initialize drive`
340			`// 0x00.[0]: media present`
341			`// 0x01.[0]: media writeprotect`
342			`// 0x02.[7:0]: media cylinders`
343			`// 0x03.[7:0]: media sectors per track`
344			`// 0x04.[31:0]: media total sector count`
345			`// 0x05.[1:0]: media heads`
346			`// 0x06.[31:0]: media sd base`
347			`// 0x07.[15:0]: media wait cycles`
348			`// 0x08.[15:0]: media wait rate 0`
349			`// 0x09.[15:0]: media wait rate 1`
350			`// 0x0A.[15:0]: media wait rate 2`
351			`// 0x0B.[15:0]: media wait rate 3`
352			`// 0x0C.[7:0]: media type: 8'h20 none; 8'h00 old; 8'hC0 720k; 8'h80 1_44M; 8'h40 2_88M`
353
354			`WRITE_MGMT(4'h0, 1)
355			`WRITE_MGMT(4'h1, 0)
356			`WRITE_MGMT(4'h2, 80)
357			`WRITE_MGMT(4'h3, 18)
358			`WRITE_MGMT(4'h4, 2880)
359			`WRITE_MGMT(4'h5, 2)
360			`WRITE_MGMT(4'h6, 32'h0A0B0C0D)
361			`WRITE_MGMT(4'h7, 200)
362			`WRITE_MGMT(4'h8, 1000)
363			`WRITE_MGMT(4'h9, 1666)
364			`WRITE_MGMT(4'hA, 2000)
365			`WRITE_MGMT(4'hB, 500)
366			`WRITE_MGMT(4'hC, 8'h80)
367
368			`#10;`
369
370			`//enable motor`
371			`WRITE_IO(3'd2, 8'h1C)
372
373			`//------------------------------------------------------------------------------ read data`
374			`/*`
375			`//cmd: READ`
376			`WRITE_IO(3'd5, 8'hC6)
377			`WRITE_IO(3'd5, 8'h04)
378			`WRITE_IO(3'd5, 8'h12) //C
379			`WRITE_IO(3'd5, 8'h01) //H
380			`WRITE_IO(3'd5, 8'h05) //R
381			`WRITE_IO(3'd5, 8'h02) //N
382			`WRITE_IO(3'd5, 8'h08) //EOT
383			`WRITE_IO(3'd5, 8'hFF) //GPL
384			`WRITE_IO(3'd5, 8'hFF) //DTL
385			`*/`
386
387			`//------------------------------------------------------------------------------ write data`
388			`/*`
389			`//cmd: WRITE`
390			`WRITE_IO(3'd5, 8'hC5)
391			`WRITE_IO(3'd5, 8'h04)
392			`WRITE_IO(3'd5, 8'h12) //C
393			`WRITE_IO(3'd5, 8'h01) //H
394			`WRITE_IO(3'd5, 8'h05) //R
395			`WRITE_IO(3'd5, 8'h02) //N
396			`WRITE_IO(3'd5, 8'h08) //EOT
397			`WRITE_IO(3'd5, 8'hFF) //GPL
398			`WRITE_IO(3'd5, 8'hFF) //DTL
399			`*/`
400
401			`//------------------------------------------------------------------------------ format`
402			`//cmd: FORMAT`
403			`WRITE_IO(3'd5, 8'h4D)
404			`WRITE_IO(3'd5, 8'h04)
405			`WRITE_IO(3'd5, 8'h02) //N
406			`WRITE_IO(3'd5, 8'd18) //SC
407			`WRITE_IO(3'd5, 8'hFF) //GPL
408			`WRITE_IO(3'd5, 8'hAB) //D
409
410			`while(finished == 0) begin`
411			`if($time > 100000) $finish_and_return(-1);`
412			`#10;`
413
414			`//$dumpflush();`
415			`end`
416
417			`#60;`
418
419			`$dumpoff();`
420			`$finish_and_return(0);`
421			`end`
422
423			`endmodule`