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[/] [ao486/] [trunk/] [sim/] [iverilog/] [ps2/] [tb_ps2.v] - Blame information for rev 2

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`timescale 1 ps / 1 ps
 
module tb_ps2();
 
reg clk;
reg rst_n;
 
wire interrupt_keyb;
wire interrupt_mouse;
 
reg  [2:0]  io_address              = 3'd0;
reg         io_read                 = 1'b0;
wire [7:0]  io_readdata;
reg         io_write                = 1'b0;
reg  [7:0]  io_writedata            = 8'd0;
 
wire        speaker_61h_read;
reg  [7:0]  speaker_61h_readdata    = 8'd0;
wire        speaker_61h_write;
wire [7:0]  speaker_61h_writedata;
 
wire        output_a20_enable;
wire        output_reset_n;
 
reg kbclk_ena       = 1'b0;
reg kbclk           = 1'b0;
 
reg kbdat_ena       = 1'b0;
reg kbdat           = 1'b0;
 
reg mouseclk_ena    = 1'b0;
reg mouseclk        = 1'b0;
 
reg mousedat_ena    = 1'b0;
reg mousedat        = 1'b0;
 
wire        ps2_kbclk = kbclk_ena? kbclk : 1'bZ;
wire        ps2_kbdat = kbdat_ena? kbdat : 1'bZ;
 
wire        ps2_mouseclk = mouseclk_ena? mouseclk : 1'bZ;
wire        ps2_mousedat = mousedat_ena? mousedat : 1'bZ;
 
ps2 ps2_inst(
    .clk                    (clk),
    .rst_n                  (rst_n),
 
    .interrupt_keyb         (interrupt_keyb),       //output
    .interrupt_mouse        (interrupt_mouse),      //output
 
    //io slave
    .io_address             (io_address),     //input [2:0]
    .io_read                (io_read),        //input
    .io_readdata            (io_readdata),    //output [7:0]
    .io_write               (io_write),       //input
    .io_writedata           (io_writedata),   //input [7:0]
 
    //port 61h
    .speaker_61h_read       (speaker_61h_read),           //output
    .speaker_61h_readdata   (speaker_61h_readdata),       //input [7:0]
    .speaker_61h_write      (speaker_61h_write),          //output
    .speaker_61h_writedata  (speaker_61h_writedata),      //output [7:0]
 
    //output port
    .output_a20_enable      (output_a20_enable),  //output
    .output_reset_n         (output_reset_n),     //output
 
    //ps2 keyboard
    .ps2_kbclk              (ps2_kbclk),      //inout
    .ps2_kbdat              (ps2_kbdat),      //inout
 
    //ps2 mouse
    .ps2_mouseclk           (ps2_mouseclk),   //inout
    .ps2_mousedat           (ps2_mousedat)    //inout
);
 
//------------------------------------------------------------------------------
 
initial begin
    clk = 1'b0;
    forever #5 clk = ~clk;
end
 
//------------------------------------------------------------------------------ keyboard send
 
`define KB_SEND(data)   \
    kbclk_ena = 1'b1;   \
    kbdat_ena = 1'b1;   \
    kbclk = 1'b1;       \
    kbdat = data;       \
    #20;                 \
    kbclk = 1'b0;       \
    #20;                 \
    kbclk_ena = 1'b0;   \
    kbclk = 1'b0;       \
    kbdat_ena = 1'b0;   \
    kbdat = 1'b0;
 
`define MOUSE_SEND(data)   \
    mouseclk_ena = 1'b1;   \
    mousedat_ena = 1'b1;   \
    mouseclk = 1'b1;       \
    mousedat = data;       \
    #200;                 \
    mouseclk = 1'b0;       \
    #200;                 \
    mouseclk_ena = 1'b0;   \
    mouseclk = 1'b0;       \
    mousedat_ena = 1'b0;   \
    mousedat = 1'b0;
 
`define MOUSE_CLK  \
    mouseclk_ena = 1'b1;   \
    mouseclk = 1'b1;       \
    #200;                 \
    mouseclk = 1'b0;       \
    #200;                 \
    mouseclk_ena = 1'b0;   \
    mouseclk = 1'b0;
 
`define KB_CLK  \
    kbclk_ena = 1'b1;   \
    kbclk = 1'b1;       \
    #20;                 \
    kbclk = 1'b0;       \
    #20;                 \
    kbclk_ena = 1'b0;   \
    kbclk = 1'b0;
 
`define READ_IO(addr)  \
    io_read         = 1'b1;   \
    io_address      = addr;   \
    #10;                      \
    io_read         = 1'b0;
 
`define WRITE_IO(addr, data)  \
    io_write        = 1'b1;   \
    io_address      = addr;   \
    io_writedata    = data;   \
    #10;                      \
    io_write        = 1'b0;
 
initial begin
    #100;
 
 
    /*
outb(PORT_PS2_STATUS, 0xaa);
 
max=0xffff;
while ( (inb(PORT_PS2_STATUS) & 0x02) && (--max>0)) outb(PORT_DIAG, 0x00);
if (max==0x0) keyboard_panic(00);
 
max=0xffff;
while ( ((inb(PORT_PS2_STATUS) & 0x01) == 0) && (--max>0) ) outb(PORT_DIAG, 0x01);
if (max==0x0) keyboard_panic(01);
    */
 
    `WRITE_IO(4, 8'hAA)
 
    #100;
    `READ_IO(3'd4)
    #100;
    `READ_IO(3'd4)
    #100;
    `READ_IO(3'd4)
    #100;
    `READ_IO(3'd4)
    #100;
    `READ_IO(3'd4)
    `READ_IO(3'd4)
    `READ_IO(3'd4)
 
    //--------------------------------------------------------------------------
 
 
 
    /*
    `WRITE_IO(4, 8'h60)
    `WRITE_IO(0, 8'h03)
 
    #10
 
    `WRITE_IO(4, 8'hD4)
    `WRITE_IO(0, 8'hF5)
 
    while(ps2_inst.mouse_state != 5) #10;
 
    #20
 
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_CLK
    `MOUSE_SEND(0)
 
    mouseclk_ena = 1'b1;
    mouseclk     = 1'b1;
    mousedat_ena = 1'b1;
    mousedat     = 1'b1;
    #20;
    mouseclk_ena = 1'b0;
    mouseclk     = 1'b0;
    mousedat_ena = 1'b0;
    mousedat     = 1'b0;
    */
 
//------------------------------------------------------------------------------ keyboard test
 
/*
    `KB_SEND(0)
 
    `KB_SEND(1)
    `KB_SEND(0)
    `KB_SEND(1)
    `KB_SEND(0)
    `KB_SEND(1)
    `KB_SEND(0)
    `KB_SEND(1)
    `KB_SEND(1)
 
    `KB_SEND(0)
    `KB_SEND(1)
 
    kbclk_ena = 1'b1;
    kbclk     = 1'b1;
    kbdat_ena = 1'b1;
    kbdat     = 1'b1;
    #20;
    kbclk_ena = 1'b0;
    kbclk     = 1'b0;
    kbdat_ena = 1'b0;
    kbdat     = 1'b0;
 
    #50;
    `READ_IO(3'd0)
 
    #50;
    `WRITE_IO(3'd0, 8'h83)
 
    while(ps2_inst.keyb_state != 5) #10;
 
    #20;
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_CLK
    `KB_SEND(0)
 
    kbclk_ena = 1'b1;
    kbclk     = 1'b1;
    kbdat_ena = 1'b1;
    kbdat     = 1'b1;
    #20;
    kbclk_ena = 1'b0;
    kbclk     = 1'b0;
    kbdat_ena = 1'b0;
    kbdat     = 1'b0;
*/
 
 
end
 
//------------------------------------------------------------------------------
 
integer finished = 0;
 
reg [255:0] dumpfile_name;
initial begin
    if( $value$plusargs("dumpfile=%s", dumpfile_name) == 0 ) begin
        dumpfile_name = "default.vcd";
    end
 
    $dumpfile(dumpfile_name);
    $dumpvars(0);
    $dumpon();
 
    $display("START");
 
    rst_n = 1'b0;
    #10 rst_n = 1'b1;
 
    while(finished == 0) begin
        if($time > 200000) $finish_and_return(-1);
        #10;
 
        //$dumpflush();
    end
 
    #60;
 
    $dumpoff();
    $finish_and_return(0);
end
 
endmodule

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Subversion Repositories ao486

[/] [ao486/] [trunk/] [sim/] [iverilog/] [ps2/] [tb_ps2.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik
2			`timescale 1 ps / 1 ps
3
4			`module tb_ps2();`
5
6			`reg clk;`
7			`reg rst_n;`
8
9			`wire interrupt_keyb;`
10			`wire interrupt_mouse;`
11
12			`reg [2:0] io_address = 3'd0;`
13			`reg io_read = 1'b0;`
14			`wire [7:0] io_readdata;`
15			`reg io_write = 1'b0;`
16			`reg [7:0] io_writedata = 8'd0;`
17
18			`wire speaker_61h_read;`
19			`reg [7:0] speaker_61h_readdata = 8'd0;`
20			`wire speaker_61h_write;`
21			`wire [7:0] speaker_61h_writedata;`
22
23			`wire output_a20_enable;`
24			`wire output_reset_n;`
25
26			`reg kbclk_ena = 1'b0;`
27			`reg kbclk = 1'b0;`
28
29			`reg kbdat_ena = 1'b0;`
30			`reg kbdat = 1'b0;`
31
32			`reg mouseclk_ena = 1'b0;`
33			`reg mouseclk = 1'b0;`
34
35			`reg mousedat_ena = 1'b0;`
36			`reg mousedat = 1'b0;`
37
38			`wire ps2_kbclk = kbclk_ena? kbclk : 1'bZ;`
39			`wire ps2_kbdat = kbdat_ena? kbdat : 1'bZ;`
40
41			`wire ps2_mouseclk = mouseclk_ena? mouseclk : 1'bZ;`
42			`wire ps2_mousedat = mousedat_ena? mousedat : 1'bZ;`
43
44			`ps2 ps2_inst(`
45			`.clk (clk),`
46			`.rst_n (rst_n),`
47
48			`.interrupt_keyb (interrupt_keyb), //output`
49			`.interrupt_mouse (interrupt_mouse), //output`
50
51			`//io slave`
52			`.io_address (io_address), //input [2:0]`
53			`.io_read (io_read), //input`
54			`.io_readdata (io_readdata), //output [7:0]`
55			`.io_write (io_write), //input`
56			`.io_writedata (io_writedata), //input [7:0]`
57
58			`//port 61h`
59			`.speaker_61h_read (speaker_61h_read), //output`
60			`.speaker_61h_readdata (speaker_61h_readdata), //input [7:0]`
61			`.speaker_61h_write (speaker_61h_write), //output`
62			`.speaker_61h_writedata (speaker_61h_writedata), //output [7:0]`
63
64			`//output port`
65			`.output_a20_enable (output_a20_enable), //output`
66			`.output_reset_n (output_reset_n), //output`
67
68			`//ps2 keyboard`
69			`.ps2_kbclk (ps2_kbclk), //inout`
70			`.ps2_kbdat (ps2_kbdat), //inout`
71
72			`//ps2 mouse`
73			`.ps2_mouseclk (ps2_mouseclk), //inout`
74			`.ps2_mousedat (ps2_mousedat) //inout`
75			`);`
76
77			`//------------------------------------------------------------------------------`
78
79			`initial begin`
80			`clk = 1'b0;`
81			`forever #5 clk = ~clk;`
82			`end`
83
84			`//------------------------------------------------------------------------------ keyboard send`
85
86			`define KB_SEND(data) \
87			`kbclk_ena = 1'b1; \`
88			`kbdat_ena = 1'b1; \`
89			`kbclk = 1'b1; \`
90			`kbdat = data; \`
91			`#20; \`
92			`kbclk = 1'b0; \`
93			`#20; \`
94			`kbclk_ena = 1'b0; \`
95			`kbclk = 1'b0; \`
96			`kbdat_ena = 1'b0; \`
97			`kbdat = 1'b0;`
98
99			`define MOUSE_SEND(data) \
100			`mouseclk_ena = 1'b1; \`
101			`mousedat_ena = 1'b1; \`
102			`mouseclk = 1'b1; \`
103			`mousedat = data; \`
104			`#200; \`
105			`mouseclk = 1'b0; \`
106			`#200; \`
107			`mouseclk_ena = 1'b0; \`
108			`mouseclk = 1'b0; \`
109			`mousedat_ena = 1'b0; \`
110			`mousedat = 1'b0;`
111
112			`define MOUSE_CLK \
113			`mouseclk_ena = 1'b1; \`
114			`mouseclk = 1'b1; \`
115			`#200; \`
116			`mouseclk = 1'b0; \`
117			`#200; \`
118			`mouseclk_ena = 1'b0; \`
119			`mouseclk = 1'b0;`
120
121			`define KB_CLK \
122			`kbclk_ena = 1'b1; \`
123			`kbclk = 1'b1; \`
124			`#20; \`
125			`kbclk = 1'b0; \`
126			`#20; \`
127			`kbclk_ena = 1'b0; \`
128			`kbclk = 1'b0;`
129
130			`define READ_IO(addr) \
131			`io_read = 1'b1; \`
132			`io_address = addr; \`
133			`#10; \`
134			`io_read = 1'b0;`
135
136			`define WRITE_IO(addr, data) \
137			`io_write = 1'b1; \`
138			`io_address = addr; \`
139			`io_writedata = data; \`
140			`#10; \`
141			`io_write = 1'b0;`
142
143			`initial begin`
144			`#100;`
145
146
147			`/*`
148			`outb(PORT_PS2_STATUS, 0xaa);`
149
150			`max=0xffff;`
151			`while ( (inb(PORT_PS2_STATUS) & 0x02) && (--max>0)) outb(PORT_DIAG, 0x00);`
152			`if (max==0x0) keyboard_panic(00);`
153
154			`max=0xffff;`
155			`while ( ((inb(PORT_PS2_STATUS) & 0x01) == 0) && (--max>0) ) outb(PORT_DIAG, 0x01);`
156			`if (max==0x0) keyboard_panic(01);`
157			`*/`
158
159			`WRITE_IO(4, 8'hAA)
160
161			`#100;`
162			`READ_IO(3'd4)
163			`#100;`
164			`READ_IO(3'd4)
165			`#100;`
166			`READ_IO(3'd4)
167			`#100;`
168			`READ_IO(3'd4)
169			`#100;`
170			`READ_IO(3'd4)
171			`READ_IO(3'd4)
172			`READ_IO(3'd4)
173
174			`//--------------------------------------------------------------------------`
175
176
177
178			`/*`
179			`WRITE_IO(4, 8'h60)
180			`WRITE_IO(0, 8'h03)
181
182			`#10`
183
184			`WRITE_IO(4, 8'hD4)
185			`WRITE_IO(0, 8'hF5)
186
187			`while(ps2_inst.mouse_state != 5) #10;`
188
189			`#20`
190
191			`MOUSE_CLK
192			`MOUSE_CLK
193			`MOUSE_CLK
194			`MOUSE_CLK
195			`MOUSE_CLK
196			`MOUSE_CLK
197			`MOUSE_CLK
198			`MOUSE_CLK
199			`MOUSE_CLK
200			`MOUSE_CLK
201			`MOUSE_SEND(0)
202
203			`mouseclk_ena = 1'b1;`
204			`mouseclk = 1'b1;`
205			`mousedat_ena = 1'b1;`
206			`mousedat = 1'b1;`
207			`#20;`
208			`mouseclk_ena = 1'b0;`
209			`mouseclk = 1'b0;`
210			`mousedat_ena = 1'b0;`
211			`mousedat = 1'b0;`
212			`*/`
213
214			`//------------------------------------------------------------------------------ keyboard test`
215
216			`/*`
217			`KB_SEND(0)
218
219			`KB_SEND(1)
220			`KB_SEND(0)
221			`KB_SEND(1)
222			`KB_SEND(0)
223			`KB_SEND(1)
224			`KB_SEND(0)
225			`KB_SEND(1)
226			`KB_SEND(1)
227
228			`KB_SEND(0)
229			`KB_SEND(1)
230
231			`kbclk_ena = 1'b1;`
232			`kbclk = 1'b1;`
233			`kbdat_ena = 1'b1;`
234			`kbdat = 1'b1;`
235			`#20;`
236			`kbclk_ena = 1'b0;`
237			`kbclk = 1'b0;`
238			`kbdat_ena = 1'b0;`
239			`kbdat = 1'b0;`
240
241			`#50;`
242			`READ_IO(3'd0)
243
244			`#50;`
245			`WRITE_IO(3'd0, 8'h83)
246
247			`while(ps2_inst.keyb_state != 5) #10;`
248
249			`#20;`
250			`KB_CLK
251			`KB_CLK
252			`KB_CLK
253			`KB_CLK
254			`KB_CLK
255			`KB_CLK
256			`KB_CLK
257			`KB_CLK
258			`KB_CLK
259			`KB_CLK
260			`KB_SEND(0)
261
262			`kbclk_ena = 1'b1;`
263			`kbclk = 1'b1;`
264			`kbdat_ena = 1'b1;`
265			`kbdat = 1'b1;`
266			`#20;`
267			`kbclk_ena = 1'b0;`
268			`kbclk = 1'b0;`
269			`kbdat_ena = 1'b0;`
270			`kbdat = 1'b0;`
271			`*/`
272
273
274			`end`
275
276			`//------------------------------------------------------------------------------`
277
278			`integer finished = 0;`
279
280			`reg [255:0] dumpfile_name;`
281			`initial begin`
282			`if( $value$plusargs("dumpfile=%s", dumpfile_name) == 0 ) begin`
283			`dumpfile_name = "default.vcd";`
284			`end`
285
286			`$dumpfile(dumpfile_name);`
287			`$dumpvars(0);`
288			`$dumpon();`
289
290			`$display("START");`
291
292			`rst_n = 1'b0;`
293			`#10 rst_n = 1'b1;`
294
295			`while(finished == 0) begin`
296			`if($time > 200000) $finish_and_return(-1);`
297			`#10;`
298
299			`//$dumpflush();`
300			`end`
301
302			`#60;`
303
304			`$dumpoff();`
305			`$finish_and_return(0);`
306			`end`
307
308			`endmodule`