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[/] [ao486/] [trunk/] [sim/] [iverilog/] [sound/] [tb_sound_dsp.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 alfik 
 
2 
`timescale 1 ps / 1 ps
3 
 
4 
module tb_sound_dsp();
5 
 
6 
reg clk;
7 
reg rst_n;
8 
 
9 
wire interrupt;
10 
 
11 
reg  [3:0]  io_address                  = 4'b0;
12 
reg         io_read                     = 1'b0;
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wire [7:0]  io_readdata_from_dsp;
14 
reg         io_write                    = 1'b0;
15 
reg  [7:0]  io_writedata                = 8'd0;
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17 
wire        dma_soundblaster_req;
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reg         dma_soundblaster_ack        = 1'd0;
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reg         dma_soundblaster_terminal   = 1'd0;
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reg  [7:0]  dma_soundblaster_readdata   = 8'd0;
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wire [7:0]  dma_soundblaster_writedata;
22 
 
23 
wire        sample_from_dsp;
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wire [7:0]  sample_from_dsp_value;
25 
 
26 
reg  [7:0]  mgmt_address                = 8'd0;
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reg         mgmt_write                  = 1'b0;
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reg  [31:0] mgmt_writedata              = 32'd0;
29 
 
30 
sound_dsp sound_dsp_inst(
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    .clk                        (clk),
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    .rst_n                      (rst_n),
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34 
    .interrupt                  (interrupt),                    //output
35 
 
36 
    //io slave 220h-22Fh
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    .io_address                 (io_address),                   //input [3:0]
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    .io_read                    (io_read),                      //input
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    .io_readdata_from_dsp       (io_readdata_from_dsp),         //output [7:0]
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    .io_write                   (io_write),                     //input
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    .io_writedata               (io_writedata),                 //input [7:0]
42 
 
43 
    //dma
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    .dma_soundblaster_req       (dma_soundblaster_req),         //output
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    .dma_soundblaster_ack       (dma_soundblaster_ack),         //input
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    .dma_soundblaster_terminal  (dma_soundblaster_terminal),    //input
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    .dma_soundblaster_readdata  (dma_soundblaster_readdata),    //input [7:0]
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    .dma_soundblaster_writedata (dma_soundblaster_writedata),   //output [7:0]
49 
 
50 
    //sample
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    .sample_from_dsp            (sample_from_dsp),              //output
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    .sample_from_dsp_value      (sample_from_dsp_value),        //output [7:0]
53 
 
54 
    //mgmt slave
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    .mgmt_address               (mgmt_address),                 //input [7:0]
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    .mgmt_write                 (mgmt_write),                   //input
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    .mgmt_writedata             (mgmt_writedata)                //input [31:0]
58 
);
59 
 
60 
//------------------------------------------------------------------------------
61 
 
62 
initial begin
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    clk = 1'b0;
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    forever #5 clk = ~clk;
65 
end
66 
 
67 
//------------------------------------------------------------------------------
68 
 
69 
`define WRITE_MGMT(addr, data)  \
70 
    mgmt_write        = 1'b1;   \
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    mgmt_address      = addr;   \
72 
    mgmt_writedata    = data;   \
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    #10;                        \
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    mgmt_write        = 1'b0;
75 
 
76 
`define WRITE_IO(addr, data)  \
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    io_write        = 1'b1;   \
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    io_address      = addr;   \
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    io_writedata    = data;   \
80 
    #10;                      \
81 
    io_write        = 1'b0;
82 
 
83 
`define READ_IO(addr)       \
84 
    io_read         = 1'b1; \
85 
    io_address      = addr; \
86 
    #10;                    \
87 
    io_read         = 1'b0;
88 
 
89 
//------------------------------------------------------------------------------
90 
 
91 
initial begin
92 
    #100;
93 
 
94 
    `WRITE_MGMT(8'd128, 16'd50)
95 
 
96 
    #20
97 
 
98 
    `WRITE_IO(4'hC, 8'hD1) //cmd: speaker on
99 
 
100 
    `WRITE_IO(4'hC, 8'h40) //cmd: time constant
101 
    `WRITE_IO(4'hC, 8'd128)
102 
 
103 
    //-------------------------------------------------------------------------- dma single output
104 
    /*
105 
    `WRITE_IO(4'hC, 8'h14)
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    `WRITE_IO(4'hC, 8'h0B)
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    `WRITE_IO(4'hC, 8'h00)
108 
    */
109 
 
110 
    //-------------------------------------------------------------------------- dma single input
111 
    /*
112 
    `WRITE_IO(4'hC, 8'h24)
113 
    `WRITE_IO(4'hC, 8'h0B)
114 
    `WRITE_IO(4'hC, 8'h00)
115 
    */
116 
 
117 
    //-------------------------------------------------------------------------- dma single output 4-bit adpcm + ref
118 
    /*
119 
    `WRITE_IO(4'hC, 8'h75)
120 
    `WRITE_IO(4'hC, 8'h04)
121 
    `WRITE_IO(4'hC, 8'h00)
122 
    */
123 
    //-------------------------------------------------------------------------- dma single output 3-bit adpcm + ref
124 
    /*
125 
    `WRITE_IO(4'hC, 8'h77)
126 
    `WRITE_IO(4'hC, 8'h0B)
127 
    `WRITE_IO(4'hC, 8'h00)
128 
    */
129 
    //-------------------------------------------------------------------------- dma single output 2-bit adpcm + ref
130 
    /*
131 
    `WRITE_IO(4'hC, 8'h17)
132 
    `WRITE_IO(4'hC, 8'h0B)
133 
    `WRITE_IO(4'hC, 8'h00)
134 
    */
135 
 
136 
    //-------------------------------------------------------------------------- dma single output 4-bit adpcm
137 
    /*
138 
    `WRITE_IO(4'hC, 8'h74)
139 
    `WRITE_IO(4'hC, 8'h04)
140 
    `WRITE_IO(4'hC, 8'h00)
141 
    */
142 
    //-------------------------------------------------------------------------- dma single output 3-bit adpcm
143 
    /*
144 
    `WRITE_IO(4'hC, 8'h76)
145 
    `WRITE_IO(4'hC, 8'h0B)
146 
    `WRITE_IO(4'hC, 8'h00)
147 
    */
148 
    //-------------------------------------------------------------------------- dma single output 2-bit adpcm
149 
    /*
150 
    `WRITE_IO(4'hC, 8'h16)
151 
    `WRITE_IO(4'hC, 8'h04)
152 
    `WRITE_IO(4'hC, 8'h00)
153 
    */
154 
 
155 
    //-------------------------------------------------------------------------- dma auto output
156 
    /*
157 
    `WRITE_IO(4'hC, 8'h48)
158 
    `WRITE_IO(4'hC, 8'h04)
159 
    `WRITE_IO(4'hC, 8'h00)
160 
 
161 
    `WRITE_IO(4'hC, 8'h1C)
162 
 
163 
    #2000
164 
 
165 
    //`WRITE_IO(4'hC, 8'hDA)
166 
 
167 
    `WRITE_IO(4'hC, 8'h17)
168 
    `WRITE_IO(4'hC, 8'h0B)
169 
    `WRITE_IO(4'hC, 8'h00)
170 
    */
171 
 
172 
    //-------------------------------------------------------------------------- dma auto input
173 
    /*
174 
    `WRITE_IO(4'hC, 8'h48)
175 
    `WRITE_IO(4'hC, 8'h04)
176 
    `WRITE_IO(4'hC, 8'h00)
177 
 
178 
    `WRITE_IO(4'hC, 8'h2C)
179 
 
180 
    #2000;
181 
 
182 
    //`WRITE_IO(4'hC, 8'hDA)
183 
 
184 
    `WRITE_IO(4'hC, 8'h17)
185 
    `WRITE_IO(4'hC, 8'h0B)
186 
    `WRITE_IO(4'hC, 8'h00)
187 
    */
188 
 
189 
    //-------------------------------------------------------------------------- dma auto output 2-bit adpcm
190 
    /*
191 
    `WRITE_IO(4'hC, 8'h48)
192 
    `WRITE_IO(4'hC, 8'h04)
193 
    `WRITE_IO(4'hC, 8'h00)
194 
 
195 
    `WRITE_IO(4'hC, 8'h1F)
196 
 
197 
    #20000;
198 
 
199 
    //`WRITE_IO(4'hC, 8'hDA)
200 
 
201 
    `WRITE_IO(4'hC, 8'h17)
202 
    `WRITE_IO(4'hC, 8'h0B)
203 
    `WRITE_IO(4'hC, 8'h00)
204 
    */
205 
 
206 
    //-------------------------------------------------------------------------- dma auto output 3-bit adpcm
207 
    /*
208 
    `WRITE_IO(4'hC, 8'h48)
209 
    `WRITE_IO(4'hC, 8'h04)
210 
    `WRITE_IO(4'hC, 8'h00)
211 
 
212 
    `WRITE_IO(4'hC, 8'h7F)
213 
 
214 
    #20000;
215 
 
216 
    //`WRITE_IO(4'hC, 8'hDA)
217 
 
218 
    `WRITE_IO(4'hC, 8'h17)
219 
    `WRITE_IO(4'hC, 8'h0B)
220 
    `WRITE_IO(4'hC, 8'h00)
221 
    */
222 
 
223 
    //-------------------------------------------------------------------------- dma auto output 4-bit adpcm
224 
    /*
225 
    `WRITE_IO(4'hC, 8'h48)
226 
    `WRITE_IO(4'hC, 8'h04)
227 
    `WRITE_IO(4'hC, 8'h00)
228 
 
229 
    `WRITE_IO(4'hC, 8'h7D)
230 
 
231 
    #20000;
232 
 
233 
    //`WRITE_IO(4'hC, 8'hDA)
234 
 
235 
    `WRITE_IO(4'hC, 8'h17)
236 
    `WRITE_IO(4'hC, 8'h0B)
237 
    `WRITE_IO(4'hC, 8'h00)
238 
    */
239 
 
240 
    //-------------------------------------------------------------------------- dma single output highspeed
241 
    /*
242 
    `WRITE_IO(4'hC, 8'h48)
243 
    `WRITE_IO(4'hC, 8'h04)
244 
    `WRITE_IO(4'hC, 8'h00)
245 
 
246 
    `WRITE_IO(4'hC, 8'h91)
247 
    */
248 
    //-------------------------------------------------------------------------- dma single input highspeed
249 
    /*
250 
    `WRITE_IO(4'hC, 8'h48)
251 
    `WRITE_IO(4'hC, 8'h04)
252 
    `WRITE_IO(4'hC, 8'h00)
253 
 
254 
    `WRITE_IO(4'hC, 8'h99)
255 
    */
256 
 
257 
    //-------------------------------------------------------------------------- dma auto output highspeed
258 
    /*
259 
    `WRITE_IO(4'hC, 8'h48)
260 
    `WRITE_IO(4'hC, 8'h04)
261 
    `WRITE_IO(4'hC, 8'h00)
262 
 
263 
    `WRITE_IO(4'hC, 8'h90)
264 
 
265 
    #2000
266 
 
267 
    `WRITE_IO(4'hC, 8'hDA)
268 
 
269 
    #2000
270 
 
271 
    `WRITE_IO(4'hC, 8'h17)
272 
    `WRITE_IO(4'hC, 8'h0B)
273 
    `WRITE_IO(4'hC, 8'h00)
274 
 
275 
    #2000
276 
 
277 
    `WRITE_IO(4'h6, 8'h01)
278 
    `WRITE_IO(4'h6, 8'h00)
279 
 
280 
    #2000
281 
 
282 
    `WRITE_IO(4'hC, 8'hDA)
283 
    */
284 
 
285 
    //-------------------------------------------------------------------------- dma auto input highspeed
286 
 
287 
    `WRITE_IO(4'hC, 8'h48)
288 
    `WRITE_IO(4'hC, 8'h04)
289 
    `WRITE_IO(4'hC, 8'h00)
290 
 
291 
    `WRITE_IO(4'hC, 8'h98)
292 
 
293 
    #2000
294 
 
295 
    `WRITE_IO(4'hC, 8'hDA)
296 
 
297 
    #2000
298 
 
299 
    `WRITE_IO(4'hC, 8'h17)
300 
    `WRITE_IO(4'hC, 8'h0B)
301 
    `WRITE_IO(4'hC, 8'h00)
302 
 
303 
    #2000
304 
 
305 
    `WRITE_IO(4'h6, 8'h01)
306 
    `WRITE_IO(4'h6, 8'h00)
307 
 
308 
    #2000;
309 
 
310 
    `WRITE_IO(4'hC, 8'hDA)
311 
 
312 
 
313 
end
314 
 
315 
always @(posedge clk) begin
316 
    if(interrupt) begin
317 
        #100
318 
        `READ_IO(4'hE)
319 
    end
320 
end
321 
//------------------------------------------------------------------------------
322 
 
323 
always @(posedge clk) begin
324 
    if(dma_soundblaster_req && dma_soundblaster_ack == 1'b0) begin
325 
        dma_soundblaster_readdata <= dma_soundblaster_readdata + 8'd1;
326 
        dma_soundblaster_ack <= 1'b1;
327 
    end
328 
    else begin
329 
        dma_soundblaster_ack <= 1'b0;
330 
    end
331 
 
332 
    if(dma_soundblaster_req == 1'b0 && dma_soundblaster_readdata == 8'd10 && dma_soundblaster_terminal == 1'b0) begin
333 
        dma_soundblaster_terminal <= 1'b1;
334 
        dma_soundblaster_readdata <= dma_soundblaster_readdata + 8'd1;
335 
    end
336 
    else begin
337 
        dma_soundblaster_terminal <= 1'b0;
338 
    end
339 
end
340 
 
341 
//------------------------------------------------------------------------------
342 
 
343 
integer finished = 0;
344 
 
345 
reg [255:0] dumpfile_name;
346 
initial begin
347 
    if( $value$plusargs("dumpfile=%s", dumpfile_name) == 0 ) begin
348 
        dumpfile_name = "default.vcd";
349 
    end
350 
 
351 
    $dumpfile(dumpfile_name);
352 
    $dumpvars(0);
353 
    $dumpon();
354 
 
355 
    $display("START");
356 
 
357 
    rst_n = 1'b0;
358 
    #10 rst_n = 1'b1;
359 
 
360 
    while(finished == 0) begin
361 
        if($time > 200000) $finish_and_return(-1);
362 
        #10;
363 
 
364 
        //$dumpflush();
365 
    end
366 
 
367 
    #60;
368 
 
369 
    $dumpoff();
370 
    $finish_and_return(0);
371 
end
372 
 
373 
//------------------------------------------------------------------------------
374 
 
375 
 
376 
endmodule

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