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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [pic/] [main.cpp] - Blame information for rev 2

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#include <cstdio>
#include <cstdlib>
 
#include "Vpic.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
 
//------------------------------------------------------------------------------
 
typedef unsigned int uint32;
typedef unsigned char uint8;
 
//------------------------------------------------------------------------------
 
enum state_t {
    S_IDLE,
 
    S_IO_READ_1,
    S_IO_READ_2,
    S_IO_READ_3,
 
    S_IO_WRITE_1,
    S_IO_WRITE_2,
    S_IO_WRITE_3,
 
    S_DELAY
};
 
uint32  address_base;
uint32  address;
uint32  byteena;
uint32  value_base;
uint32  value;
state_t state = S_IDLE;
uint32  shifted;
uint32  shifted_read;
uint32  length;
uint32  value_read;
 
uint32  delay;
 
uint32  interrupt_input = 0;
uint32  interrupt_vector = 0;
bool    interrupt_ack = false;
 
void check_byteena(uint32 byteena) {
    if(byteena == 0 || byteena == 5 || byteena == 9 || byteena == 10 || byteena == 11 || byteena == 13) {
        printf("ERROR: invalid byteena: %x\n", byteena);
        exit(-1);
    }
 
    value_read = 0;
    address_base = address;
    value_base = value;
    shifted_read = 0;
 
    shifted = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) break;
 
        shifted++;
        address++;
        byteena >>= 1;
        value >>= 8;
    }
 
    length = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) length++;
 
        byteena >>= 1;
    }
}
 
bool is_address_ok(uint32 address) {
    if(address >= 0x0020 && address <= 0x021) return true;
    if(address >= 0x00A0 && address <= 0x0A1) return true;
 
    return false;
}
 
bool next_record() {
    static FILE *fp = NULL;
 
    if(fp == NULL) {
        fp = fopen("./../../../../backup/run-3/track.txt", "rb");
        if(fp == NULL) {
            printf("ERROR: can not open file.\n");
            exit(-1);
        }
    }
 
    do {
        char line[256];
        memset(line, 0, sizeof(line));
 
        char *res = fgets(line, sizeof(line), fp);
        if(res == NULL) {
            fclose(fp);
            fp = NULL;
            return false;
        }
 
//printf("line: %s\n", line);
 
        int count;
 
        count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_READ_1;
printf("line: %s", line);
            return true;
        }
        count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_WRITE_1;
printf("line: %s", line);
            return true;
        }
 
        uint32 irq_signal = 0;
        count = sscanf(line, "raise_irq %d", &irq_signal);
        if(count == 1) {
            interrupt_input |= (1 << irq_signal);
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
        }
 
        count = sscanf(line, "lower_irq %d", &irq_signal);
        if(count == 1) {
            interrupt_input &= ~(1 << irq_signal);
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
        }
 
        count = sscanf(line, "IAC %d", &irq_signal);
        if(count == 1) {
            interrupt_ack = true;
            interrupt_vector = irq_signal;
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
        }
 
    } while(true);
 
    return false;
}
 
//------------------------------------------------------------------------------
 
int main(int argc, char **argv) {
    Verilated::commandArgs(argc, argv);
 
    Verilated::traceEverOn(true);
    VerilatedVcdC* tracer = new VerilatedVcdC;
 
    Vpic *top = new Vpic();
    top->trace (tracer, 99);
    //tracer->rolloverMB(1000000);
    tracer->open("pic.vcd");
 
    bool dump = true;
 
    //reset
    top->clk = 0; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 1; top->eval();
 
    uint32 cycle = 0;
    while(!Verilated::gotFinish()) {
 
        //----------------------------------------------------------------------
 
        top->interrupt_done = 0;
 
        if(state == S_IDLE) {
            bool res = next_record();
            if(res == false) {
                printf("End of file.\n");
                break;
            }
 
            top->interrupt_input = interrupt_input & 0xFFFF;
 
            if(interrupt_ack) {
                if(top->interrupt_do == 0) {
                    printf("ERROR: interrupt_do not set for: %d\n", interrupt_vector);
                    exit(-1);
                }
 
                if(top->interrupt_vector != interrupt_vector) {
                    printf("ERROR: interrupt_vector %d != %d\n", interrupt_vector, top->interrupt_vector);
                    exit(-1);
                }
 
                top->interrupt_done = 1;
                interrupt_ack = false;
            }
        }
 
        //----------------------------------------------------------------------
 
        if(state == S_DELAY) {
            delay--;
 
            if(delay == 0) {
                state = S_IDLE;
            }
        }
        else if(state == S_IO_READ_1) {
            if(address >= 0x00A0 && address <= 0x00A1) {
                top->slave_address = address & 0x1;
                top->slave_read = 1;
            }
            else if(address >= 0x0020 && address <= 0x0021) {
                top->master_address = address & 0x1;
                top->master_read = 1;
            }
            else {
                printf("ERROR: invalid io rd address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_READ_2;
        }
        else if(state == S_IO_READ_2) {
            length--;
            shifted_read++;
 
            uint32 top_readdata = 0;
 
            if(address >= 0x00A0 && address <= 0x00A1)      top_readdata = top->slave_readdata & 0xFF;
            else if(address >= 0x0020 && address <= 0x0021) top_readdata = top->master_readdata & 0xFF;
 
            if(length > 0) {
                address++;
 
                if(address >= 0x00A0 && address <= 0x00A1)      top->slave_address  = address & 0x1;
                else if(address >= 0x0020 && address <= 0x0021) top->master_address = address & 0x1;
                else {
                    printf("ERROR: invalid io rd address: %08x\n", address);
                    exit(-1);
                }
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8;
 
                top->slave_read = 0;
                top->master_read = 0;
                state = S_IO_READ_3;
            }
            else {
                top->slave_read = 0;
                top->master_read = 0;
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8*(4 - shifted_read - shifted);
 
                if(value_read != value_base) {
                    printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);
 
//if(! ((address_base ==  && byteena == )))
exit(0);
                }
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_READ_3) {
            if(address >= 0x00A0 && address <= 0x00A1)      top->slave_read = 1;
            else if(address >= 0x0020 && address <= 0x0021) top->master_read = 1;
 
            state = S_IO_READ_2;
        }
        else if(state == S_IO_WRITE_1) {
            if(address >= 0x00A0 && address <= 0x00A1) {
                top->slave_address = address & 0x1;
                top->slave_write = 1;
                top->slave_writedata = value & 0xFF;
            }
            else if(address >= 0x0020 && address <= 0x0021) {
                top->master_address = address & 0x1;
                top->master_write = 1;
                top->master_writedata = value & 0xFF;
            }
            else {
                printf("ERROR: invalid io wr address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_WRITE_2;
        }
        else if(state == S_IO_WRITE_2) {
            length--;
 
            if(length > 0) {
                address++;
                value >>= 8;
 
                if(address >= 0x00A0 && address <= 0x00A1) {
                    top->slave_address = address & 0x1;
                    top->slave_writedata = value & 0xFF;
                }
                else if(address >= 0x0020 && address <= 0x0021) {
                    top->master_address = address & 0x1;
                    top->master_writedata = value & 0xFF;
                }
                else {
                    printf("ERROR: invalid io wr address: %08x\n", address);
                    exit(-1);
                }
 
                top->slave_write = 0;
                top->master_write = 0;
                state = S_IO_WRITE_3;
            }
            else {
                top->slave_write = 0;
                top->master_write = 0;
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_WRITE_3) {
            if(address >= 0x00A0 && address <= 0x00A1)      top->slave_write = 1;
            else if(address >= 0x0020 && address <= 0x0021) top->master_write = 1;
 
            state = S_IO_WRITE_2;
        }
 
        //----------------------------------------------------------------------
 
        top->clk = 0;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        top->clk = 1;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        tracer->flush();
    }
    tracer->close();
    delete tracer;
    delete top;
 
    return 0;
}
 
//------------------------------------------------------------------------------
 
/*
    input               clk,
    input               rst_n,
 
    //master pic 0020-0021
    input               master_address,
    input               master_read,
    output reg  [7:0]   master_readdata,
    input               master_write,
    input       [7:0]   master_writedata,
 
    //slave pic 00A0-00A1
    input               slave_address,
    input               slave_read,
    output reg  [7:0]   slave_readdata,
    input               slave_write,
    input       [7:0]   slave_writedata,
 
    //interrupt input
    input       [15:0]  interrupt_input,
 
    //interrupt output
    output reg          interrupt_do,
    output reg  [7:0]   interrupt_vector,
    input               interrupt_done
*/

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Subversion Repositories ao486

[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [pic/] [main.cpp] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`#include <cstdio>`
2			`#include <cstdlib>`
3
4			`#include "Vpic.h"`
5			`#include "verilated.h"`
6			`#include "verilated_vcd_c.h"`
7
8			`//------------------------------------------------------------------------------`
9
10			`typedef unsigned int uint32;`
11			`typedef unsigned char uint8;`
12
13			`//------------------------------------------------------------------------------`
14
15			`enum state_t {`
16			`S_IDLE,`
17
18			`S_IO_READ_1,`
19			`S_IO_READ_2,`
20			`S_IO_READ_3,`
21
22			`S_IO_WRITE_1,`
23			`S_IO_WRITE_2,`
24			`S_IO_WRITE_3,`
25
26			`S_DELAY`
27			`};`
28
29			`uint32 address_base;`
30			`uint32 address;`
31			`uint32 byteena;`
32			`uint32 value_base;`
33			`uint32 value;`
34			`state_t state = S_IDLE;`
35			`uint32 shifted;`
36			`uint32 shifted_read;`
37			`uint32 length;`
38			`uint32 value_read;`
39
40			`uint32 delay;`
41
42			`uint32 interrupt_input = 0;`
43			`uint32 interrupt_vector = 0;`
44			`bool interrupt_ack = false;`
45
46			`void check_byteena(uint32 byteena) {`
47			`if(byteena == 0 \|\| byteena == 5 \|\| byteena == 9 \|\| byteena == 10 \|\| byteena == 11 \|\| byteena == 13) {`
48			`printf("ERROR: invalid byteena: %x\n", byteena);`
49			`exit(-1);`
50			`}`
51
52			`value_read = 0;`
53			`address_base = address;`
54			`value_base = value;`
55			`shifted_read = 0;`
56
57			`shifted = 0;`
58			`for(uint32 i=0; i<4; i++) {`
59			`if(byteena & 1) break;`
60
61			`shifted++;`
62			`address++;`
63			`byteena >>= 1;`
64			`value >>= 8;`
65			`}`
66
67			`length = 0;`
68			`for(uint32 i=0; i<4; i++) {`
69			`if(byteena & 1) length++;`
70
71			`byteena >>= 1;`
72			`}`
73			`}`
74
75			`bool is_address_ok(uint32 address) {`
76			`if(address >= 0x0020 && address <= 0x021) return true;`
77			`if(address >= 0x00A0 && address <= 0x0A1) return true;`
78
79			`return false;`
80			`}`
81
82			`bool next_record() {`
83			`static FILE *fp = NULL;`
84
85			`if(fp == NULL) {`
86			`fp = fopen("./../../../../backup/run-3/track.txt", "rb");`
87			`if(fp == NULL) {`
88			`printf("ERROR: can not open file.\n");`
89			`exit(-1);`
90			`}`
91			`}`
92
93			`do {`
94			`char line[256];`
95			`memset(line, 0, sizeof(line));`
96
97			`char *res = fgets(line, sizeof(line), fp);`
98			`if(res == NULL) {`
99			`fclose(fp);`
100			`fp = NULL;`
101			`return false;`
102			`}`
103
104			`//printf("line: %s\n", line);`
105
106			`int count;`
107
108			`count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);`
109			`if(count == 3 && is_address_ok(address)) {`
110			`check_byteena(byteena);`
111			`state = S_IO_READ_1;`
112			`printf("line: %s", line);`
113			`return true;`
114			`}`
115			`count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);`
116			`if(count == 3 && is_address_ok(address)) {`
117			`check_byteena(byteena);`
118			`state = S_IO_WRITE_1;`
119			`printf("line: %s", line);`
120			`return true;`
121			`}`
122
123			`uint32 irq_signal = 0;`
124			`count = sscanf(line, "raise_irq %d", &irq_signal);`
125			`if(count == 1) {`
126			`interrupt_input \|= (1 << irq_signal);`
127			`printf("line: %s", line);`
128			`delay = 5;`
129			`state = S_DELAY;`
130			`return true;`
131			`}`
132
133			`count = sscanf(line, "lower_irq %d", &irq_signal);`
134			`if(count == 1) {`
135			`interrupt_input &= ~(1 << irq_signal);`
136			`printf("line: %s", line);`
137			`delay = 5;`
138			`state = S_DELAY;`
139			`return true;`
140			`}`
141
142			`count = sscanf(line, "IAC %d", &irq_signal);`
143			`if(count == 1) {`
144			`interrupt_ack = true;`
145			`interrupt_vector = irq_signal;`
146			`printf("line: %s", line);`
147			`delay = 5;`
148			`state = S_DELAY;`
149			`return true;`
150			`}`
151
152			`} while(true);`
153
154			`return false;`
155			`}`
156
157			`//------------------------------------------------------------------------------`
158
159			`int main(int argc, char **argv) {`
160			`Verilated::commandArgs(argc, argv);`
161
162			`Verilated::traceEverOn(true);`
163			`VerilatedVcdC* tracer = new VerilatedVcdC;`
164
165			`Vpic *top = new Vpic();`
166			`top->trace (tracer, 99);`
167			`//tracer->rolloverMB(1000000);`
168			`tracer->open("pic.vcd");`
169
170			`bool dump = true;`
171
172			`//reset`
173			`top->clk = 0; top->rst_n = 1; top->eval();`
174			`top->clk = 1; top->rst_n = 1; top->eval();`
175			`top->clk = 1; top->rst_n = 0; top->eval();`
176			`top->clk = 0; top->rst_n = 0; top->eval();`
177			`top->clk = 0; top->rst_n = 1; top->eval();`
178
179			`uint32 cycle = 0;`
180			`while(!Verilated::gotFinish()) {`
181
182			`//----------------------------------------------------------------------`
183
184			`top->interrupt_done = 0;`
185
186			`if(state == S_IDLE) {`
187			`bool res = next_record();`
188			`if(res == false) {`
189			`printf("End of file.\n");`
190			`break;`
191			`}`
192
193			`top->interrupt_input = interrupt_input & 0xFFFF;`
194
195			`if(interrupt_ack) {`
196			`if(top->interrupt_do == 0) {`
197			`printf("ERROR: interrupt_do not set for: %d\n", interrupt_vector);`
198			`exit(-1);`
199			`}`
200
201			`if(top->interrupt_vector != interrupt_vector) {`
202			`printf("ERROR: interrupt_vector %d != %d\n", interrupt_vector, top->interrupt_vector);`
203			`exit(-1);`
204			`}`
205
206			`top->interrupt_done = 1;`
207			`interrupt_ack = false;`
208			`}`
209			`}`
210
211			`//----------------------------------------------------------------------`
212
213			`if(state == S_DELAY) {`
214			`delay--;`
215
216			`if(delay == 0) {`
217			`state = S_IDLE;`
218			`}`
219			`}`
220			`else if(state == S_IO_READ_1) {`
221			`if(address >= 0x00A0 && address <= 0x00A1) {`
222			`top->slave_address = address & 0x1;`
223			`top->slave_read = 1;`
224			`}`
225			`else if(address >= 0x0020 && address <= 0x0021) {`
226			`top->master_address = address & 0x1;`
227			`top->master_read = 1;`
228			`}`
229			`else {`
230			`printf("ERROR: invalid io rd address: %08x\n", address);`
231			`exit(-1);`
232			`}`
233			`state = S_IO_READ_2;`
234			`}`
235			`else if(state == S_IO_READ_2) {`
236			`length--;`
237			`shifted_read++;`
238
239			`uint32 top_readdata = 0;`
240
241			`if(address >= 0x00A0 && address <= 0x00A1) top_readdata = top->slave_readdata & 0xFF;`
242			`else if(address >= 0x0020 && address <= 0x0021) top_readdata = top->master_readdata & 0xFF;`
243
244			`if(length > 0) {`
245			`address++;`
246
247			`if(address >= 0x00A0 && address <= 0x00A1) top->slave_address = address & 0x1;`
248			`else if(address >= 0x0020 && address <= 0x0021) top->master_address = address & 0x1;`
249			`else {`
250			`printf("ERROR: invalid io rd address: %08x\n", address);`
251			`exit(-1);`
252			`}`
253
254			`value_read \|= (top_readdata & 0xFF) << 24;`
255			`value_read >>= 8;`
256
257			`top->slave_read = 0;`
258			`top->master_read = 0;`
259			`state = S_IO_READ_3;`
260			`}`
261			`else {`
262			`top->slave_read = 0;`
263			`top->master_read = 0;`
264
265			`value_read \|= (top_readdata & 0xFF) << 24;`
266			`value_read >>= 8*(4 - shifted_read - shifted);`
267
268			`if(value_read != value_base) {`
269			`printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);`
270
271			`//if(! ((address_base == && byteena == )))`
272			`exit(0);`
273			`}`
274
275			`delay = 5;`
276			`state = S_DELAY;`
277			`}`
278			`}`
279			`else if(state == S_IO_READ_3) {`
280			`if(address >= 0x00A0 && address <= 0x00A1) top->slave_read = 1;`
281			`else if(address >= 0x0020 && address <= 0x0021) top->master_read = 1;`
282
283			`state = S_IO_READ_2;`
284			`}`
285			`else if(state == S_IO_WRITE_1) {`
286			`if(address >= 0x00A0 && address <= 0x00A1) {`
287			`top->slave_address = address & 0x1;`
288			`top->slave_write = 1;`
289			`top->slave_writedata = value & 0xFF;`
290			`}`
291			`else if(address >= 0x0020 && address <= 0x0021) {`
292			`top->master_address = address & 0x1;`
293			`top->master_write = 1;`
294			`top->master_writedata = value & 0xFF;`
295			`}`
296			`else {`
297			`printf("ERROR: invalid io wr address: %08x\n", address);`
298			`exit(-1);`
299			`}`
300			`state = S_IO_WRITE_2;`
301			`}`
302			`else if(state == S_IO_WRITE_2) {`
303			`length--;`
304
305			`if(length > 0) {`
306			`address++;`
307			`value >>= 8;`
308
309			`if(address >= 0x00A0 && address <= 0x00A1) {`
310			`top->slave_address = address & 0x1;`
311			`top->slave_writedata = value & 0xFF;`
312			`}`
313			`else if(address >= 0x0020 && address <= 0x0021) {`
314			`top->master_address = address & 0x1;`
315			`top->master_writedata = value & 0xFF;`
316			`}`
317			`else {`
318			`printf("ERROR: invalid io wr address: %08x\n", address);`
319			`exit(-1);`
320			`}`
321
322			`top->slave_write = 0;`
323			`top->master_write = 0;`
324			`state = S_IO_WRITE_3;`
325			`}`
326			`else {`
327			`top->slave_write = 0;`
328			`top->master_write = 0;`
329
330			`delay = 5;`
331			`state = S_DELAY;`
332			`}`
333			`}`
334			`else if(state == S_IO_WRITE_3) {`
335			`if(address >= 0x00A0 && address <= 0x00A1) top->slave_write = 1;`
336			`else if(address >= 0x0020 && address <= 0x0021) top->master_write = 1;`
337
338			`state = S_IO_WRITE_2;`
339			`}`
340
341			`//----------------------------------------------------------------------`
342
343			`top->clk = 0;`
344			`top->eval();`
345			`if(dump) tracer->dump(cycle++);`
346
347			`top->clk = 1;`
348			`top->eval();`
349			`if(dump) tracer->dump(cycle++);`
350
351			`tracer->flush();`
352			`}`
353			`tracer->close();`
354			`delete tracer;`
355			`delete top;`
356
357			`return 0;`
358			`}`
359
360			`//------------------------------------------------------------------------------`
361
362			`/*`
363			`input clk,`
364			`input rst_n,`
365
366			`//master pic 0020-0021`
367			`input master_address,`
368			`input master_read,`
369			`output reg [7:0] master_readdata,`
370			`input master_write,`
371			`input [7:0] master_writedata,`
372
373			`//slave pic 00A0-00A1`
374			`input slave_address,`
375			`input slave_read,`
376			`output reg [7:0] slave_readdata,`
377			`input slave_write,`
378			`input [7:0] slave_writedata,`
379
380			`//interrupt input`
381			`input [15:0] interrupt_input,`
382
383			`//interrupt output`
384			`output reg interrupt_do,`
385			`output reg [7:0] interrupt_vector,`
386			`input interrupt_done`
387			`*/`