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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [ps2/] [main.cpp] - Blame information for rev 7

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#include <cstdio>
#include <cstdlib>
 
#include "Vps2.h"
#include "verilated.h"
#include "verilated_vcd_c.h"
 
//------------------------------------------------------------------------------
 
typedef unsigned int uint32;
typedef unsigned char uint8;
 
//------------------------------------------------------------------------------
 
enum state_t {
    S_IDLE,
 
    S_IO_READ_1,
    S_IO_READ_2,
    S_IO_READ_3,
 
    S_IO_WRITE_1,
    S_IO_WRITE_2,
    S_IO_WRITE_3,
 
    S_DELAY
};
 
uint32  address_base;
uint32  address;
uint32  byteena;
uint32  value_base;
uint32  value;
state_t state = S_IDLE;
uint32  shifted;
uint32  shifted_read;
uint32  length;
uint32  value_read;
 
uint32  delay;
 
uint32  interrupt_input = 0;
uint32  interrupt_vector = 0;
bool    interrupt_ack = false;
 
void check_byteena(uint32 byteena) {
    if(byteena == 0 || byteena == 5 || byteena == 9 || byteena == 10 || byteena == 11 || byteena == 13) {
        printf("ERROR: invalid byteena: %x\n", byteena);
        exit(-1);
    }
 
    value_read = 0;
    address_base = address;
    value_base = value;
    shifted_read = 0;
 
    shifted = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) break;
 
        shifted++;
        address++;
        byteena >>= 1;
        value >>= 8;
    }
 
    length = 0;
    for(uint32 i=0; i<4; i++) {
        if(byteena & 1) length++;
 
        byteena >>= 1;
    }
}
 
bool is_address_ok(uint32 address) {
    if(address >= 0x0060 && address <= 0x0067) return true;
    if(address >= 0x0090 && address <= 0x009F) return true;
 
    return false;
}
 
bool next_record() {
    static FILE *fp = NULL;
 
    if(fp == NULL) {
        fp = fopen("./../../../../backup/run-3/track.txt", "rb");
        if(fp == NULL) {
            printf("ERROR: can not open file.\n");
            exit(-1);
        }
    }
 
    do {
        char line[256];
        memset(line, 0, sizeof(line));
 
        char *res = fgets(line, sizeof(line), fp);
        if(res == NULL) {
            fclose(fp);
            fp = NULL;
            return false;
        }
 
//printf("line: %s\n", line);
 
        int count;
 
        count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_READ_1;
printf("line: %s", line);
            return true;
        }
        count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);
        if(count == 3 && is_address_ok(address)) {
            check_byteena(byteena);
            state = S_IO_WRITE_1;
printf("line: %s", line);
            return true;
        }
 
        uint32 irq_signal = 0;
        count = sscanf(line, "raise_irq %d", &irq_signal);
        if(count == 1 && (irq_signal == 1 || irq_signal == 12)) {
            interrupt_input |= (1 << irq_signal);
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
        }
 
        count = sscanf(line, "lower_irq %d", &irq_signal);
        if(count == 1 && (irq_signal == 1 || irq_signal == 12)) {
            interrupt_input &= ~(1 << irq_signal);
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
        }
 
        count = sscanf(line, "IAC %d", &irq_signal);
        if(count == 1) {
            interrupt_ack = true;
            interrupt_vector = irq_signal;
printf("line: %s", line);
            delay = 5;
            state = S_DELAY;
            return true;
        }
 
    } while(true);
 
    return false;
}
 
//------------------------------------------------------------------------------
 
int main(int argc, char **argv) {
    Verilated::commandArgs(argc, argv);
 
    Verilated::traceEverOn(true);
    VerilatedVcdC* tracer = new VerilatedVcdC;
 
    Vps2 *top = new Vps2();
    top->trace (tracer, 99);
    //tracer->rolloverMB(1000000);
    tracer->open("ps2.vcd");
 
    bool dump = true;
 
    //reset
    top->clk = 0; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 1; top->eval();
    top->clk = 1; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 0; top->eval();
    top->clk = 0; top->rst_n = 1; top->eval();
 
    uint32 cycle = 0;
    while(!Verilated::gotFinish()) {
 
        //----------------------------------------------------------------------
 
        if(state == S_IDLE) {
            bool res = next_record();
            if(res == false) {
                printf("End of file.\n");
                break;
            }
 
        }
 
        //----------------------------------------------------------------------
 
        if(state == S_DELAY) {
            delay--;
 
            if(delay == 0) {
                state = S_IDLE;
            }
        }
        else if(state == S_IO_READ_1) {
            if(address >= 0x0060 && address <= 0x0067) {
                top->io_address = address & 0x7;
                top->io_read = 1;
            }
            else if(address >= 0x0090 && address <= 0x009F) {
                top->sysctl_address = address & 0xF;
                top->sysctl_read = 1;
            }
            else {
                printf("ERROR: invalid io rd address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_READ_2;
        }
        else if(state == S_IO_READ_2) {
            length--;
            shifted_read++;
 
            uint32 top_readdata = 0;
 
            if(address >= 0x0060 && address <= 0x0067)      top_readdata = top->io_readdata & 0xFF;
            else if(address >= 0x0090 && address <= 0x009F) top_readdata = top->sysctl_readdata & 0xFF;
 
            if(length > 0) {
                address++;
 
                if(address >= 0x0060 && address <= 0x0067)      top->io_address  = address & 0x1;
                else if(address >= 0x0090 && address <= 0x009F) top->sysctl_address = address & 0x1;
                else {
                    printf("ERROR: invalid io rd address: %08x\n", address);
                    exit(-1);
                }
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8;
 
                top->io_read = 0;
                top->sysctl_read = 0;
                state = S_IO_READ_3;
            }
            else {
                top->io_read = 0;
                top->sysctl_read = 0;
 
                value_read |= (top_readdata & 0xFF) << 24;
                value_read >>= 8*(4 - shifted_read - shifted);
 
                if(value_read != value_base) {
                    printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);
 
//if(! ((address_base ==  && byteena == )))
//exit(0);
                }
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_READ_3) {
            if(address >= 0x0060 && address <= 0x0067)      top->io_read = 1;
            else if(address >= 0x0090 && address <= 0x009F) top->sysctl_read = 1;
 
            state = S_IO_READ_2;
        }
        else if(state == S_IO_WRITE_1) {
            if(address >= 0x0060 && address <= 0x0067) {
                top->io_address = address & 0x7;
                top->io_write = 1;
                top->io_writedata = value & 0xFF;
            }
            else if(address >= 0x0090 && address <= 0x009F) {
                top->sysctl_address = address & 0xF;
                top->sysctl_write = 1;
                top->sysctl_writedata = value & 0xFF;
            }
            else {
                printf("ERROR: invalid io wr address: %08x\n", address);
                exit(-1);
            }
            state = S_IO_WRITE_2;
        }
        else if(state == S_IO_WRITE_2) {
            length--;
 
            if(length > 0) {
                address++;
                value >>= 8;
 
                if(address >= 0x0060 && address <= 0x0067) {
                    top->io_address = address & 0x7;
                    top->io_writedata = value & 0xFF;
                }
                else if(address >= 0x0090 && address <= 0x009F) {
                    top->sysctl_address = address & 0xF;
                    top->sysctl_writedata = value & 0xFF;
                }
                else {
                    printf("ERROR: invalid io wr address: %08x\n", address);
                    exit(-1);
                }
 
                top->io_write = 0;
                top->sysctl_write = 0;
                state = S_IO_WRITE_3;
            }
            else {
                top->io_write = 0;
                top->sysctl_write = 0;
 
                delay = 5;
                state = S_DELAY;
            }
        }
        else if(state == S_IO_WRITE_3) {
            if(address >= 0x0060 && address <= 0x0067)      top->io_write = 1;
            else if(address >= 0x0090 && address <= 0x009F) top->sysctl_write = 1;
 
            state = S_IO_WRITE_2;
        }
 
        //----------------------------------------------------------------------
 
        top->clk = 0;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        top->clk = 1;
        top->eval();
        if(dump) tracer->dump(cycle++);
 
        tracer->flush();
    }
    tracer->close();
    delete tracer;
    delete top;
 
    return 0;
}
 
//------------------------------------------------------------------------------
 
/*
module ps2(
    input                   clk,
    input                   rst_n,
 
    output reg              irq_keyb,
    output reg              irq_mouse,
 
    //io slave 0x60-0x67
    input       [2:0]       io_address,
    input                   io_read,
    output reg  [7:0]       io_readdata,
    input                   io_write,
    input       [7:0]       io_writedata,
 
    //io slave 0x90-0x9F
    input       [3:0]       sysctl_address,
    input                   sysctl_read,
    output reg  [7:0]       sysctl_readdata,
    input                   sysctl_write,
    input       [7:0]       sysctl_writedata,
 
    //speaker port 61h
    output                  speaker_61h_read,
    input       [7:0]       speaker_61h_readdata,
    output                  speaker_61h_write,
    output      [7:0]       speaker_61h_writedata,
 
    //output port
    output reg              output_a20_enable,
    output reg              output_reset_n,
 
    //ps2 keyboard
    inout                   ps2_kbclk,
    inout                   ps2_kbdat,
 
    //ps2 mouse
    inout                   ps2_mouseclk,
    inout                   ps2_mousedat
);
*/

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[/] [ao486/] [trunk/] [sim/] [verilator/] [soc/] [ps2/] [main.cpp] - Blame information for rev 7

Line No.	Rev	Author	Line
1	2	alfik	`#include <cstdio>`
2			`#include <cstdlib>`
3
4			`#include "Vps2.h"`
5			`#include "verilated.h"`
6			`#include "verilated_vcd_c.h"`
7
8			`//------------------------------------------------------------------------------`
9
10			`typedef unsigned int uint32;`
11			`typedef unsigned char uint8;`
12
13			`//------------------------------------------------------------------------------`
14
15			`enum state_t {`
16			`S_IDLE,`
17
18			`S_IO_READ_1,`
19			`S_IO_READ_2,`
20			`S_IO_READ_3,`
21
22			`S_IO_WRITE_1,`
23			`S_IO_WRITE_2,`
24			`S_IO_WRITE_3,`
25
26			`S_DELAY`
27			`};`
28
29			`uint32 address_base;`
30			`uint32 address;`
31			`uint32 byteena;`
32			`uint32 value_base;`
33			`uint32 value;`
34			`state_t state = S_IDLE;`
35			`uint32 shifted;`
36			`uint32 shifted_read;`
37			`uint32 length;`
38			`uint32 value_read;`
39
40			`uint32 delay;`
41
42			`uint32 interrupt_input = 0;`
43			`uint32 interrupt_vector = 0;`
44			`bool interrupt_ack = false;`
45
46			`void check_byteena(uint32 byteena) {`
47			`if(byteena == 0 \|\| byteena == 5 \|\| byteena == 9 \|\| byteena == 10 \|\| byteena == 11 \|\| byteena == 13) {`
48			`printf("ERROR: invalid byteena: %x\n", byteena);`
49			`exit(-1);`
50			`}`
51
52			`value_read = 0;`
53			`address_base = address;`
54			`value_base = value;`
55			`shifted_read = 0;`
56
57			`shifted = 0;`
58			`for(uint32 i=0; i<4; i++) {`
59			`if(byteena & 1) break;`
60
61			`shifted++;`
62			`address++;`
63			`byteena >>= 1;`
64			`value >>= 8;`
65			`}`
66
67			`length = 0;`
68			`for(uint32 i=0; i<4; i++) {`
69			`if(byteena & 1) length++;`
70
71			`byteena >>= 1;`
72			`}`
73			`}`
74
75			`bool is_address_ok(uint32 address) {`
76			`if(address >= 0x0060 && address <= 0x0067) return true;`
77			`if(address >= 0x0090 && address <= 0x009F) return true;`
78
79			`return false;`
80			`}`
81
82			`bool next_record() {`
83			`static FILE *fp = NULL;`
84
85			`if(fp == NULL) {`
86			`fp = fopen("./../../../../backup/run-3/track.txt", "rb");`
87			`if(fp == NULL) {`
88			`printf("ERROR: can not open file.\n");`
89			`exit(-1);`
90			`}`
91			`}`
92
93			`do {`
94			`char line[256];`
95			`memset(line, 0, sizeof(line));`
96
97			`char *res = fgets(line, sizeof(line), fp);`
98			`if(res == NULL) {`
99			`fclose(fp);`
100			`fp = NULL;`
101			`return false;`
102			`}`
103
104			`//printf("line: %s\n", line);`
105
106			`int count;`
107
108			`count = sscanf(line, "io rd %x %x %x", &address, &byteena, &value);`
109			`if(count == 3 && is_address_ok(address)) {`
110			`check_byteena(byteena);`
111			`state = S_IO_READ_1;`
112			`printf("line: %s", line);`
113			`return true;`
114			`}`
115			`count = sscanf(line, "io wr %x %x %x", &address, &byteena, &value);`
116			`if(count == 3 && is_address_ok(address)) {`
117			`check_byteena(byteena);`
118			`state = S_IO_WRITE_1;`
119			`printf("line: %s", line);`
120			`return true;`
121			`}`
122
123			`uint32 irq_signal = 0;`
124			`count = sscanf(line, "raise_irq %d", &irq_signal);`
125			`if(count == 1 && (irq_signal == 1 \|\| irq_signal == 12)) {`
126			`interrupt_input \|= (1 << irq_signal);`
127			`printf("line: %s", line);`
128			`delay = 5;`
129			`state = S_DELAY;`
130			`return true;`
131			`}`
132
133			`count = sscanf(line, "lower_irq %d", &irq_signal);`
134			`if(count == 1 && (irq_signal == 1 \|\| irq_signal == 12)) {`
135			`interrupt_input &= ~(1 << irq_signal);`
136			`printf("line: %s", line);`
137			`delay = 5;`
138			`state = S_DELAY;`
139			`return true;`
140			`}`
141
142			`count = sscanf(line, "IAC %d", &irq_signal);`
143			`if(count == 1) {`
144			`interrupt_ack = true;`
145			`interrupt_vector = irq_signal;`
146			`printf("line: %s", line);`
147			`delay = 5;`
148			`state = S_DELAY;`
149			`return true;`
150			`}`
151
152			`} while(true);`
153
154			`return false;`
155			`}`
156
157			`//------------------------------------------------------------------------------`
158
159			`int main(int argc, char **argv) {`
160			`Verilated::commandArgs(argc, argv);`
161
162			`Verilated::traceEverOn(true);`
163			`VerilatedVcdC* tracer = new VerilatedVcdC;`
164
165			`Vps2 *top = new Vps2();`
166			`top->trace (tracer, 99);`
167			`//tracer->rolloverMB(1000000);`
168			`tracer->open("ps2.vcd");`
169
170			`bool dump = true;`
171
172			`//reset`
173			`top->clk = 0; top->rst_n = 1; top->eval();`
174			`top->clk = 1; top->rst_n = 1; top->eval();`
175			`top->clk = 1; top->rst_n = 0; top->eval();`
176			`top->clk = 0; top->rst_n = 0; top->eval();`
177			`top->clk = 0; top->rst_n = 1; top->eval();`
178
179			`uint32 cycle = 0;`
180			`while(!Verilated::gotFinish()) {`
181
182			`//----------------------------------------------------------------------`
183
184			`if(state == S_IDLE) {`
185			`bool res = next_record();`
186			`if(res == false) {`
187			`printf("End of file.\n");`
188			`break;`
189			`}`
190
191			`}`
192
193			`//----------------------------------------------------------------------`
194
195			`if(state == S_DELAY) {`
196			`delay--;`
197
198			`if(delay == 0) {`
199			`state = S_IDLE;`
200			`}`
201			`}`
202			`else if(state == S_IO_READ_1) {`
203			`if(address >= 0x0060 && address <= 0x0067) {`
204			`top->io_address = address & 0x7;`
205			`top->io_read = 1;`
206			`}`
207			`else if(address >= 0x0090 && address <= 0x009F) {`
208			`top->sysctl_address = address & 0xF;`
209			`top->sysctl_read = 1;`
210			`}`
211			`else {`
212			`printf("ERROR: invalid io rd address: %08x\n", address);`
213			`exit(-1);`
214			`}`
215			`state = S_IO_READ_2;`
216			`}`
217			`else if(state == S_IO_READ_2) {`
218			`length--;`
219			`shifted_read++;`
220
221			`uint32 top_readdata = 0;`
222
223			`if(address >= 0x0060 && address <= 0x0067) top_readdata = top->io_readdata & 0xFF;`
224			`else if(address >= 0x0090 && address <= 0x009F) top_readdata = top->sysctl_readdata & 0xFF;`
225
226			`if(length > 0) {`
227			`address++;`
228
229			`if(address >= 0x0060 && address <= 0x0067) top->io_address = address & 0x1;`
230			`else if(address >= 0x0090 && address <= 0x009F) top->sysctl_address = address & 0x1;`
231			`else {`
232			`printf("ERROR: invalid io rd address: %08x\n", address);`
233			`exit(-1);`
234			`}`
235
236			`value_read \|= (top_readdata & 0xFF) << 24;`
237			`value_read >>= 8;`
238
239			`top->io_read = 0;`
240			`top->sysctl_read = 0;`
241			`state = S_IO_READ_3;`
242			`}`
243			`else {`
244			`top->io_read = 0;`
245			`top->sysctl_read = 0;`
246
247			`value_read \|= (top_readdata & 0xFF) << 24;`
248			`value_read >>= 8*(4 - shifted_read - shifted);`
249
250			`if(value_read != value_base) {`
251			`printf("mismatch io rd %08x %x %08x != %08x\n", address_base, byteena, value_base, value_read);`
252
253			`//if(! ((address_base == && byteena == )))`
254			`//exit(0);`
255			`}`
256
257			`delay = 5;`
258			`state = S_DELAY;`
259			`}`
260			`}`
261			`else if(state == S_IO_READ_3) {`
262			`if(address >= 0x0060 && address <= 0x0067) top->io_read = 1;`
263			`else if(address >= 0x0090 && address <= 0x009F) top->sysctl_read = 1;`
264
265			`state = S_IO_READ_2;`
266			`}`
267			`else if(state == S_IO_WRITE_1) {`
268			`if(address >= 0x0060 && address <= 0x0067) {`
269			`top->io_address = address & 0x7;`
270			`top->io_write = 1;`
271			`top->io_writedata = value & 0xFF;`
272			`}`
273			`else if(address >= 0x0090 && address <= 0x009F) {`
274			`top->sysctl_address = address & 0xF;`
275			`top->sysctl_write = 1;`
276			`top->sysctl_writedata = value & 0xFF;`
277			`}`
278			`else {`
279			`printf("ERROR: invalid io wr address: %08x\n", address);`
280			`exit(-1);`
281			`}`
282			`state = S_IO_WRITE_2;`
283			`}`
284			`else if(state == S_IO_WRITE_2) {`
285			`length--;`
286
287			`if(length > 0) {`
288			`address++;`
289			`value >>= 8;`
290
291			`if(address >= 0x0060 && address <= 0x0067) {`
292			`top->io_address = address & 0x7;`
293			`top->io_writedata = value & 0xFF;`
294			`}`
295			`else if(address >= 0x0090 && address <= 0x009F) {`
296			`top->sysctl_address = address & 0xF;`
297			`top->sysctl_writedata = value & 0xFF;`
298			`}`
299			`else {`
300			`printf("ERROR: invalid io wr address: %08x\n", address);`
301			`exit(-1);`
302			`}`
303
304			`top->io_write = 0;`
305			`top->sysctl_write = 0;`
306			`state = S_IO_WRITE_3;`
307			`}`
308			`else {`
309			`top->io_write = 0;`
310			`top->sysctl_write = 0;`
311
312			`delay = 5;`
313			`state = S_DELAY;`
314			`}`
315			`}`
316			`else if(state == S_IO_WRITE_3) {`
317			`if(address >= 0x0060 && address <= 0x0067) top->io_write = 1;`
318			`else if(address >= 0x0090 && address <= 0x009F) top->sysctl_write = 1;`
319
320			`state = S_IO_WRITE_2;`
321			`}`
322
323			`//----------------------------------------------------------------------`
324
325			`top->clk = 0;`
326			`top->eval();`
327			`if(dump) tracer->dump(cycle++);`
328
329			`top->clk = 1;`
330			`top->eval();`
331			`if(dump) tracer->dump(cycle++);`
332
333			`tracer->flush();`
334			`}`
335			`tracer->close();`
336			`delete tracer;`
337			`delete top;`
338
339			`return 0;`
340			`}`
341
342			`//------------------------------------------------------------------------------`
343
344			`/*`
345			`module ps2(`
346			`input clk,`
347			`input rst_n,`
348
349			`output reg irq_keyb,`
350			`output reg irq_mouse,`
351
352			`//io slave 0x60-0x67`
353			`input [2:0] io_address,`
354			`input io_read,`
355			`output reg [7:0] io_readdata,`
356			`input io_write,`
357			`input [7:0] io_writedata,`
358
359			`//io slave 0x90-0x9F`
360			`input [3:0] sysctl_address,`
361			`input sysctl_read,`
362			`output reg [7:0] sysctl_readdata,`
363			`input sysctl_write,`
364			`input [7:0] sysctl_writedata,`
365
366			`//speaker port 61h`
367			`output speaker_61h_read,`
368			`input [7:0] speaker_61h_readdata,`
369			`output speaker_61h_write,`
370			`output [7:0] speaker_61h_writedata,`
371
372			`//output port`
373			`output reg output_a20_enable,`
374			`output reg output_reset_n,`
375
376			`//ps2 keyboard`
377			`inout ps2_kbclk,`
378			`inout ps2_kbdat,`
379
380			`//ps2 mouse`
381			`inout ps2_mouseclk,`
382			`inout ps2_mousedat`
383			`);`
384			`*/`