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alfik |
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
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# Date created = 22:37:57 July 09, 2013
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# ao486_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name TOP_LEVEL_ENTITY ao486
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:37:57 JULY 09, 2013"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name SEARCH_PATH /home/alek/aktualne/ao486/rtl
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_string.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_stack.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_register.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_debug.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write_commands.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/write.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_segment.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_mutex.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_effective_address.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_debug.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read_commands.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/read.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/pipeline.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/microcode_commands.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/microcode.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/fetch.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_shift.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_offset.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_multiply.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_divide.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute_commands.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/execute.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_regs.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_ready.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_prefix.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode_commands.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/decode.v
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set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/condition.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_regs.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb_memtype.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/tlb.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch_control.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/prefetch.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_write.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_read.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeline.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_writeburst.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readline.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readcode.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_readburst.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcachewrite.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/link_dcacheread.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_read.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_matched.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache_control_ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/icache.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_write.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_to_icache_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_read.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_matched.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache_control_ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/dcache.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/cache_data_ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/memory/avalon_mem.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_prefetch_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_icache_control_ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_to_icache_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_dcache_control_ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/altera/altera_cache_data_ram.v
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set_global_assignment -name VERILOG_FILE ../../rtl/exception.v
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set_global_assignment -name VERILOG_FILE ../../rtl/global_regs.v
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set_global_assignment -name VERILOG_FILE ../../rtl/defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/avalon_io.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ao486.v
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set_global_assignment -name SDC_FILE ao486.sdc
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name SEED 1
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set_global_assignment -name ECO_OPTIMIZE_TIMING OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.5
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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