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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 09:25:05 September 22, 2013
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# soc_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name TOP_LEVEL_ENTITY ps2_soc
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:25:05 SEPTEMBER 22, 2013"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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#============================================================
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# PS2
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#============================================================
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2
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set_location_assignment PIN_G6 -to PS2_CLK
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set_location_assignment PIN_H5 -to PS2_DAT
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set_location_assignment PIN_G5 -to PS2_CLK2
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set_location_assignment PIN_F5 -to PS2_DAT2
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#============================================================
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# CLOCK
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#============================================================
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set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
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set_location_assignment PIN_Y2 -to CLOCK_50
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set_global_assignment -name QIP_FILE soc/synthesis/soc.qip
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set_global_assignment -name VERILOG_FILE ps2_soc.v
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set_global_assignment -name SDC_FILE soc.sdc
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
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set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
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set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:pll_inst|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to PS2_CLK2 -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to PS2_DAT2 -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "soc:u0|ps2:ps2_0|status_inputbufferfull" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "soc:u0|ps2:ps2_0|status_mousebufferfull" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "soc:u0|ps2:ps2_0|status_outputbufferfull" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to PS2_CLK2 -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to PS2_DAT2 -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "soc:u0|ps2:ps2_0|status_inputbufferfull" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "soc:u0|ps2:ps2_0|status_mousebufferfull" -section_id auto_signaltap_0
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set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "soc:u0|ps2:ps2_0|status_outputbufferfull" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=5" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=5" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=38" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=8691" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=6333" -section_id auto_signaltap_0
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name SLD_FILE /home/alek/aktualne/ps2/output_files/stp1_auto_stripped.stp
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