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[/] [ao486/] [trunk/] [syn/] [components/] [ps2/] [soc.sdc] - Blame information for rev 2

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1 2 alfik
#************************************************************
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# THIS IS A WIZARD-GENERATED FILE.
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#
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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#
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#************************************************************
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors.  Please refer to the
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# applicable agreement for further details.
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# Clock constraints
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create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}]
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# Automatically constrain PLL and other generated clocks
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derive_pll_clocks -create_base_clocks
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# Automatically calculate clock uncertainty to jitter and other effects.
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derive_clock_uncertainty
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# tsu/th constraints
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# tco constraints
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# tpd constraints
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