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[/] [ao486/] [trunk/] [syn/] [soc/] [firmware/] [exe_bsp/] [system.h] - Blame information for rev 8

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1 2 alfik
/*
2
 * system.h - SOPC Builder system and BSP software package information
3
 *
4
 * Machine generated for CPU 'nios2' in SOPC Builder design 'system'
5
 * SOPC Builder design path: ../../system.sopcinfo
6
 *
7
 * Generated: Fri Jan 17 00:23:52 CET 2014
8
 */
9
 
10
/*
11
 * DO NOT MODIFY THIS FILE
12
 *
13
 * Changing this file will have subtle consequences
14
 * which will almost certainly lead to a nonfunctioning
15
 * system. If you do modify this file, be aware that your
16
 * changes will be overwritten and lost when this file
17
 * is generated again.
18
 *
19
 * DO NOT MODIFY THIS FILE
20
 */
21
 
22
/*
23
 * License Agreement
24
 *
25
 * Copyright (c) 2008
26
 * Altera Corporation, San Jose, California, USA.
27
 * All rights reserved.
28
 *
29
 * Permission is hereby granted, free of charge, to any person obtaining a
30
 * copy of this software and associated documentation files (the "Software"),
31
 * to deal in the Software without restriction, including without limitation
32
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
33
 * and/or sell copies of the Software, and to permit persons to whom the
34
 * Software is furnished to do so, subject to the following conditions:
35
 *
36
 * The above copyright notice and this permission notice shall be included in
37
 * all copies or substantial portions of the Software.
38
 *
39
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
40
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
41
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
42
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
43
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
45
 * DEALINGS IN THE SOFTWARE.
46
 *
47
 * This agreement shall be governed in all respects by the laws of the State
48
 * of California and by the laws of the United States of America.
49
 */
50
 
51
#ifndef __SYSTEM_H_
52
#define __SYSTEM_H_
53
 
54
/* Include definitions from linker script generator */
55
#include "linker.h"
56
 
57
 
58
/*
59
 * CPU configuration
60
 *
61
 */
62
 
63
#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"
64
#define ALT_CPU_BIG_ENDIAN 0
65
#define ALT_CPU_BREAK_ADDR 0x00009820
66
#define ALT_CPU_CPU_FREQ 30000000u
67
#define ALT_CPU_CPU_ID_SIZE 1
68
#define ALT_CPU_CPU_ID_VALUE 0x00000000
69
#define ALT_CPU_CPU_IMPLEMENTATION "tiny"
70
#define ALT_CPU_DATA_ADDR_WIDTH 0x1c
71
#define ALT_CPU_DCACHE_LINE_SIZE 0
72
#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
73
#define ALT_CPU_DCACHE_SIZE 0
74
#define ALT_CPU_EXCEPTION_ADDR 0x00010020
75
#define ALT_CPU_FLUSHDA_SUPPORTED
76
#define ALT_CPU_FREQ 30000000
77
#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
78
#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0
79
#define ALT_CPU_HARDWARE_MULX_PRESENT 0
80
#define ALT_CPU_HAS_DEBUG_CORE 1
81
#define ALT_CPU_HAS_DEBUG_STUB
82
#define ALT_CPU_HAS_JMPI_INSTRUCTION
83
#define ALT_CPU_ICACHE_LINE_SIZE 0
84
#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
85
#define ALT_CPU_ICACHE_SIZE 0
86
#define ALT_CPU_INST_ADDR_WIDTH 0x11
87
#define ALT_CPU_NAME "nios2"
88
#define ALT_CPU_RESET_ADDR 0x00010000
89
 
90
 
91
/*
92
 * CPU configuration (with legacy prefix - don't use these anymore)
93
 *
94
 */
95
 
96
#define NIOS2_BIG_ENDIAN 0
97
#define NIOS2_BREAK_ADDR 0x00009820
98
#define NIOS2_CPU_FREQ 30000000u
99
#define NIOS2_CPU_ID_SIZE 1
100
#define NIOS2_CPU_ID_VALUE 0x00000000
101
#define NIOS2_CPU_IMPLEMENTATION "tiny"
102
#define NIOS2_DATA_ADDR_WIDTH 0x1c
103
#define NIOS2_DCACHE_LINE_SIZE 0
104
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
105
#define NIOS2_DCACHE_SIZE 0
106
#define NIOS2_EXCEPTION_ADDR 0x00010020
107
#define NIOS2_FLUSHDA_SUPPORTED
108
#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
109
#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0
110
#define NIOS2_HARDWARE_MULX_PRESENT 0
111
#define NIOS2_HAS_DEBUG_CORE 1
112
#define NIOS2_HAS_DEBUG_STUB
113
#define NIOS2_HAS_JMPI_INSTRUCTION
114
#define NIOS2_ICACHE_LINE_SIZE 0
115
#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
116
#define NIOS2_ICACHE_SIZE 0
117
#define NIOS2_INST_ADDR_WIDTH 0x11
118
#define NIOS2_RESET_ADDR 0x00010000
119
 
120
 
121
/*
122
 * Define for each module class mastered by the CPU
123
 *
124
 */
125
 
126
#define __ALTERA_AVALON_JTAG_UART
127
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
128
#define __ALTERA_AVALON_ONCHIP_MEMORY2
129
#define __ALTERA_AVALON_PIO
130
#define __ALTERA_NIOS2_QSYS
131
#define __DRIVER_SD
132
#define __FLOPPY
133
#define __HDD
134
#define __PC_BUS
135
#define __PIT
136
#define __RTC
137
#define __SOUND
138
#define __VGA
139
 
140
 
141
/*
142
 * System configuration
143
 *
144
 */
145
 
146
#define ALT_DEVICE_FAMILY "Cyclone IV E"
147
#define ALT_ENHANCED_INTERRUPT_API_PRESENT
148
#define ALT_IRQ_BASE NULL
149
#define ALT_LOG_PORT "/dev/null"
150
#define ALT_LOG_PORT_BASE 0x0
151
#define ALT_LOG_PORT_DEV null
152
#define ALT_LOG_PORT_TYPE ""
153
#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
154
#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
155
#define ALT_NUM_INTERRUPT_CONTROLLERS 1
156
#define ALT_STDERR "/dev/null"
157
#define ALT_STDERR_BASE 0x0
158
#define ALT_STDERR_DEV null
159
#define ALT_STDERR_TYPE ""
160
#define ALT_STDIN "/dev/null"
161
#define ALT_STDIN_BASE 0x0
162
#define ALT_STDIN_DEV null
163
#define ALT_STDIN_TYPE ""
164
#define ALT_STDOUT "/dev/jtag_uart"
165
#define ALT_STDOUT_BASE 0x8888
166
#define ALT_STDOUT_DEV jtag_uart
167
#define ALT_STDOUT_IS_JTAG_UART
168
#define ALT_STDOUT_PRESENT
169
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
170
#define ALT_SYSTEM_NAME "system"
171
 
172
 
173
/*
174
 * driver_sd configuration
175
 *
176
 */
177
 
178
#define ALT_MODULE_CLASS_driver_sd driver_sd
179
#define DRIVER_SD_BASE 0x0
180
#define DRIVER_SD_IRQ -1
181
#define DRIVER_SD_IRQ_INTERRUPT_CONTROLLER_ID -1
182
#define DRIVER_SD_NAME "/dev/driver_sd"
183
#define DRIVER_SD_SPAN 16
184
#define DRIVER_SD_TYPE "driver_sd"
185
 
186
 
187
/*
188
 * floppy configuration
189
 *
190
 */
191
 
192
#define ALT_MODULE_CLASS_floppy floppy
193
#define FLOPPY_BASE 0x8800
194
#define FLOPPY_IRQ -1
195
#define FLOPPY_IRQ_INTERRUPT_CONTROLLER_ID -1
196
#define FLOPPY_NAME "/dev/floppy"
197
#define FLOPPY_SPAN 64
198
#define FLOPPY_TYPE "floppy"
199
 
200
 
201
/*
202
 * hal configuration
203
 *
204
 */
205
 
206
#define ALT_MAX_FD 4
207
#define ALT_SYS_CLK none
208
#define ALT_TIMESTAMP_CLK none
209
 
210
 
211
/*
212
 * hdd configuration
213
 *
214
 */
215
 
216
#define ALT_MODULE_CLASS_hdd hdd
217
#define HDD_BASE 0x8840
218
#define HDD_IRQ -1
219
#define HDD_IRQ_INTERRUPT_CONTROLLER_ID -1
220
#define HDD_NAME "/dev/hdd"
221
#define HDD_SPAN 32
222
#define HDD_TYPE "hdd"
223
 
224
 
225
/*
226
 * jtag_uart configuration
227
 *
228
 */
229
 
230
#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart
231
#define JTAG_UART_BASE 0x8888
232
#define JTAG_UART_IRQ 0
233
#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0
234
#define JTAG_UART_NAME "/dev/jtag_uart"
235
#define JTAG_UART_READ_DEPTH 256
236
#define JTAG_UART_READ_THRESHOLD 8
237
#define JTAG_UART_SPAN 8
238
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
239
#define JTAG_UART_WRITE_DEPTH 256
240
#define JTAG_UART_WRITE_THRESHOLD 8
241
 
242
 
243
/*
244
 * onchip_for_nios2 configuration
245
 *
246
 */
247
 
248
#define ALT_MODULE_CLASS_onchip_for_nios2 altera_avalon_onchip_memory2
249
#define ONCHIP_FOR_NIOS2_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
250
#define ONCHIP_FOR_NIOS2_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
251
#define ONCHIP_FOR_NIOS2_BASE 0x10000
252
#define ONCHIP_FOR_NIOS2_CONTENTS_INFO ""
253
#define ONCHIP_FOR_NIOS2_DUAL_PORT 0
254
#define ONCHIP_FOR_NIOS2_GUI_RAM_BLOCK_TYPE "AUTO"
255
#define ONCHIP_FOR_NIOS2_INIT_CONTENTS_FILE "system_onchip_for_nios2"
256
#define ONCHIP_FOR_NIOS2_INIT_MEM_CONTENT 1
257
#define ONCHIP_FOR_NIOS2_INSTANCE_ID "NONE"
258
#define ONCHIP_FOR_NIOS2_IRQ -1
259
#define ONCHIP_FOR_NIOS2_IRQ_INTERRUPT_CONTROLLER_ID -1
260
#define ONCHIP_FOR_NIOS2_NAME "/dev/onchip_for_nios2"
261
#define ONCHIP_FOR_NIOS2_NON_DEFAULT_INIT_FILE_ENABLED 0
262
#define ONCHIP_FOR_NIOS2_RAM_BLOCK_TYPE "AUTO"
263
#define ONCHIP_FOR_NIOS2_READ_DURING_WRITE_MODE "DONT_CARE"
264
#define ONCHIP_FOR_NIOS2_SINGLE_CLOCK_OP 0
265
#define ONCHIP_FOR_NIOS2_SIZE_MULTIPLE 1
266
#define ONCHIP_FOR_NIOS2_SIZE_VALUE 32768
267
#define ONCHIP_FOR_NIOS2_SPAN 32768
268
#define ONCHIP_FOR_NIOS2_TYPE "altera_avalon_onchip_memory2"
269
#define ONCHIP_FOR_NIOS2_WRITABLE 1
270
 
271
 
272
/*
273
 * pc_bus configuration
274
 *
275
 */
276
 
277
#define ALT_MODULE_CLASS_pc_bus pc_bus
278
#define PC_BUS_BASE 0x88a0
279
#define PC_BUS_IRQ -1
280
#define PC_BUS_IRQ_INTERRUPT_CONTROLLER_ID -1
281
#define PC_BUS_NAME "/dev/pc_bus"
282
#define PC_BUS_SPAN 16
283
#define PC_BUS_TYPE "pc_bus"
284
 
285
 
286
/*
287
 * pio_input configuration
288
 *
289
 */
290
 
291
#define ALT_MODULE_CLASS_pio_input altera_avalon_pio
292
#define PIO_INPUT_BASE 0x8890
293
#define PIO_INPUT_BIT_CLEARING_EDGE_REGISTER 0
294
#define PIO_INPUT_BIT_MODIFYING_OUTPUT_REGISTER 0
295
#define PIO_INPUT_CAPTURE 1
296
#define PIO_INPUT_DATA_WIDTH 8
297
#define PIO_INPUT_DO_TEST_BENCH_WIRING 0
298
#define PIO_INPUT_DRIVEN_SIM_VALUE 0
299
#define PIO_INPUT_EDGE_TYPE "RISING"
300
#define PIO_INPUT_FREQ 30000000
301
#define PIO_INPUT_HAS_IN 1
302
#define PIO_INPUT_HAS_OUT 0
303
#define PIO_INPUT_HAS_TRI 0
304
#define PIO_INPUT_IRQ -1
305
#define PIO_INPUT_IRQ_INTERRUPT_CONTROLLER_ID -1
306
#define PIO_INPUT_IRQ_TYPE "NONE"
307
#define PIO_INPUT_NAME "/dev/pio_input"
308
#define PIO_INPUT_RESET_VALUE 0
309
#define PIO_INPUT_SPAN 16
310
#define PIO_INPUT_TYPE "altera_avalon_pio"
311
 
312
 
313
/*
314
 * pio_output configuration
315
 *
316
 */
317
 
318
#define ALT_MODULE_CLASS_pio_output altera_avalon_pio
319
#define PIO_OUTPUT_BASE 0x8860
320
#define PIO_OUTPUT_BIT_CLEARING_EDGE_REGISTER 0
321
#define PIO_OUTPUT_BIT_MODIFYING_OUTPUT_REGISTER 0
322
#define PIO_OUTPUT_CAPTURE 0
323
#define PIO_OUTPUT_DATA_WIDTH 8
324
#define PIO_OUTPUT_DO_TEST_BENCH_WIRING 0
325
#define PIO_OUTPUT_DRIVEN_SIM_VALUE 0
326
#define PIO_OUTPUT_EDGE_TYPE "NONE"
327
#define PIO_OUTPUT_FREQ 30000000
328
#define PIO_OUTPUT_HAS_IN 0
329
#define PIO_OUTPUT_HAS_OUT 1
330
#define PIO_OUTPUT_HAS_TRI 0
331
#define PIO_OUTPUT_IRQ -1
332
#define PIO_OUTPUT_IRQ_INTERRUPT_CONTROLLER_ID -1
333
#define PIO_OUTPUT_IRQ_TYPE "NONE"
334
#define PIO_OUTPUT_NAME "/dev/pio_output"
335
#define PIO_OUTPUT_RESET_VALUE 255
336
#define PIO_OUTPUT_SPAN 16
337
#define PIO_OUTPUT_TYPE "altera_avalon_pio"
338
 
339
 
340
/*
341
 * pit configuration
342
 *
343
 */
344
 
345
#define ALT_MODULE_CLASS_pit pit
346
#define PIT_BASE 0x8880
347
#define PIT_IRQ -1
348
#define PIT_IRQ_INTERRUPT_CONTROLLER_ID -1
349
#define PIT_NAME "/dev/pit"
350
#define PIT_SPAN 8
351
#define PIT_TYPE "pit"
352
 
353
 
354
/*
355
 * rtc configuration
356
 *
357
 */
358
 
359
#define ALT_MODULE_CLASS_rtc rtc
360
#define RTC_BASE 0x8c00
361
#define RTC_IRQ -1
362
#define RTC_IRQ_INTERRUPT_CONTROLLER_ID -1
363
#define RTC_NAME "/dev/rtc"
364
#define RTC_SPAN 1024
365
#define RTC_TYPE "rtc"
366
 
367
 
368
/*
369
 * sdram configuration
370
 *
371
 */
372
 
373
#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller
374
#define SDRAM_BASE 0x8000000
375
#define SDRAM_CAS_LATENCY 2
376
#define SDRAM_CONTENTS_INFO
377
#define SDRAM_INIT_NOP_DELAY 0.0
378
#define SDRAM_INIT_REFRESH_COMMANDS 2
379
#define SDRAM_IRQ -1
380
#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1
381
#define SDRAM_IS_INITIALIZED 1
382
#define SDRAM_NAME "/dev/sdram"
383
#define SDRAM_POWERUP_DELAY 100.0
384
#define SDRAM_REFRESH_PERIOD 15.625
385
#define SDRAM_REGISTER_DATA_IN 1
386
#define SDRAM_SDRAM_ADDR_WIDTH 0x19
387
#define SDRAM_SDRAM_BANK_WIDTH 2
388
#define SDRAM_SDRAM_COL_WIDTH 10
389
#define SDRAM_SDRAM_DATA_WIDTH 32
390
#define SDRAM_SDRAM_NUM_BANKS 4
391
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
392
#define SDRAM_SDRAM_ROW_WIDTH 13
393
#define SDRAM_SHARED_DATA 0
394
#define SDRAM_SIM_MODEL_BASE 0
395
#define SDRAM_SPAN 134217728
396
#define SDRAM_STARVATION_INDICATOR 0
397
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
398
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
399
#define SDRAM_T_AC 5.5
400
#define SDRAM_T_MRD 3
401
#define SDRAM_T_RCD 20.0
402
#define SDRAM_T_RFC 70.0
403
#define SDRAM_T_RP 20.0
404
#define SDRAM_T_WR 14.0
405
 
406
 
407
/*
408
 * sound configuration
409
 *
410
 */
411
 
412
#define ALT_MODULE_CLASS_sound sound
413
#define SOUND_BASE 0x9000
414
#define SOUND_IRQ -1
415
#define SOUND_IRQ_INTERRUPT_CONTROLLER_ID -1
416
#define SOUND_NAME "/dev/sound"
417
#define SOUND_SPAN 2048
418
#define SOUND_TYPE "sound"
419
 
420
 
421
/*
422
 * vga configuration
423
 *
424
 */
425
 
426
#define ALT_MODULE_CLASS_vga vga
427
#define VGA_BASE 0xa000
428
#define VGA_IRQ -1
429
#define VGA_IRQ_INTERRUPT_CONTROLLER_ID -1
430
#define VGA_NAME "/dev/vga"
431
#define VGA_SPAN 1024
432
#define VGA_TYPE "vga"
433
 
434
#endif /* __SYSTEM_H_ */

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