| 1 |
12 |
alfik |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
| 2 |
|
|
<html xmlns="http://www.w3.org/1999/xhtml">
|
| 3 |
|
|
<head>
|
| 4 |
|
|
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
| 5 |
|
|
<title>ao68000: ao68000.v Source File</title>
|
| 6 |
|
|
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
| 7 |
|
|
<link href="doxygen.css" rel="stylesheet" type="text/css"/>
|
| 8 |
|
|
</head>
|
| 9 |
|
|
<body>
|
| 10 |
|
|
<!-- Generated by Doxygen 1.7.2 -->
|
| 11 |
|
|
<div class="navigation" id="top">
|
| 12 |
|
|
<div class="tabs">
|
| 13 |
|
|
<ul class="tablist">
|
| 14 |
|
|
<li><a href="index.html"><span>Main Page</span></a></li>
|
| 15 |
|
|
<li><a href="modules.html"><span>Modules</span></a></li>
|
| 16 |
|
|
<li><a href="annotated.html"><span>Design Unit List</span></a></li>
|
| 17 |
|
|
<li class="current"><a href="files.html"><span>Files</span></a></li>
|
| 18 |
|
|
</ul>
|
| 19 |
|
|
</div>
|
| 20 |
|
|
<div class="tabs2">
|
| 21 |
|
|
<ul class="tablist">
|
| 22 |
|
|
<li><a href="files.html"><span>File List</span></a></li>
|
| 23 |
|
|
<li><a href="globals.html"><span>File Members</span></a></li>
|
| 24 |
|
|
</ul>
|
| 25 |
|
|
</div>
|
| 26 |
|
|
<div class="header">
|
| 27 |
|
|
<div class="headertitle">
|
| 28 |
|
|
<h1>ao68000.v</h1> </div>
|
| 29 |
|
|
</div>
|
| 30 |
|
|
<div class="contents">
|
| 31 |
|
|
<a href="ao68000_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">/* </span>
|
| 32 |
|
|
<a name="l00002"></a>00002 <span class="keyword"> Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.</span>
|
| 33 |
|
|
<a name="l00003"></a>00003 <span class="keyword"> </span>
|
| 34 |
|
|
<a name="l00004"></a>00004 <span class="keyword"> Redistribution and use in source and binary forms, with or without modification, are</span>
|
| 35 |
|
|
<a name="l00005"></a>00005 <span class="keyword"> permitted provided that the following conditions are met:</span>
|
| 36 |
|
|
<a name="l00006"></a>00006 <span class="keyword"> </span>
|
| 37 |
|
|
<a name="l00007"></a>00007 <span class="keyword"> 1. Redistributions of source code must retain the above copyright notice, this list of</span>
|
| 38 |
|
|
<a name="l00008"></a>00008 <span class="keyword"> conditions and the following disclaimer.</span>
|
| 39 |
|
|
<a name="l00009"></a>00009 <span class="keyword"> </span>
|
| 40 |
|
|
<a name="l00010"></a>00010 <span class="keyword"> 2. Redistributions in binary form must reproduce the above copyright notice, this list</span>
|
| 41 |
|
|
<a name="l00011"></a>00011 <span class="keyword"> of conditions and the following disclaimer in the documentation and/or other materials</span>
|
| 42 |
|
|
<a name="l00012"></a>00012 <span class="keyword"> provided with the distribution.</span>
|
| 43 |
|
|
<a name="l00013"></a>00013 <span class="keyword"> </span>
|
| 44 |
|
|
<a name="l00014"></a>00014 <span class="keyword"> THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED</span>
|
| 45 |
|
|
<a name="l00015"></a>00015 <span class="keyword"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND</span>
|
| 46 |
|
|
<a name="l00016"></a>00016 <span class="keyword"> FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR</span>
|
| 47 |
|
|
<a name="l00017"></a>00017 <span class="keyword"> CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span>
|
| 48 |
|
|
<a name="l00018"></a>00018 <span class="keyword"> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
|
| 49 |
|
|
<a name="l00019"></a>00019 <span class="keyword"> SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span>
|
| 50 |
|
|
<a name="l00020"></a>00020 <span class="keyword"> ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
|
| 51 |
|
|
<a name="l00021"></a>00021 <span class="keyword"> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF</span>
|
| 52 |
|
|
<a name="l00022"></a>00022 <span class="keyword"> ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
|
| 53 |
|
|
<a name="l00023"></a>00023 <span class="keyword"> */</span>
|
| 54 |
|
|
<a name="l00024"></a>00024
|
| 55 |
|
|
<a name="l00025"></a>00025
|
| 56 |
|
|
<a name="l00028"></a>00028
|
| 57 |
|
|
<a name="l00029"></a>00029 <span class="keyword">/***********************************************************************************************************************</span>
|
| 58 |
|
|
<a name="l00030"></a>00030 <span class="keyword"> Definitions of microcode operations - parsed by ao68000_tool to generate the defines in the section below</span>
|
| 59 |
|
|
<a name="l00031"></a>00031 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 60 |
|
|
<a name="l00032"></a>00032 <span class="keyword">// OPERATIONS START</span>
|
| 61 |
|
|
<a name="l00033"></a><a class="code" href="ao68000_8v.html#abae31742ff59754c5cae379a8326620a">00033</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af70dbd85a39263f4155eb79ad9c4144b">EA_REG_IDLE</a> <span class="vhdllogic">3'd0</span>
|
| 62 |
|
|
<a name="l00034"></a><a class="code" href="ao68000_8v.html#a3efa9ceb254bdf57b20bb7889d1d9d85">00034</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab608c5385657295b902b8ffc21c43d03">EA_REG_IR_2_0</a> <span class="vhdllogic">3'd1</span>
|
| 63 |
|
|
<a name="l00035"></a><a class="code" href="ao68000_8v.html#a1fb94867e22aea24310bc9c7364151ff">00035</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a56f29ecaaf69843219c88d8e0f252048">EA_REG_IR_11_9</a> <span class="vhdllogic">3'd2</span>
|
| 64 |
|
|
<a name="l00036"></a><a class="code" href="ao68000_8v.html#a6f85cbc7214132e6211b1b55130be1e8">00036</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af2b8ce7c793c79dee8394ad309a1ef71">EA_REG_MOVEM_REG_2_0</a> <span class="vhdllogic">3'd3</span>
|
| 65 |
|
|
<a name="l00037"></a><a class="code" href="ao68000_8v.html#ad564d7eda943ec9dc8aec71df47ab335">00037</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa5ef414e1c0f769a38cdd8b3aeef5184">EA_REG_3b111</a> <span class="vhdllogic">3'd4</span>
|
| 66 |
|
|
<a name="l00038"></a><a class="code" href="ao68000_8v.html#a3583aff884766bee4adde2b33cdb78a1">00038</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab4936576a8613273a6487d2b78812c55">EA_REG_3b100</a> <span class="vhdllogic">3'd5</span>
|
| 67 |
|
|
<a name="l00039"></a>00039
|
| 68 |
|
|
<a name="l00040"></a><a class="code" href="ao68000_8v.html#abec810f79440caf330d07ac85496726f">00040</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a59614fe274af03b21220e0f4aabee329">EA_MOD_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 69 |
|
|
<a name="l00041"></a><a class="code" href="ao68000_8v.html#a8a4633818c1ff779c277b26794ea6ae5">00041</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0c094175d5b6718611708b08af5e6342">EA_MOD_IR_5_3</a> <span class="vhdllogic">4'd1</span>
|
| 70 |
|
|
<a name="l00042"></a><a class="code" href="ao68000_8v.html#a038c3260f9da9154b330ce04665698cd">00042</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a45b520ba3dd813510ddca0ebe0a652f4">EA_MOD_MOVEM_MOD_5_3</a> <span class="vhdllogic">4'd2</span>
|
| 71 |
|
|
<a name="l00043"></a><a class="code" href="ao68000_8v.html#a1b98562dc7f9f79616c74ea9fe4a7e89">00043</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a46d304e545e3f136f9bc7fe83ffe61df">EA_MOD_IR_8_6</a> <span class="vhdllogic">4'd3</span>
|
| 72 |
|
|
<a name="l00044"></a><a class="code" href="ao68000_8v.html#a49add3beaff2163883cddc5cabf5a7d3">00044</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2e15ad20aa0f28ef9042982260a21316">EA_MOD_PREDEC</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// predecrement: -(An)</span>
|
| 73 |
|
|
<a name="l00045"></a><a class="code" href="ao68000_8v.html#a9de88008e1324d704d69c3e152bca40b">00045</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae4ecbd320f11539d132c8e6aa3fdcb5c">EA_MOD_3b111</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// extended mod</span>
|
| 74 |
|
|
<a name="l00046"></a><a class="code" href="ao68000_8v.html#a0a8e98b1f5984d32748629351a56292a">00046</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aee18d2c3a30bdec23a7de0889deb0d94">EA_MOD_DN_PREDEC</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// MOD.DN_PREDEC: Dn 3'b000 (ir[3] == 1'b0), -(An) 3'b100 (ir[3] == 1'b1)</span>
|
| 75 |
|
|
<a name="l00047"></a><a class="code" href="ao68000_8v.html#a8361e5c9c5e67bd645f81cd60bd147ad">00047</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac190b9646213ddb87ec06a5858d479b3">EA_MOD_DN_AN_EXG</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// MOD.DN_AN_EXG: Dn 3'b000 (ir[7:3] == 5'b01000 or 5'b10001), An 3'b001 (ir[7:3] == 5'b01001)</span>
|
| 76 |
|
|
<a name="l00048"></a><a class="code" href="ao68000_8v.html#a0fa6f8cdf59eca8135017fa536a37bb9">00048</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a51a36024571aca1d7d7c7fa928956589">EA_MOD_POSTINC</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// MOD.POSTINC: postincrement (An)+ 3'b011</span>
|
| 77 |
|
|
<a name="l00049"></a><a class="code" href="ao68000_8v.html#af51a4ebf83f285bd72bfa635916f7a31">00049</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a7a6ccf87a21e66605e4672e95a6578e4">EA_MOD_AN</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// MOD.AN: An 3'b001, saved result is sign-extended</span>
|
| 78 |
|
|
<a name="l00050"></a><a class="code" href="ao68000_8v.html#a1f9d91cd3804c31adfff0a203d4482ad">00050</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8a000a242ea6cc51ac97ec35753faf7b">EA_MOD_DN</a> <span class="vhdllogic">4'd10</span> <span class="keyword">// MOD.DN: Dn 3'b000</span>
|
| 79 |
|
|
<a name="l00051"></a><a class="code" href="ao68000_8v.html#a743b7cf5f69a2a4c76ebd17517afa21a">00051</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a88ded717145b6f89a3cd3416577225f0">EA_MOD_INDIRECTOFFSET</a> <span class="vhdllogic">4'd11</span> <span class="keyword">// MOD.INDIRECTOFFSET: (d16, An) 3'b101</span>
|
| 80 |
|
|
<a name="l00052"></a>00052
|
| 81 |
|
|
<a name="l00053"></a><a class="code" href="ao68000_8v.html#a079f5d082417be2ce9b66e2b8d37790d">00053</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a30b69aee8fb5af4ab38fc9f0d92a28d3">EA_TYPE_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 82 |
|
|
<a name="l00054"></a><a class="code" href="ao68000_8v.html#a98ad62929618c4fced8b123598b14972">00054</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">EA_TYPE_ALL</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// TYPE.ALL: all</span>
|
| 83 |
|
|
<a name="l00055"></a><a class="code" href="ao68000_8v.html#a1d947d3a176585d3397b013493106a8d">00055</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">EA_TYPE_CONTROL_POSTINC</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// TYPE.CONTROL_POSTINC: control or postincrement</span>
|
| 84 |
|
|
<a name="l00056"></a><a class="code" href="ao68000_8v.html#a3f020325cf111cdc0ccf8cdc30ab0508">00056</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">EA_TYPE_CONTROLALTER_PREDEC</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// TYPE.CONTROLALTER_PREDEC: control alter or predecrement</span>
|
| 85 |
|
|
<a name="l00057"></a><a class="code" href="ao68000_8v.html#a03b0950ea83f966e56258a9532601135">00057</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">EA_TYPE_CONTROL</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// TYPE.CONTROL: control</span>
|
| 86 |
|
|
<a name="l00058"></a><a class="code" href="ao68000_8v.html#a820799c8bb1a83ef02e3995f9ee5efe7">00058</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">EA_TYPE_DATAALTER</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// TYPE.DATAALTER: data alter</span>
|
| 87 |
|
|
<a name="l00059"></a><a class="code" href="ao68000_8v.html#a65ea75348e3f757f701f7018e6ff938b">00059</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">EA_TYPE_DN_AN</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// TYPE.DN_AN: Dn, An</span>
|
| 88 |
|
|
<a name="l00060"></a><a class="code" href="ao68000_8v.html#a214dbf835e0d0ee454f95e110352d5e7">00060</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">EA_TYPE_MEMORYALTER</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// TYPE.MEMORYALTER: memory alter</span>
|
| 89 |
|
|
<a name="l00061"></a><a class="code" href="ao68000_8v.html#a4e9d7d8a1f16ab9f3e0ddbe21b5eb20f">00061</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">EA_TYPE_DATA</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// TYPE.DATA: data</span>
|
| 90 |
|
|
<a name="l00062"></a>00062
|
| 91 |
|
|
<a name="l00063"></a><a class="code" href="ao68000_8v.html#aa1547162afaa2d5d8b4f4e204b0854b0">00063</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ad7005d0bbe62ff9fad837f5a1ae6ef6b">OP1_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 92 |
|
|
<a name="l00064"></a><a class="code" href="ao68000_8v.html#aebf8d67a21a657f92acd1a43cf10879d">00064</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a29e287eda5813f253f9f1cd527021533">OP1_FROM_OP2</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// move from operand2</span>
|
| 93 |
|
|
<a name="l00065"></a><a class="code" href="ao68000_8v.html#ae8151e119a198fa34a58db33e06d554c">00065</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab601cf0d52e5fe6ae155ab8084b236e1">OP1_FROM_ADDRESS</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// move from address</span>
|
| 94 |
|
|
<a name="l00066"></a><a class="code" href="ao68000_8v.html#a02f7dfa31e10014b5e4da47123aad300">00066</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aec7f41507eab6c659f5d544c942b441e">OP1_FROM_DATA</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// move from data, sign extend</span>
|
| 95 |
|
|
<a name="l00067"></a><a class="code" href="ao68000_8v.html#a397791cb02941c8cb7390bfb441054ba">00067</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#abc0874c9141535c9c6a071653810c8fc">OP1_FROM_IMMEDIATE</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// move immediate, sign extend</span>
|
| 96 |
|
|
<a name="l00068"></a><a class="code" href="ao68000_8v.html#a3526a210d9ceb1c99e0855617ec1d95d">00068</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2adbf20e4776f4f5449563560fcfea3e">OP1_FROM_RESULT</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// move from result</span>
|
| 97 |
|
|
<a name="l00069"></a><a class="code" href="ao68000_8v.html#a40014be6eacd344d8d9ddc62c0d731f5">00069</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac2bd7be96e464a7a06affeb71024f266">OP1_MOVEQ</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// move moveq: { 24{ir[7]}, ir[7:0] }</span>
|
| 98 |
|
|
<a name="l00070"></a><a class="code" href="ao68000_8v.html#a16ecbce30b6efc118fc70f6b08d2f2f1">00070</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aade66d4090f1aea9ed568a4e17ff1eae">OP1_FROM_PC</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// move from PC</span>
|
| 99 |
|
|
<a name="l00071"></a><a class="code" href="ao68000_8v.html#af4bc964b37615c6c9d6cce1dd78da980">00071</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4db6f8d952dd7d7cfffeb0de4ad4a08b">OP1_LOAD_ZEROS</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// load zeros: 32'b0</span>
|
| 100 |
|
|
<a name="l00072"></a><a class="code" href="ao68000_8v.html#a47278169c2b4d96bd0757d0ab42c4e3f">00072</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae8489ec12e458975d614347191ba2004">OP1_LOAD_ONES</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// load ones: 32'hFFFFFFFF</span>
|
| 101 |
|
|
<a name="l00073"></a><a class="code" href="ao68000_8v.html#a0ad92995fd292dddd4b906d5cb08ddbc">00073</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9e1d49d77f5b144fff6cc8c0c021e5d2">OP1_FROM_SR</a> <span class="vhdllogic">4'd10</span> <span class="keyword">// move from SR</span>
|
| 102 |
|
|
<a name="l00074"></a><a class="code" href="ao68000_8v.html#ac7544eda832f9d9eee0545bac86f2f9d">00074</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1a44c33265ec779ad10e437621cda43b">OP1_FROM_USP</a> <span class="vhdllogic">4'd11</span> <span class="keyword">// move from USP</span>
|
| 103 |
|
|
<a name="l00075"></a><a class="code" href="ao68000_8v.html#a39cb7a5d93e2b993e2fb086670b800d0">00075</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4900ac90de9fd53eaeb1acddf51a9008">OP1_FROM_AN</a> <span class="vhdllogic">4'd12</span> <span class="keyword">// move from An, 32 bits</span>
|
| 104 |
|
|
<a name="l00076"></a><a class="code" href="ao68000_8v.html#a4454a54d475ca2a44c73f05bfdd193fa">00076</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3aa722db3503e9370be36b3d409f3e17">OP1_FROM_DN</a> <span class="vhdllogic">4'd13</span> <span class="keyword">// move from Dn, sign extend</span>
|
| 105 |
|
|
<a name="l00077"></a><a class="code" href="ao68000_8v.html#ab8202afb6909378e40231779e276a99c">00077</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a083db35259f035ab10f606d2c7dd82c6">OP1_FROM_IR</a> <span class="vhdllogic">4'd14</span> <span class="keyword">// move from ir[15:0]</span>
|
| 106 |
|
|
<a name="l00078"></a><a class="code" href="ao68000_8v.html#aff71bb71e12f46d60beacfd59c9e0131">00078</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a707f0ca7fa1a08446ba113ede9d5d8a4">OP1_FROM_FAULT_ADDRESS</a> <span class="vhdllogic">4'd15</span> <span class="keyword">// move from fault_address</span>
|
| 107 |
|
|
<a name="l00079"></a>00079
|
| 108 |
|
|
<a name="l00080"></a><a class="code" href="ao68000_8v.html#a6e7e6957190ba51c010b10628e61781c">00080</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4b4bbc9cf744c33746a1c2b2d6e6c8f6">OP2_IDLE</a> <span class="vhdllogic">3'd0</span>
|
| 109 |
|
|
<a name="l00081"></a><a class="code" href="ao68000_8v.html#a03ca343d05447b065220a980db5e2a5f">00081</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a092ca695ecfa2de9e4d4a27bbd89d40f">OP2_FROM_OP1</a> <span class="vhdllogic">3'd1</span> <span class="keyword">// move from operand1</span>
|
| 110 |
|
|
<a name="l00082"></a><a class="code" href="ao68000_8v.html#a5d285b9e30573f05d50aaec27da8e374">00082</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5c2c8ed577b6ab91a5ae3861643575e7">OP2_LOAD_1</a> <span class="vhdllogic">3'd2</span> <span class="keyword">// load: 32'b1</span>
|
| 111 |
|
|
<a name="l00083"></a><a class="code" href="ao68000_8v.html#a24418acaa3ce529bc88ab23c5074f866">00083</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a7c904b70c2347aaee330105f74a69fc1">OP2_LOAD_COUNT</a> <span class="vhdllogic">3'd3</span> <span class="keyword">// load count</span>
|
| 112 |
|
|
<a name="l00084"></a><a class="code" href="ao68000_8v.html#a5d0ef90efe00620583145237d48dcaaf">00084</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aacec01f4da467eb6785c611710c1219d">OP2_ADDQ_SUBQ</a> <span class="vhdllogic">3'd4</span> <span class="keyword">// load addq_subq</span>
|
| 113 |
|
|
<a name="l00085"></a><a class="code" href="ao68000_8v.html#a3b60c6832e1d7f8a79333123b958ae3e">00085</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ad8cdca7f0cbac16e09b4e1a1e3ab4f11">OP2_MOVE_OFFSET</a> <span class="vhdllogic">3'd5</span> <span class="keyword">// move offset</span>
|
| 114 |
|
|
<a name="l00086"></a><a class="code" href="ao68000_8v.html#ae4deaa79b3e48335d86b3170b5cdbd0d">00086</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a041be53a35bc1a415713d34c839c81c5">OP2_MOVE_ADDRESS_BUS_INFO</a> <span class="vhdllogic">3'd6</span> <span class="keyword">// move address_bus_info</span>
|
| 115 |
|
|
<a name="l00087"></a><a class="code" href="ao68000_8v.html#afb9ecb75d2b2a62dc848b1a03b95428f">00087</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a81d303d3fcf43bd2ed3b99072571f816">OP2_DECR_BY_1</a> <span class="vhdllogic">3'd7</span> <span class="keyword">// decrement by 1</span>
|
| 116 |
|
|
<a name="l00088"></a>00088
|
| 117 |
|
|
<a name="l00089"></a><a class="code" href="ao68000_8v.html#af7e83494cf885e6115824c1fc7725fa2">00089</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3f7506465d358bddd4692916e422237d">ADDRESS_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 118 |
|
|
<a name="l00090"></a><a class="code" href="ao68000_8v.html#ab421ad02e89cca481d403101a57cef57">00090</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a864e0b06304816dec2d4658503d97495">ADDRESS_INCR_BY_SIZE</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// increment by size</span>
|
| 119 |
|
|
<a name="l00091"></a><a class="code" href="ao68000_8v.html#a12d456f00683eb526f0a8c5708908c24">00091</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa479827c57933eb9ff03788bbe9d6e3a">ADDRESS_DECR_BY_SIZE</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// decrement by size</span>
|
| 120 |
|
|
<a name="l00092"></a><a class="code" href="ao68000_8v.html#aed439cba8d3261fe5d83b2dd4d59b48a">00092</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac4044068e496c3393c6336b72873a958">ADDRESS_INCR_BY_2</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// increment by 2</span>
|
| 121 |
|
|
<a name="l00093"></a><a class="code" href="ao68000_8v.html#aea482fb7d6660d30f33ae8051e240c96">00093</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#afc15ad5da6b4afd71eb879476c603fe3">ADDRESS_FROM_AN_OUTPUT</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// move from An output</span>
|
| 122 |
|
|
<a name="l00094"></a><a class="code" href="ao68000_8v.html#ad0fca2b15d909d42f7614c899a0764ff">00094</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac1143ff5a059fc5609c9419fcd402ae1">ADDRESS_FROM_BASE_INDEX_OFFSET</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// move from base+index+offset</span>
|
| 123 |
|
|
<a name="l00095"></a><a class="code" href="ao68000_8v.html#ad9ac4e6d105a7cbb5479faf529ae00a7">00095</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa6ba908e680fe87e46ac1cf014eed463">ADDRESS_FROM_IMM_16</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// move from {16{ir1[15]}, ir1[15:0]}</span>
|
| 124 |
|
|
<a name="l00096"></a><a class="code" href="ao68000_8v.html#ab55c9e9c151605863a8563e8e9a438e6">00096</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa688332c940cad3a10561a5c9f74698a">ADDRESS_FROM_IMM_32</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// move from {ir1[15:0], ir2[15:0]}</span>
|
| 125 |
|
|
<a name="l00097"></a><a class="code" href="ao68000_8v.html#a170ee7ff137ea34a1d1885ba86e332ba">00097</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">ADDRESS_FROM_PC_INDEX_OFFSET</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// move from pc+index+offset</span>
|
| 126 |
|
|
<a name="l00098"></a><a class="code" href="ao68000_8v.html#a976e0837935917b54a3f575786283804">00098</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2a30a0ecfa48e96cc5be837e7db71cab">ADDRESS_FROM_TRAP</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// move trap {22'b0, trap[7:0], 2'b0}</span>
|
| 127 |
|
|
<a name="l00099"></a>00099
|
| 128 |
|
|
<a name="l00100"></a><a class="code" href="ao68000_8v.html#a6b7b916e46f4e826e397f24c7e6cd5f1">00100</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a85698146140d774ffe2b54e5be255726">SIZE_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 129 |
15 |
alfik |
<a name="l00101"></a><a class="code" href="ao68000_8v.html#a80529f3bcf69bd83cb12853628e45dde">00101</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">SIZE_BYTE</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// load byte: 3'b001</span>
|
| 130 |
|
|
<a name="l00102"></a><a class="code" href="ao68000_8v.html#aa31da57c5af273923c08b1c95ff91fa6">00102</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9da3fa515a6d6e5949573714c5682999">SIZE_WORD</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// load word: 3'b010</span>
|
| 131 |
|
|
<a name="l00103"></a><a class="code" href="ao68000_8v.html#a9f8b67ce84f0ac105c8c92764b32ee2d">00103</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae54bb350f5d3a019211af2a214f46273">SIZE_LONG</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// load long: 3'b100</span>
|
| 132 |
12 |
alfik |
<a name="l00104"></a><a class="code" href="ao68000_8v.html#ab2a1ed498771dd52791361f258607630">00104</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">SIZE_1</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// SIZE.1: word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 )</span>
|
| 133 |
|
|
<a name="l00105"></a><a class="code" href="ao68000_8v.html#a5118e28f30c7e8403bed7875aeb8f902">00105</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">SIZE_1_PLUS</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// SIZE.1+: word ( ir[7:6] == 2'b10 ), long ( ir[7:6] == 2'b11 )</span>
|
| 134 |
|
|
<a name="l00106"></a><a class="code" href="ao68000_8v.html#ac10136ab62631671a5e7ba54240bad1b">00106</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">SIZE_2</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// SIZE.2: word ( ir[6] == 1'b0 ), long ( ir[6] == 1'b1 )</span>
|
| 135 |
|
|
<a name="l00107"></a><a class="code" href="ao68000_8v.html#a5e687ed60160bb8241204154edf8bdb9">00107</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">SIZE_3</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// SIZE.3: byte ( ir[7:6] == 2'b00 ), word ( ir[7:6] == 2'b01 ), long ( ir[7:6] == 2'b10 )</span>
|
| 136 |
|
|
<a name="l00108"></a><a class="code" href="ao68000_8v.html#a3ec9affe31dd35c8d683099f07f57f8b">00108</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">SIZE_4</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// SIZE.4: byte ( ir[13:12] == 2'b01 ), word( ir[13:12] == 2'b11 ), long ( ir[13:12] == 2'b10 )</span>
|
| 137 |
|
|
<a name="l00109"></a><a class="code" href="ao68000_8v.html#a72b1bf10a1ddfbec8ef86fa9b54d1fc7">00109</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">SIZE_5</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// SIZE.5: word ( ir[8] == 1'b0 ), long ( ir[8] == 1'b1 )</span>
|
| 138 |
|
|
<a name="l00110"></a><a class="code" href="ao68000_8v.html#aed12a5061f70d4a4e9710145a5a25e00">00110</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">SIZE_6</a> <span class="vhdllogic">4'd10</span> <span class="keyword">// SIZE.6: byte ( ir[5:3] != 3'b000 ), long ( ir[5:3] == 3'b000 )</span>
|
| 139 |
|
|
<a name="l00111"></a>00111
|
| 140 |
|
|
<a name="l00112"></a><a class="code" href="ao68000_8v.html#ad9661d840acc60943ce787ae9dc5ecb4">00112</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a7161c92592ac4af6d07bc988a542eb89">MOVEM_MODREG_IDLE</a> <span class="vhdllogic">3'd0</span>
|
| 141 |
|
|
<a name="l00113"></a><a class="code" href="ao68000_8v.html#acd1bf5ea8cad474f54d0e2b78b7dd251">00113</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a59e6a074af6fbcf3490ecdb2d277e452">MOVEM_MODREG_LOAD_0</a> <span class="vhdllogic">3'd1</span> <span class="keyword">// load 6'b0</span>
|
| 142 |
|
|
<a name="l00114"></a><a class="code" href="ao68000_8v.html#a607cc3361b5ebfeaa5aff2bc85c256e2">00114</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a96857bc6f8514765cf6add0567891646">MOVEM_MODREG_LOAD_6b001111</a> <span class="vhdllogic">3'd2</span> <span class="keyword">// load 6'b001111</span>
|
| 143 |
|
|
<a name="l00115"></a><a class="code" href="ao68000_8v.html#a33dd6f67011d4a1b63599e32c31a7cfa">00115</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab865a06c214356bb8906149ad6beebf2">MOVEM_MODREG_INCR_BY_1</a> <span class="vhdllogic">3'd3</span> <span class="keyword">// increment by 1</span>
|
| 144 |
|
|
<a name="l00116"></a><a class="code" href="ao68000_8v.html#ab4e3e29bdf64a78ec71c92dfd75f6f59">00116</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#afc15f893a792d1af5e5c90f8ed788662">MOVEM_MODREG_DECR_BY_1</a> <span class="vhdllogic">3'd4</span> <span class="keyword">// decrement by 1</span>
|
| 145 |
|
|
<a name="l00117"></a>00117
|
| 146 |
|
|
<a name="l00118"></a><a class="code" href="ao68000_8v.html#a385a47ea219d80dce0e2186c9f01fca6">00118</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aac70873800ce60db62fcd45ba16f3ce7">MOVEM_LOOP_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 147 |
|
|
<a name="l00119"></a><a class="code" href="ao68000_8v.html#abc3f14b58079b96ec275ccd42c03a097">00119</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8465e4a24e72c1cb6e12015c4ff806c5">MOVEM_LOOP_LOAD_0</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// load 4'b0</span>
|
| 148 |
|
|
<a name="l00120"></a><a class="code" href="ao68000_8v.html#accd753c037653608148ded38d5f3240d">00120</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#add999e8b65307d6d46547d776999f215">MOVEM_LOOP_INCR_BY_1</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// increment by 1</span>
|
| 149 |
|
|
<a name="l00121"></a>00121
|
| 150 |
|
|
<a name="l00122"></a><a class="code" href="ao68000_8v.html#ae4b2d15139d04a8ec077587d69c81acf">00122</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac8b73e6443257517edb5d46c7bb98b41">MOVEM_REG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 151 |
|
|
<a name="l00123"></a><a class="code" href="ao68000_8v.html#a3a69b37d46c72264b15f867dfc8f9259">00123</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa7d78c26e9e37f761c7a0b178fe13cf8">MOVEM_REG_FROM_OP1</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// load from operand1[15:0]</span>
|
| 152 |
|
|
<a name="l00124"></a><a class="code" href="ao68000_8v.html#a70b9341e13ea7ac94a14d545a8a93bee">00124</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac34150d75e16d155befcfcb8a95e45a3">MOVEM_REG_SHIFT_RIGHT</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// shift right</span>
|
| 153 |
|
|
<a name="l00125"></a>00125
|
| 154 |
|
|
<a name="l00126"></a><a class="code" href="ao68000_8v.html#ad13843ba8d23f96318f6a5bf29de192c">00126</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a72dbbf2f944b4b355076763c467eb1d6">IR_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 155 |
|
|
<a name="l00127"></a><a class="code" href="ao68000_8v.html#a4b8ea3a5f3960c1b1f93705d158656b8">00127</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a987216cfc97019736d0251dcd5470e68">IR_LOAD_WHEN_PREFETCH_VALID</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// load from prefetch_ir[79:64]</span>
|
| 156 |
|
|
<a name="l00128"></a>00128
|
| 157 |
|
|
<a name="l00129"></a><a class="code" href="ao68000_8v.html#a29d5eaf4cf16d6a429a95c6537a615ac">00129</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#abc0b06b8aa080c37acb52c035ec53cc6">PC_IDLE</a> <span class="vhdllogic">3'd0</span>
|
| 158 |
|
|
<a name="l00130"></a><a class="code" href="ao68000_8v.html#a3597453c83a6a1641470f65d8b4ec404">00130</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a63d3becb9e2a770cfd9df4a70298c30a">PC_FROM_RESULT</a> <span class="vhdllogic">3'd1</span> <span class="keyword">// move from result</span>
|
| 159 |
|
|
<a name="l00131"></a><a class="code" href="ao68000_8v.html#aca2504aa7b43efbd7b19e91f5b31706e">00131</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a023942fcdb1eb88002847e9730cf62c2">PC_INCR_BY_2</a> <span class="vhdllogic">3'd2</span> <span class="keyword">// increment by 2</span>
|
| 160 |
|
|
<a name="l00132"></a><a class="code" href="ao68000_8v.html#a6a2fde91ff2ec347bc678a50f2890656">00132</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6b8aff09ca5bd77e19e6d7a5076a58bd">PC_INCR_BY_4</a> <span class="vhdllogic">3'd3</span> <span class="keyword">// increment by 4</span>
|
| 161 |
13 |
alfik |
<a name="l00133"></a><a class="code" href="ao68000_8v.html#a82eee4a847e1a2819bacf5bd94295681">00133</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aefc526541d0911ae626689caead407ab">PC_INCR_BY_SIZE</a> <span class="vhdllogic">3'd4</span> <span class="keyword">// increment by size: 2 (size == 3'b001 || size == 3'b010), 4 (size == 3'b100)</span>
|
| 162 |
12 |
alfik |
<a name="l00134"></a><a class="code" href="ao68000_8v.html#a55731d0cae54f7992cd84f690b472f3b">00134</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a48c2827ab160beae0aab354b09b59e1a">PC_FROM_PREFETCH_IR</a> <span class="vhdllogic">3'd5</span> <span class="keyword">// move from prefetch_ir</span>
|
| 163 |
|
|
<a name="l00135"></a><a class="code" href="ao68000_8v.html#a7ea056a3858070e63182c2b870d30db6">00135</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6f1c276d75adca2b0290b7936476fde8">PC_INCR_BY_2_IN_MAIN_LOOP</a> <span class="vhdllogic">3'd6</span> <span class="keyword">// increment by 2, in main loop, when valid prefetch and valid instruction</span>
|
| 164 |
|
|
<a name="l00136"></a>00136
|
| 165 |
|
|
<a name="l00137"></a><a class="code" href="ao68000_8v.html#af1f815598887f16e2959dd1a9452d009">00137</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4147921254003739e353b2a48d39b592">TRAP_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 166 |
|
|
<a name="l00138"></a><a class="code" href="ao68000_8v.html#abdfcbec17451d64285a3458a77171565">00138</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4267c71337dc6963db47aba754396f48">TRAP_ILLEGAL_INSTR</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// move illegal_instr: 8'd4</span>
|
| 167 |
|
|
<a name="l00139"></a><a class="code" href="ao68000_8v.html#aa0305e0170a90ab6a0e20754d8598500">00139</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a111476f2c18a4085c9a5cea3692dc990">TRAP_DIV_BY_ZERO</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// move divide_by_zero: 8'd5</span>
|
| 168 |
|
|
<a name="l00140"></a><a class="code" href="ao68000_8v.html#adacfa6ab393eab920ec127cc7cabc869">00140</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a7d97a1e77166d92c1d69452c3e836682">TRAP_CHK</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// move chk: 8'd6</span>
|
| 169 |
|
|
<a name="l00141"></a><a class="code" href="ao68000_8v.html#ae5af1d8f2d78838c3b7be0fd669026f8">00141</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a66a7d33a63851daa49e101494acd6118">TRAP_TRAPV</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// move trapv: 8'd7</span>
|
| 170 |
|
|
<a name="l00142"></a><a class="code" href="ao68000_8v.html#af317b5cab94a31093e52dd207f4e3538">00142</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a940b41a2a1e4c585e15f1c2bef5d5c6f">TRAP_PRIVIL_VIOLAT</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// move priv_viol: 8'd8</span>
|
| 171 |
|
|
<a name="l00143"></a><a class="code" href="ao68000_8v.html#a012324f78d35a882d2284708e0c72e46">00143</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a84705ced93a01047ec829b7ea942cee0">TRAP_TRACE</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// move trace: 8'd9</span>
|
| 172 |
|
|
<a name="l00144"></a><a class="code" href="ao68000_8v.html#a7fea9f37f942a9a2dc77f3d3b8a3571a">00144</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4d09227bd9de91efc1a40bf676e10c72">TRAP_TRAP</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// move trap: { 3'b0, 1'b1, ir[3:0] }</span>
|
| 173 |
|
|
<a name="l00145"></a><a class="code" href="ao68000_8v.html#ad05ac9ae0137b57eb3054f106ca32193">00145</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8d6c015903e3a60339a6e8cc196bb440">TRAP_FROM_DECODER</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// move from decoder_trap</span>
|
| 174 |
|
|
<a name="l00146"></a><a class="code" href="ao68000_8v.html#aa60e455881e6ae49d7c84a5fc9e0ac00">00146</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a57812c3cf3905152a60361ae979a4c2d">TRAP_FROM_INTERRUPT</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// move from interrupt_trap</span>
|
| 175 |
|
|
<a name="l00147"></a>00147
|
| 176 |
|
|
<a name="l00148"></a><a class="code" href="ao68000_8v.html#a0ce45ad3e0febf9927ae532d15fd3f11">00148</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a83d70c41e3ac228b147e691dd852b361">OFFSET_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 177 |
|
|
<a name="l00149"></a><a class="code" href="ao68000_8v.html#a782129309f5bf455d756e993dcdf170d">00149</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ad904ffb95a59f475e446877344adb415">OFFSET_IMM_8</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// { 24{ir1[7]}, ir1[7:0] }</span>
|
| 178 |
|
|
<a name="l00150"></a><a class="code" href="ao68000_8v.html#a49b8d7c9ad6b05f60e3e8fc61ff8c0b9">00150</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a87c5da2d7633077683260709d88602e0">OFFSET_IMM_16</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// { 16{ir1[15]}, ir1[15:0] }</span>
|
| 179 |
|
|
<a name="l00151"></a>00151
|
| 180 |
|
|
<a name="l00152"></a><a class="code" href="ao68000_8v.html#a178f30ad25f9dff1494dfb4b5f45ff12">00152</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a353afe052d566e31fc27a217e346caeb">INDEX_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 181 |
|
|
<a name="l00153"></a><a class="code" href="ao68000_8v.html#a9b0b9a5546694d2d2b66e9c80b16e064">00153</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1db54bd70d82cea2a77c6d5c823f04db">INDEX_0</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// 32'b0</span>
|
| 182 |
|
|
<a name="l00154"></a><a class="code" href="ao68000_8v.html#a02facfea9d3e4e1d1aa2bc753e3b96ff">00154</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af05405b84ee28262882d3c7ac7a5a80c">INDEX_LOAD_EXTENDED</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// load from extended instruction word</span>
|
| 183 |
|
|
<a name="l00155"></a>00155
|
| 184 |
|
|
<a name="l00156"></a><a class="code" href="ao68000_8v.html#a571de9975654a97d97bd6df0ef5627e1">00156</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af48fa0ca0e425be1cc6520c443a68df8">STOP_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 185 |
|
|
<a name="l00157"></a><a class="code" href="ao68000_8v.html#ac7283fe46fb28e406b71fc1d9c871997">00157</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5131e7ee341cd6f2ea5350a89b19a488">STOP_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, continue when: trace,interrupt or reset</span>
|
| 186 |
|
|
<a name="l00158"></a><a class="code" href="ao68000_8v.html#a7d07d95625d67dbbbbb223b72760deb1">00158</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0e63684fc863d639423c2d9f0f8e6cd9">STOP_FLAG_CLEAR</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear</span>
|
| 187 |
|
|
<a name="l00159"></a>00159
|
| 188 |
|
|
<a name="l00160"></a><a class="code" href="ao68000_8v.html#a0bb87b29c7ce28cb55b874ba9594d041">00160</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a29d2f3912d2d6e99115b2a3fbc6b12e0">TRACE_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 189 |
|
|
<a name="l00161"></a><a class="code" href="ao68000_8v.html#a275d1ebae68442f0f5e603efcde61215">00161</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3cb5bcdd68537f527007213efe5c2d4f">TRACE_FLAG_COPY_WHEN_NO_STOP</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// remember trace bit, move from sr[15]</span>
|
| 190 |
|
|
<a name="l00162"></a>00162
|
| 191 |
|
|
<a name="l00163"></a><a class="code" href="ao68000_8v.html#a4d54b27132c5a6e6c164665060644c1c">00163</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3698c674b2af4c589be9288a945ed80c">GROUP_0_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 192 |
|
|
<a name="l00164"></a><a class="code" href="ao68000_8v.html#a0d9a9d22a9b57de610604c351c33f276">00164</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5333b31d43f3c7de70d3cad313720ef4">GROUP_0_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, processing group zero exception</span>
|
| 193 |
|
|
<a name="l00165"></a><a class="code" href="ao68000_8v.html#ae96871c70aa3eae5be04935bec3cc518">00165</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a28adb393ace594d548dfe7f070fd837b">GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear</span>
|
| 194 |
|
|
<a name="l00166"></a>00166
|
| 195 |
|
|
<a name="l00167"></a><a class="code" href="ao68000_8v.html#a245c5943c822609d08704a0616ded4e5">00167</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af01c1d6ee373c292d68833540daed30c">INSTRUCTION_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 196 |
|
|
<a name="l00168"></a><a class="code" href="ao68000_8v.html#acd8c6f17c7dc603c58cc57b5df590b9b">00168</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6882447365cc7940c16017ee13305875">INSTRUCTION_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, processing instruction</span>
|
| 197 |
|
|
<a name="l00169"></a><a class="code" href="ao68000_8v.html#af0bcba7401823dab2bb76a94778fb788">00169</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#adaf70d0e1aaa9fe89fc79971d67bc172">INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear, in main loop, when valid prefetch and valid instruction</span>
|
| 198 |
|
|
<a name="l00170"></a>00170
|
| 199 |
|
|
<a name="l00171"></a><a class="code" href="ao68000_8v.html#a75fc0f1773f61dd7898078ce4f39b2fc">00171</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a10b30bd6d46d39f598e7677487c2d0cb">READ_MODIFY_WRITE_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 200 |
|
|
<a name="l00172"></a><a class="code" href="ao68000_8v.html#a3d2e3e3bcbfb7fc57a0c4d8d11e89eab">00172</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2ba2dbb4697aa9a3559b775da0ade761">READ_MODIFY_WRITE_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, execute a RMW cycle</span>
|
| 201 |
|
|
<a name="l00173"></a><a class="code" href="ao68000_8v.html#a3eb266124ca9f95b9291011577a32bc8">00173</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ace5de6cd5ad33427e8efd5ec8191c297">READ_MODIFY_WRITE_FLAG_CLEAR</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear</span>
|
| 202 |
|
|
<a name="l00174"></a>00174
|
| 203 |
|
|
<a name="l00175"></a><a class="code" href="ao68000_8v.html#ac2fdc0768d391942724a5dbe12623935">00175</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab5502396519fe76ccdb1fcd5dd89d6db">DO_RESET_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 204 |
|
|
<a name="l00176"></a><a class="code" href="ao68000_8v.html#a2c976c137948e04adb8af28b7acc4cd5">00176</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a682472d63f131aa31c38abd6f2d577ab">DO_RESET_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, signal reset</span>
|
| 205 |
|
|
<a name="l00177"></a><a class="code" href="ao68000_8v.html#add4adcf29ef3a3476f653d76ee05ec9a">00177</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#afd7c962bcd95f3629d247e7790f9cf95">DO_RESET_FLAG_CLEAR</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear</span>
|
| 206 |
|
|
<a name="l00178"></a>00178
|
| 207 |
|
|
<a name="l00179"></a><a class="code" href="ao68000_8v.html#adfe8c1f8a1f75118dd98a76d80fbecfb">00179</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aca5ce5e76fad95242ff4b2e866d65ba3">DO_INTERRUPT_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 208 |
|
|
<a name="l00180"></a><a class="code" href="ao68000_8v.html#ac6a82717f334829ed6caf3dc9c49a305">00180</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#acc420165ae00aa63b4d40c220dc1ed79">DO_INTERRUPT_FLAG_SET_IF_ACTIVE</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set if interrupt active</span>
|
| 209 |
|
|
<a name="l00181"></a><a class="code" href="ao68000_8v.html#ab07c3644cd1fe30f4f2e11f9645b2f9d">00181</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#abe668eeea71491f898b31b9c66a4db96">DO_INTERRUPT_FLAG_CLEAR</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear</span>
|
| 210 |
|
|
<a name="l00182"></a>00182
|
| 211 |
|
|
<a name="l00183"></a><a class="code" href="ao68000_8v.html#a91286482784ede154a3f0ce46832a043">00183</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a596fe712a42f5a016dd874d93276a455">DO_READ_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 212 |
|
|
<a name="l00184"></a><a class="code" href="ao68000_8v.html#a9d50b2f7e7824a158133a58ddec32a59">00184</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a210a4746c070617bd4272cf091ce4977">DO_READ_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, perform read operation</span>
|
| 213 |
|
|
<a name="l00185"></a><a class="code" href="ao68000_8v.html#abdc4b801145aa75f4839c9083bedd054">00185</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3186ce27b4c9202d124c4bee6b07e2fd">DO_READ_FLAG_CLEAR</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear</span>
|
| 214 |
|
|
<a name="l00186"></a>00186
|
| 215 |
|
|
<a name="l00187"></a><a class="code" href="ao68000_8v.html#a26b38765090f24bf23e43ce1f5a4501f">00187</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aff0ed461ed992ebbcb0604d4ff38a30c">DO_WRITE_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 216 |
|
|
<a name="l00188"></a><a class="code" href="ao68000_8v.html#a59c6607a856694f1136b95e788261d87">00188</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a97fc325edc48a555daf24f1757c5e7bf">DO_WRITE_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, perform write operation</span>
|
| 217 |
|
|
<a name="l00189"></a><a class="code" href="ao68000_8v.html#ab4cf38a3c02ac7636031938829b83099">00189</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ad6f9aea669c0c0233f4155f29afc4d1d">DO_WRITE_FLAG_CLEAR</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// clear</span>
|
| 218 |
|
|
<a name="l00190"></a>00190
|
| 219 |
|
|
<a name="l00191"></a><a class="code" href="ao68000_8v.html#ac011f8ca6d9f609f43381e25a0f861e7">00191</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a77c1b798cdb6a26283803ff14ef9287f">DO_BLOCKED_FLAG_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 220 |
|
|
<a name="l00192"></a><a class="code" href="ao68000_8v.html#aef77b8b57b180509202a0012e7386da5">00192</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac69029fe984c3090537ed247a8106344">DO_BLOCKED_FLAG_SET</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// set, block processor</span>
|
| 221 |
|
|
<a name="l00193"></a>00193
|
| 222 |
|
|
<a name="l00194"></a><a class="code" href="ao68000_8v.html#a4497060651e910cc03544b6fab57a78d">00194</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aea55c86a7b738d149d82f7205edfd072">DATA_WRITE_IDLE</a> <span class="vhdllogic">2'd0</span>
|
| 223 |
|
|
<a name="l00195"></a><a class="code" href="ao68000_8v.html#a85d61d3f40907dd6fade18144aafd033">00195</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab576808298f9e1938241b8843e55c54e">DATA_WRITE_FROM_RESULT</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// load data write register from result register</span>
|
| 224 |
|
|
<a name="l00196"></a>00196
|
| 225 |
|
|
<a name="l00197"></a><a class="code" href="ao68000_8v.html#a9fb69d6fec3e8749781e97efec6eb06e">00197</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a107302370f5dbc56a4fb626569a97030">AN_ADDRESS_IDLE</a> <span class="vhdllogic">2'd0</span> <span class="keyword">// load from ea_reg, user or supervisor</span>
|
| 226 |
|
|
<a name="l00198"></a><a class="code" href="ao68000_8v.html#a3230219b3d822c8b34b433800dca9cbc">00198</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a50986c5b3afb053fcb3841dce7a93115">AN_ADDRESS_FROM_EXTENDED</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// load from extended instruction word: ir1[14:12], user or supervisor</span>
|
| 227 |
|
|
<a name="l00199"></a><a class="code" href="ao68000_8v.html#ad996a71d6b3f2d14f6e8d6a4e1f72a55">00199</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ad5d4b9f48266549b9e8e5ac0c3ad239a">AN_ADDRESS_USP</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// load USP address</span>
|
| 228 |
|
|
<a name="l00200"></a><a class="code" href="ao68000_8v.html#a204250e0abcb7d62c16fd929ffda29af">00200</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0dff5098fabf2afeac419c2e3c69b452">AN_ADDRESS_SSP</a> <span class="vhdllogic">2'd3</span> <span class="keyword">// load SSP address</span>
|
| 229 |
|
|
<a name="l00201"></a>00201
|
| 230 |
|
|
<a name="l00202"></a><a class="code" href="ao68000_8v.html#a672f0b2216f1bcf07fd60f10ffb02d2b">00202</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a07cd63c0bfba6d76b1905298a99f854c">AN_WRITE_ENABLE_IDLE</a> <span class="vhdllogic">1'd0</span>
|
| 231 |
|
|
<a name="l00203"></a><a class="code" href="ao68000_8v.html#a8a5b3874603380e1b7fc5f5bde929f79">00203</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa75c6a17ea004be38c442cad25207ca6">AN_WRITE_ENABLE_SET</a> <span class="vhdllogic">1'd1</span> <span class="keyword">// set write enable on An register</span>
|
| 232 |
|
|
<a name="l00204"></a>00204
|
| 233 |
|
|
<a name="l00205"></a><a class="code" href="ao68000_8v.html#a0659c4a78e258ecdbe84cc62b7c72c1f">00205</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#acfb395959ef2700610f60fc82f37ab50">AN_INPUT_IDLE</a> <span class="vhdllogic">2'd0</span> <span class="keyword">// load from result</span>
|
| 234 |
|
|
<a name="l00206"></a><a class="code" href="ao68000_8v.html#a789f400fe408fd869d82e959dc52d329">00206</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a67d98f6de465730c1bc9792aab02784c">AN_INPUT_FROM_ADDRESS</a> <span class="vhdllogic">2'd1</span> <span class="keyword">// load from address</span>
|
| 235 |
|
|
<a name="l00207"></a><a class="code" href="ao68000_8v.html#aec3e5bdcb57b25cb4db201c411f110be">00207</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a90bc8bad52abb88cc05948307f41ffcf">AN_INPUT_FROM_PREFETCH_IR</a> <span class="vhdllogic">2'd2</span> <span class="keyword">// load from prefetch_ir, for reset, for SSP</span>
|
| 236 |
|
|
<a name="l00208"></a>00208
|
| 237 |
|
|
<a name="l00209"></a><a class="code" href="ao68000_8v.html#ae39d4c3690af2ea35bf4ddde54cf9020">00209</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ace818e631ab56c55afcfca9204e98e63">DN_ADDRESS_IDLE</a> <span class="vhdllogic">1'd0</span> <span class="keyword">// load from ea_reg</span>
|
| 238 |
|
|
<a name="l00210"></a><a class="code" href="ao68000_8v.html#a2356a4dd1a5ca20df51978f02cd26ea1">00210</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aad74420658cfe8412a03c3dd6654ceb1">DN_ADDRESS_FROM_EXTENDED</a> <span class="vhdllogic">1'd1</span> <span class="keyword">// load from extended instruction word: ir1[14:12]</span>
|
| 239 |
|
|
<a name="l00211"></a>00211
|
| 240 |
|
|
<a name="l00212"></a><a class="code" href="ao68000_8v.html#a119d6fdee52f58ecd97d849fb7787933">00212</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6bb12655a3c731478432010788a19b3a">DN_WRITE_ENABLE_IDLE</a> <span class="vhdllogic">1'd0</span>
|
| 241 |
|
|
<a name="l00213"></a><a class="code" href="ao68000_8v.html#aa88ef95674720505ccf731b70eec839c">00213</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8d8686a40be339821aec7a13bb091f9b">DN_WRITE_ENABLE_SET</a> <span class="vhdllogic">1'd1</span> <span class="keyword">// set write enable on Dn register</span>
|
| 242 |
|
|
<a name="l00214"></a>00214
|
| 243 |
|
|
<a name="l00215"></a><a class="code" href="ao68000_8v.html#a185a231c9d82a5cb8f49c9f782bc14e7">00215</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aea95dec53ff31c627c3378441fb8777e">ALU_IDLE</a> <span class="vhdllogic">5'd0</span>
|
| 244 |
|
|
<a name="l00216"></a><a class="code" href="ao68000_8v.html#a43279337ab58ad64b0b08c2e341d1f86">00216</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a687e6310453b4cedb64aa6e66b058c18">ALU_SR_SET_INTERRUPT</a> <span class="vhdllogic">5'd1</span>
|
| 245 |
|
|
<a name="l00217"></a><a class="code" href="ao68000_8v.html#a5ae55f6c41e7d2c76bb1aab2e4b0711d">00217</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac9fc44b8d3bbcd6c742f1ba074fc668d">ALU_SR_SET_TRAP</a> <span class="vhdllogic">5'd2</span>
|
| 246 |
|
|
<a name="l00218"></a><a class="code" href="ao68000_8v.html#abd5cc513b37f9596dd8d296c07f965b3">00218</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a59147ff996e0ba496f1f06d7a06decae">ALU_MOVEP_M2R_1</a> <span class="vhdllogic">5'd3</span>
|
| 247 |
|
|
<a name="l00219"></a><a class="code" href="ao68000_8v.html#a4f153e60b25292ce0144c4b34f387120">00219</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3b1155f3496b0fc984e5418e09586bf5">ALU_MOVEP_M2R_2</a> <span class="vhdllogic">5'd4</span>
|
| 248 |
|
|
<a name="l00220"></a><a class="code" href="ao68000_8v.html#a79875173f36e931760163dcc0efe0c03">00220</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5458c8548afc8f7517bdc582c9946b2f">ALU_MOVEP_M2R_3</a> <span class="vhdllogic">5'd5</span>
|
| 249 |
|
|
<a name="l00221"></a><a class="code" href="ao68000_8v.html#a53f050eb21a4574cd4d08fe0e94061b3">00221</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8ec0074ca9c5cfec15aa93b92353e09b">ALU_MOVEP_M2R_4</a> <span class="vhdllogic">5'd6</span>
|
| 250 |
|
|
<a name="l00222"></a><a class="code" href="ao68000_8v.html#a646019a185af1b8a4dfe560d6285ce80">00222</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aab7548aba43c6c12259a2a154ce2982b">ALU_MOVEP_R2M_1</a> <span class="vhdllogic">5'd7</span>
|
| 251 |
|
|
<a name="l00223"></a><a class="code" href="ao68000_8v.html#a1a72309c52cb532f2783bd9ac1e176fb">00223</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9918f4663f481092da549f3cb008721d">ALU_MOVEP_R2M_2</a> <span class="vhdllogic">5'd8</span>
|
| 252 |
|
|
<a name="l00224"></a><a class="code" href="ao68000_8v.html#a1deb70ff2190d570e5f62639cd041d41">00224</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aee5fc91f58c97ffa4d252e127c9e4226">ALU_MOVEP_R2M_3</a> <span class="vhdllogic">5'd9</span>
|
| 253 |
|
|
<a name="l00225"></a><a class="code" href="ao68000_8v.html#ab602f685f46b237439ecf15880fcf47e">00225</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0bc85184fda7b9fcbf00afa29be91d42">ALU_MOVEP_R2M_4</a> <span class="vhdllogic">5'd10</span>
|
| 254 |
|
|
<a name="l00226"></a><a class="code" href="ao68000_8v.html#afc500b39154287dadc5832fc02eae035">00226</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6a119b7268e4e0a78e0307ba0c693ccb">ALU_SIGN_EXTEND</a> <span class="vhdllogic">5'd11</span>
|
| 255 |
|
|
<a name="l00227"></a><a class="code" href="ao68000_8v.html#af7eb69558c00ab2aff17bc03da09fe45">00227</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae497ab0b3e0550245c333bdb426d4236">ALU_ARITHMETIC_LOGIC</a> <span class="vhdllogic">5'd12</span>
|
| 256 |
|
|
<a name="l00228"></a><a class="code" href="ao68000_8v.html#a601f3c5b34accd66ec4e72cf420a5e0b">00228</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3e54001e73374bd4f7cfda3de55bd944">ALU_ABCD_SBCD_ADDX_SUBX</a> <span class="vhdllogic">5'd13</span>
|
| 257 |
|
|
<a name="l00229"></a><a class="code" href="ao68000_8v.html#a391413e929d9cd0171a175a4641c5683">00229</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac444f659b2726fd335e839dfadabbfe3">ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare</a> <span class="vhdllogic">5'd14</span>
|
| 258 |
|
|
<a name="l00230"></a><a class="code" href="ao68000_8v.html#a5e01e942b55a31404115a39740827c62">00230</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac946f278d039868214c441c11fcf2587">ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR</a> <span class="vhdllogic">5'd15</span>
|
| 259 |
|
|
<a name="l00231"></a><a class="code" href="ao68000_8v.html#a593c63ceb3669ccb39c366b9573bf314">00231</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a268aa82704bd8f1c1548dfc69a12a951">ALU_MOVE</a> <span class="vhdllogic">5'd16</span>
|
| 260 |
|
|
<a name="l00232"></a><a class="code" href="ao68000_8v.html#a1b4695a72b8d0e3f710df6f86030d56c">00232</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a30a87601d2ca38286bb0d486d59f6a07">ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ</a> <span class="vhdllogic">5'd17</span>
|
| 261 |
|
|
<a name="l00233"></a><a class="code" href="ao68000_8v.html#a2b23555c0e46c828ed661af45443f50f">00233</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af0a4db089a5eb288abf9453ca2d79c26">ALU_CHK</a> <span class="vhdllogic">5'd18</span>
|
| 262 |
|
|
<a name="l00234"></a><a class="code" href="ao68000_8v.html#ab6f46721fa6d6a108c01a61e2d661ee3">00234</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">ALU_MULS_MULU_DIVS_DIVU</a> <span class="vhdllogic">5'd19</span>
|
| 263 |
|
|
<a name="l00235"></a><a class="code" href="ao68000_8v.html#ab5f2abdb56e7a6936c4ab271580bba52">00235</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a14b85ce3e5b4ede3b2c4e89f420c8c3c">ALU_BCHG_BCLR_BSET_BTST</a> <span class="vhdllogic">5'd20</span>
|
| 264 |
|
|
<a name="l00236"></a><a class="code" href="ao68000_8v.html#a436fe5adcadbae571eedb35dd98487ac">00236</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac7de3ab6c8eec4381bde5e4f61b45761">ALU_TAS</a> <span class="vhdllogic">5'd21</span>
|
| 265 |
|
|
<a name="l00237"></a><a class="code" href="ao68000_8v.html#aa191713af71dd78ddfe6a9dee3d2d1bc">00237</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a07c7e53af3f4995a167966ba18c2728f">ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT</a> <span class="vhdllogic">5'd22</span>
|
| 266 |
|
|
<a name="l00238"></a><a class="code" href="ao68000_8v.html#ad6a90b18962092a662ad077d57984652">00238</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a32c0e163ff437b07e40593ab59e42fe3">ALU_SIMPLE_LONG_ADD</a> <span class="vhdllogic">5'd23</span>
|
| 267 |
|
|
<a name="l00239"></a><a class="code" href="ao68000_8v.html#a06f84841e35fc97186b630f26f150869">00239</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aea6fee15f3d775b1a8d262490203c713">ALU_SIMPLE_LONG_SUB</a> <span class="vhdllogic">5'd24</span>
|
| 268 |
|
|
<a name="l00240"></a><a class="code" href="ao68000_8v.html#a3c579fa060ac05434f085b03edf68501">00240</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5083d98f4b785fe7af85ba1114f678ff">ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR</a> <span class="vhdllogic">5'd25</span>
|
| 269 |
|
|
<a name="l00241"></a><a class="code" href="ao68000_8v.html#a29a77523d5e44bf1df8a8203c033cc05">00241</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab6d6f774c41848f9c33c7b393620be2d">ALU_SIMPLE_MOVE</a> <span class="vhdllogic">5'd26</span>
|
| 270 |
|
|
<a name="l00242"></a><a class="code" href="ao68000_8v.html#ae3067aec1dc26a3d09f0c7a730422110">00242</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac439a8b79bd4b213f0f33172bd5e5a73">ALU_LINK_MOVE</a> <span class="vhdllogic">5'd27</span>
|
| 271 |
|
|
<a name="l00243"></a>00243
|
| 272 |
|
|
<a name="l00244"></a><a class="code" href="ao68000_8v.html#af733b52724e9524ce18eae512df35480">00244</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6cf12df8a04c3df66b43fb7301e424e9">BRANCH_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 273 |
|
|
<a name="l00245"></a><a class="code" href="ao68000_8v.html#a82d805b282202c87398b9712a85b58f1">00245</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#abdfc603db0ea3694052298e85fb6efad">BRANCH_movem_loop</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// BRANCH(movem_loop == 4'b1000)</span>
|
| 274 |
|
|
<a name="l00246"></a><a class="code" href="ao68000_8v.html#aa62d45e622148f3f284300cd1c8ec385">00246</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#acc65cf5ec49ce78ecf98c956cd2de769">BRANCH_movem_reg</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// BRANCH(movem_reg[0] == 0)</span>
|
| 275 |
|
|
<a name="l00247"></a><a class="code" href="ao68000_8v.html#afc9bc6cac2e242769d2598a29fedf825">00247</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa0b5846a5e98be60da75608078377571">BRANCH_operand2</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// BRANCH(operand2[5:0] == 6'b0)</span>
|
| 276 |
13 |
alfik |
<a name="l00248"></a><a class="code" href="ao68000_8v.html#a7ad9ea4a5ffa00527c26fa64ad75bf4c">00248</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3db021156e8171951f6b91c78bbb7e1f">BRANCH_alu_signal</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// BRANCH(alu_signal == 1'b0)</span>
|
| 277 |
|
|
<a name="l00249"></a><a class="code" href="ao68000_8v.html#a176308e082b64f5fd73d9f046b6a8594">00249</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a62fe8e5939da15f9f391886fe174183a">BRANCH_alu_mult_div_ready</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// BRANCH(alu_mult_div_ready == 1'b1)</span>
|
| 278 |
12 |
alfik |
<a name="l00250"></a><a class="code" href="ao68000_8v.html#a30c4a8c9db7c14ea5317270becb6240c">00250</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af3158a11a9fc793d4aeead4195871507">BRANCH_condition_0</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// BRANCH(condition == 1'b0)</span>
|
| 279 |
|
|
<a name="l00251"></a><a class="code" href="ao68000_8v.html#a4539242544f8cd667a6ce0deac0d788d">00251</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a48d5a0127f3bc738b8503c0713b9fba9">BRANCH_condition_1</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// BRANCH(condition == 1'b1)</span>
|
| 280 |
|
|
<a name="l00252"></a><a class="code" href="ao68000_8v.html#abdf93f72eff40b1a560a95062afe148f">00252</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0cbdc7b4e718d5cc690b435995bb7708">BRANCH_result</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// BRANCH(result[15:0] == 16'hFFFF)</span>
|
| 281 |
|
|
<a name="l00253"></a><a class="code" href="ao68000_8v.html#a1d95cdc4aa317fc88b00283fb14fe0dd">00253</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3861f0d4bd11e996bda23577348e86f7">BRANCH_V</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// BRANCH(V == 1'b0)</span>
|
| 282 |
|
|
<a name="l00254"></a><a class="code" href="ao68000_8v.html#abc054cf1d1155b7c0bb40bfa31fe2b66">00254</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5fb736520363d5359408ed4af63c6125">BRANCH_movep_16</a> <span class="vhdllogic">4'd10</span> <span class="keyword">// BRANCH(ir[6] == 0)</span>
|
| 283 |
|
|
<a name="l00255"></a><a class="code" href="ao68000_8v.html#a2136a9cf3941acd7a5d9c62e282fc6fb">00255</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">BRANCH_stop_flag_wait_ir_decode</a> <span class="vhdllogic">4'd11</span> <span class="keyword">// BRANCH(stop_flag == 1'b1) if no branch: wait for prefetch ir valid and decode instruction</span>
|
| 284 |
|
|
<a name="l00256"></a><a class="code" href="ao68000_8v.html#af29c19330ca8b945ab8d9280b0a79c82">00256</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a719e200160515b706ebab9fe1e18c8c7">BRANCH_ir</a> <span class="vhdllogic">4'd12</span> <span class="keyword">// BRANCH(ir[7:0] != 8'b0)</span>
|
| 285 |
|
|
<a name="l00257"></a><a class="code" href="ao68000_8v.html#a77c4ea1006f7e281f908731fa586e28a">00257</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af396200d0e5941fe60e8d960f2e3aa91">BRANCH_trace_flag_and_interrupt</a> <span class="vhdllogic">4'd13</span> <span class="keyword">// BRANCH(trace_flag == 1'b0 && interrupt_mask != 3'b000) if no branch: jump to main loop</span>
|
| 286 |
|
|
<a name="l00258"></a><a class="code" href="ao68000_8v.html#ac54a3fc8c9f015e1175bc1793fb7ebfd">00258</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a63f967b1bbe9ad356e3ccbbb2924e03f">BRANCH_group_0_flag</a> <span class="vhdllogic">4'd14</span> <span class="keyword">// BRANCH(group_0_flag == 0)</span>
|
| 287 |
|
|
<a name="l00259"></a><a class="code" href="ao68000_8v.html#ab753c6979146d57589c24a73cb13b501">00259</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">BRANCH_procedure</a> <span class="vhdllogic">4'd15</span> <span class="keyword">// call procedure, return from procedure</span>
|
| 288 |
|
|
<a name="l00260"></a>00260
|
| 289 |
|
|
<a name="l00261"></a><a class="code" href="ao68000_8v.html#ade10675cfd99420bd3a287db52dfc17a">00261</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a98081d1329be92c30eb943724c0cef86">PROCEDURE_IDLE</a> <span class="vhdllogic">4'd0</span>
|
| 290 |
|
|
<a name="l00262"></a><a class="code" href="ao68000_8v.html#a9a6fa21e702ac35eeefb6d4ef6472fdd">00262</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5c7af3686fb890de6242f973de1ee549">PROCEDURE_call_load_ea</a> <span class="vhdllogic">4'd1</span> <span class="keyword">// load ea</span>
|
| 291 |
|
|
<a name="l00263"></a><a class="code" href="ao68000_8v.html#afc4dc88ce07d49ad1754962b413978ce">00263</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a698b04745cbbec22896235d5cfffac43">PROCEDURE_call_perform_ea_read</a> <span class="vhdllogic">4'd2</span> <span class="keyword">// perform_ea_read</span>
|
| 292 |
|
|
<a name="l00264"></a><a class="code" href="ao68000_8v.html#a87c36a08818823df8de112dbe5caaebf">00264</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa98c954da2ac9f709907c8c593b1439e">PROCEDURE_call_perform_ea_write</a> <span class="vhdllogic">4'd3</span> <span class="keyword">// perform_ea_write</span>
|
| 293 |
|
|
<a name="l00265"></a><a class="code" href="ao68000_8v.html#abc8942a868848a7669b61773b6251093">00265</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a30022c5eb1821e27dd5c70d4affbc835">PROCEDURE_call_save_ea</a> <span class="vhdllogic">4'd4</span> <span class="keyword">// save ea</span>
|
| 294 |
|
|
<a name="l00266"></a><a class="code" href="ao68000_8v.html#a8926d78d8690a5f5b6dfa6d41f553f39">00266</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af842761d13933777546d76bd997e7494">PROCEDURE_return</a> <span class="vhdllogic">4'd5</span> <span class="keyword">// return from procedure</span>
|
| 295 |
|
|
<a name="l00267"></a><a class="code" href="ao68000_8v.html#aa41b49eec539fbca25bc9368c26f077a">00267</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a26a2f20a92ff8ab6f13d6633f3c9475c">PROCEDURE_wait_finished</a> <span class="vhdllogic">4'd6</span> <span class="keyword">// wait for finished signal from bus controler</span>
|
| 296 |
|
|
<a name="l00268"></a><a class="code" href="ao68000_8v.html#acefb835b19db5c68d5b41002f77c8fa0">00268</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa072f73b12cd178a44f47980e1bb98cb">PROCEDURE_wait_prefetch_valid</a> <span class="vhdllogic">4'd7</span> <span class="keyword">// wait for prefetch ir valid, 64 bits</span>
|
| 297 |
|
|
<a name="l00269"></a><a class="code" href="ao68000_8v.html#a247183de3681e23a64f17850ae339a46">00269</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0ef2adec86a42dd30d78e9d259d828fd">PROCEDURE_wait_prefetch_valid_32</a> <span class="vhdllogic">4'd8</span> <span class="keyword">// wait for prefetch ir valid, 32 bits</span>
|
| 298 |
|
|
<a name="l00270"></a><a class="code" href="ao68000_8v.html#a98c5a07ca4b8f55b285464572d984964">00270</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a7950509479648899370516cfa0221c43">PROCEDURE_jump_to_main_loop</a> <span class="vhdllogic">4'd9</span> <span class="keyword">// jump to main loop</span>
|
| 299 |
|
|
<a name="l00271"></a><a class="code" href="ao68000_8v.html#a261ee70d7c2dd9f84476f009b062eeb0">00271</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a318a0823db3c0aa8dfeae26f05495e5b">PROCEDURE_push_micropc</a> <span class="vhdllogic">4'd10</span> <span class="keyword">// save current micro_pc</span>
|
| 300 |
|
|
<a name="l00272"></a><a class="code" href="ao68000_8v.html#ad43b342d0876d583ad40ecf910724954">00272</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2c67cc2747b67d04684855e14c2b9fbb">PROCEDURE_call_trap</a> <span class="vhdllogic">4'd11</span> <span class="keyword">// call trap service procedure</span>
|
| 301 |
|
|
<a name="l00273"></a><a class="code" href="ao68000_8v.html#a01e61f6c91ea808bf15c0bc327fcd3ca">00273</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#acfe58e669e77374120e6e534fc621316">PROCEDURE_pop_micropc</a> <span class="vhdllogic">4'd12</span> <span class="keyword">// pop most recent micro_pc and forget</span>
|
| 302 |
|
|
<a name="l00274"></a><a class="code" href="ao68000_8v.html#ab90a26325a5af04ad9433faa3edd5e2e">00274</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac74b95b43e6c95ed82036002767bc22c">PROCEDURE_interrupt_mask</a> <span class="vhdllogic">4'd13</span> <span class="keyword">// if interrupt active continue, else jump to main loop</span>
|
| 303 |
|
|
<a name="l00275"></a><a class="code" href="ao68000_8v.html#aefb64784846ddb9132483912192632d8">00275</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">PROCEDURE_call_read</a> <span class="vhdllogic">4'd14</span> <span class="keyword">// load_ea + perform_ea_read</span>
|
| 304 |
|
|
<a name="l00276"></a><a class="code" href="ao68000_8v.html#ad9a98b2cb48c9cb4442ac3ebecd260bc">00276</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a50af2007588b7a528b934ae7672b1214">PROCEDURE_call_write</a> <span class="vhdllogic">4'd15</span> <span class="keyword">// perform_ea_write + save_ea + return</span>
|
| 305 |
|
|
<a name="l00277"></a>00277 <span class="keyword">// OPERATIONS END</span>
|
| 306 |
|
|
<a name="l00278"></a>00278
|
| 307 |
|
|
<a name="l00279"></a>00279 <span class="keyword">/***********************************************************************************************************************</span>
|
| 308 |
|
|
<a name="l00280"></a>00280 <span class="keyword"> Automatically generated by ao68000_tool microcode word bit assignments and addresses</span>
|
| 309 |
|
|
<a name="l00281"></a>00281 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 310 |
|
|
<a name="l00282"></a>00282 <span class="keyword">// MICROCODE - DO NOT EDIT BELOW</span>
|
| 311 |
|
|
<a name="l00283"></a><a class="code" href="ao68000_8v.html#a6ef81425ac3daa6970f3df92db1a6325">00283</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3a14e27ef3dcc344f66e5eb0aa93d38d">MICRO_DATA_ea_reg</a> micro_data[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>]
|
| 312 |
|
|
<a name="l00284"></a><a class="code" href="ao68000_8v.html#aabf523bb3e9ede36111acd537aca70f9">00284</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa691c194246c2ac4def5609ba8963326">MICRO_DATA_ea_mod</a> micro_data[<span class="vhdllogic">6</span>:<span class="vhdllogic">3</span>]
|
| 313 |
|
|
<a name="l00285"></a><a class="code" href="ao68000_8v.html#a1ec6741ebf273336ec4584d66ae37ffe">00285</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae45014e01523ad88c7b7bd74cdb1b8db">MICRO_DATA_ea_type</a> micro_data[<span class="vhdllogic">10</span>:<span class="vhdllogic">7</span>]
|
| 314 |
|
|
<a name="l00286"></a><a class="code" href="ao68000_8v.html#afebf33d60f4f8be00b3d6fa7afdd326d">00286</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a80f755d97ef46590665dc161a3de3f60">MICRO_DATA_op1</a> micro_data[<span class="vhdllogic">14</span>:<span class="vhdllogic">11</span>]
|
| 315 |
|
|
<a name="l00287"></a><a class="code" href="ao68000_8v.html#aa695bec37252c32e10742b0d9f1e38b6">00287</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab1641cfecafe6ff147522b68bd7f9c0d">MICRO_DATA_op2</a> micro_data[<span class="vhdllogic">17</span>:<span class="vhdllogic">15</span>]
|
| 316 |
|
|
<a name="l00288"></a><a class="code" href="ao68000_8v.html#a33a5e1963bf65b251c0f3ff5f7572732">00288</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a600647e8ee417a6f81b00e53f101af5f">MICRO_DATA_address</a> micro_data[<span class="vhdllogic">21</span>:<span class="vhdllogic">18</span>]
|
| 317 |
|
|
<a name="l00289"></a><a class="code" href="ao68000_8v.html#aa7ee2698a06d94f380745c7bbe936426">00289</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a73de1704db2fb003c3a2da4b3f1667de">MICRO_DATA_size</a> micro_data[<span class="vhdllogic">25</span>:<span class="vhdllogic">22</span>]
|
| 318 |
|
|
<a name="l00290"></a><a class="code" href="ao68000_8v.html#ad0b1624b8cc4a2d03fce11254f960372">00290</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a73831c7c30f75ec6e263ce47f1a3fb64">MICRO_DATA_movem_modreg</a> micro_data[<span class="vhdllogic">28</span>:<span class="vhdllogic">26</span>]
|
| 319 |
|
|
<a name="l00291"></a><a class="code" href="ao68000_8v.html#a4176bd40d99ee111db2bea0109349a1a">00291</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a93b7332d93eddbed779bba21295794f3">MICRO_DATA_movem_loop</a> micro_data[<span class="vhdllogic">30</span>:<span class="vhdllogic">29</span>]
|
| 320 |
|
|
<a name="l00292"></a><a class="code" href="ao68000_8v.html#a6c3ad387c24516778b554de5f544e9bf">00292</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5246b6d3ea1d05aa2d34597666a8da31">MICRO_DATA_movem_reg</a> micro_data[<span class="vhdllogic">32</span>:<span class="vhdllogic">31</span>]
|
| 321 |
|
|
<a name="l00293"></a><a class="code" href="ao68000_8v.html#aa198c1bed97e0ad6f7f4f6f24c77766d">00293</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a15830df6bfc267949eaeb9c862ec021a">MICRO_DATA_ir</a> micro_data[<span class="vhdllogic">34</span>:<span class="vhdllogic">33</span>]
|
| 322 |
|
|
<a name="l00294"></a><a class="code" href="ao68000_8v.html#aa1775c009cc16c3a6bcc068f1de3bd9f">00294</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a35a9274fdd4fa537efdb15f0b0b787e6">MICRO_DATA_pc</a> micro_data[<span class="vhdllogic">37</span>:<span class="vhdllogic">35</span>]
|
| 323 |
|
|
<a name="l00295"></a><a class="code" href="ao68000_8v.html#a5f10c6462da6c4004edd6ba127cc3925">00295</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac4878c2a7cf765d443c1c9da238b5ac9">MICRO_DATA_trap</a> micro_data[<span class="vhdllogic">41</span>:<span class="vhdllogic">38</span>]
|
| 324 |
|
|
<a name="l00296"></a><a class="code" href="ao68000_8v.html#a1344c6a09cd514e33cf879638e0c0f3f">00296</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4deaea8bc3d376dac501f3a314f1490c">MICRO_DATA_offset</a> micro_data[<span class="vhdllogic">43</span>:<span class="vhdllogic">42</span>]
|
| 325 |
|
|
<a name="l00297"></a><a class="code" href="ao68000_8v.html#a16f46e3da89023238a3206da9a864245">00297</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ad722ce87f573d9c6e1010e5a87005383">MICRO_DATA_index</a> micro_data[<span class="vhdllogic">45</span>:<span class="vhdllogic">44</span>]
|
| 326 |
|
|
<a name="l00298"></a><a class="code" href="ao68000_8v.html#af463d6dfe088ed4971bee9cbb4220142">00298</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5e820e2a23919cb4005a8cc9651c26c0">MICRO_DATA_stop_flag</a> micro_data[<span class="vhdllogic">47</span>:<span class="vhdllogic">46</span>]
|
| 327 |
|
|
<a name="l00299"></a><a class="code" href="ao68000_8v.html#ab6bf25c868a11c4ebe2b87367a5d123b">00299</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa913e0fe5ccffe6e2d7e91d43f39f139">MICRO_DATA_trace_flag</a> micro_data[<span class="vhdllogic">49</span>:<span class="vhdllogic">48</span>]
|
| 328 |
|
|
<a name="l00300"></a><a class="code" href="ao68000_8v.html#ae4ccc6dc98a4bd404249c5f291ba4d6a">00300</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a595e837c71d69c5a4d7c4a3c9d64ffb0">MICRO_DATA_group_0_flag</a> micro_data[<span class="vhdllogic">51</span>:<span class="vhdllogic">50</span>]
|
| 329 |
|
|
<a name="l00301"></a><a class="code" href="ao68000_8v.html#ac227ea998ce2e81e10a1be6ec9ebc4c1">00301</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a188c9ee8d0adc5ec2fb732fdece9ea31">MICRO_DATA_instruction_flag</a> micro_data[<span class="vhdllogic">53</span>:<span class="vhdllogic">52</span>]
|
| 330 |
|
|
<a name="l00302"></a><a class="code" href="ao68000_8v.html#a87951ae08bef1208fd636efc0d65cdf3">00302</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae152374d2c661e9bfcb222888087b18f">MICRO_DATA_read_modify_write_flag</a> micro_data[<span class="vhdllogic">55</span>:<span class="vhdllogic">54</span>]
|
| 331 |
|
|
<a name="l00303"></a><a class="code" href="ao68000_8v.html#a87d9ca517e0db145b9fa96c1d4f1b48c">00303</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a05f6c84753b5b54fe61fe36a740b739d">MICRO_DATA_do_reset_flag</a> micro_data[<span class="vhdllogic">57</span>:<span class="vhdllogic">56</span>]
|
| 332 |
|
|
<a name="l00304"></a><a class="code" href="ao68000_8v.html#a4512f2422910357f4ae9f0f39ff60e60">00304</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a989be17e3392ddf7c87fcf41a9c1576b">MICRO_DATA_do_interrupt_flag</a> micro_data[<span class="vhdllogic">59</span>:<span class="vhdllogic">58</span>]
|
| 333 |
|
|
<a name="l00305"></a><a class="code" href="ao68000_8v.html#a40acececb0e30e947f36e1ca1bc70e14">00305</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3935f3fc6e20767fdeee079bdb08648f">MICRO_DATA_do_read_flag</a> micro_data[<span class="vhdllogic">61</span>:<span class="vhdllogic">60</span>]
|
| 334 |
|
|
<a name="l00306"></a><a class="code" href="ao68000_8v.html#ad6b47390e7d45cfdf3ed7898509205b0">00306</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a42e2926c262bd037f32951c89a51067e">MICRO_DATA_do_write_flag</a> micro_data[<span class="vhdllogic">63</span>:<span class="vhdllogic">62</span>]
|
| 335 |
|
|
<a name="l00307"></a><a class="code" href="ao68000_8v.html#a16327822b3b9a8f8b0de245867c0aca0">00307</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#adf7ac746fc276a0c3083d2606df75af4">MICRO_DATA_do_blocked_flag</a> micro_data[<span class="vhdllogic">65</span>:<span class="vhdllogic">64</span>]
|
| 336 |
|
|
<a name="l00308"></a><a class="code" href="ao68000_8v.html#ae04a1798dc92a3bacae2f52455ee8d91">00308</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0843baa7810722c7e1afd79aa615a9f0">MICRO_DATA_data_write</a> micro_data[<span class="vhdllogic">67</span>:<span class="vhdllogic">66</span>]
|
| 337 |
|
|
<a name="l00309"></a><a class="code" href="ao68000_8v.html#adf492d3aba5a96fb92981329623efa9c">00309</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a08e217a2a40544a7d5c4e916a3b4d6cf">MICRO_DATA_an_address</a> micro_data[<span class="vhdllogic">69</span>:<span class="vhdllogic">68</span>]
|
| 338 |
|
|
<a name="l00310"></a><a class="code" href="ao68000_8v.html#a8f7a4c24e52ade0663ac1d4b47afe44c">00310</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af767fe70444603fdcde8beb39ef85c8c">MICRO_DATA_an_write_enable</a> micro_data[<span class="vhdllogic">70</span>:<span class="vhdllogic">70</span>]
|
| 339 |
|
|
<a name="l00311"></a><a class="code" href="ao68000_8v.html#aa0630462dc3f0aa3c8ef1440d0f6b5ce">00311</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa6a6132c427e511630e6889582d48828">MICRO_DATA_an_input</a> micro_data[<span class="vhdllogic">72</span>:<span class="vhdllogic">71</span>]
|
| 340 |
|
|
<a name="l00312"></a><a class="code" href="ao68000_8v.html#a3fc5b433434a63c13fd4540e85e88622">00312</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1055ed2c94344c9b59a9061b451fd4b8">MICRO_DATA_dn_address</a> micro_data[<span class="vhdllogic">73</span>:<span class="vhdllogic">73</span>]
|
| 341 |
|
|
<a name="l00313"></a><a class="code" href="ao68000_8v.html#a1e73bf0857c4744890d7f94536512299">00313</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#abb7709933320bf644d6a57c3040538a3">MICRO_DATA_dn_write_enable</a> micro_data[<span class="vhdllogic">74</span>:<span class="vhdllogic">74</span>]
|
| 342 |
|
|
<a name="l00314"></a><a class="code" href="ao68000_8v.html#acd1f66614af2cf0c231cf93248b8582e">00314</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6dde91e1905423f9fb4184ae3554b5cd">MICRO_DATA_alu</a> micro_data[<span class="vhdllogic">79</span>:<span class="vhdllogic">75</span>]
|
| 343 |
|
|
<a name="l00315"></a><a class="code" href="ao68000_8v.html#a56c56c6560eb00fb6a9ba6211e95cb65">00315</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a156b8e8011ac86392d0e47b50cc1bd12">MICRO_DATA_branch</a> micro_data[<span class="vhdllogic">83</span>:<span class="vhdllogic">80</span>]
|
| 344 |
|
|
<a name="l00316"></a><a class="code" href="ao68000_8v.html#a773f710aeba391c02509192b69de3fbd">00316</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8356eb451657c128626552b5a360de3a">MICRO_DATA_procedure</a> micro_data[<span class="vhdllogic">87</span>:<span class="vhdllogic">84</span>]
|
| 345 |
|
|
<a name="l00317"></a>00317
|
| 346 |
|
|
<a name="l00318"></a><a class="code" href="ao68000_8v.html#a1968dd1421c5a999838228e955a82d40">00318</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#afadd69027964ef6d7c9f923ed2714bbe">MICROPC_MOVE</a> <span class="vhdllogic">9'd231</span>
|
| 347 |
13 |
alfik |
<a name="l00319"></a><a class="code" href="ao68000_8v.html#a05e53cc87165049f906e67afa2329da4">00319</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a506e512a7df02654649a4275b676b5f7">MICROPC_MOVE_USP_to_An</a> <span class="vhdllogic">9'd400</span>
|
| 348 |
|
|
<a name="l00320"></a><a class="code" href="ao68000_8v.html#ac178cc762c349f3c500fb01ccf59abe9">00320</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9d9308b3732ecf15f57a22600ac300b8">MICROPC_TAS</a> <span class="vhdllogic">9'd332</span>
|
| 349 |
|
|
<a name="l00321"></a><a class="code" href="ao68000_8v.html#a0d2cfeb23b6f839077af216e173e1237">00321</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#afefae415ee468c051f367b74183a122b">MICROPC_BSR</a> <span class="vhdllogic">9'd430</span>
|
| 350 |
12 |
alfik |
<a name="l00322"></a><a class="code" href="ao68000_8v.html#abf77fcda5659a23885d5fc4b0d8368ce">00322</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ada4b6f4df06a5dcac3ec15d4c8f4d31e">MICROPC_ADDRESS_BUS_TRAP</a> <span class="vhdllogic">9'd3</span>
|
| 351 |
|
|
<a name="l00323"></a><a class="code" href="ao68000_8v.html#a32257a88f74b022c9cb886f2e94cd426">00323</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2516dd6bb3a4f804a752557b483e077b">MICROPC_MOVEP_register_to_memory</a> <span class="vhdllogic">9'd106</span>
|
| 352 |
13 |
alfik |
<a name="l00324"></a><a class="code" href="ao68000_8v.html#aa7a60b9cfa407e7a0216770809f65b7c">00324</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6f040be4f69b57ba9603d5eae6085425">MICROPC_NEGX_CLR_NEG_NOT_NBCD</a> <span class="vhdllogic">9'd337</span>
|
| 353 |
|
|
<a name="l00325"></a><a class="code" href="ao68000_8v.html#a67ea2dfdd15cd8e2863c78cc0a05095d">00325</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a70b05c3577437ee3a51c6b63859242c5">MICROPC_RTS</a> <span class="vhdllogic">9'd471</span>
|
| 354 |
12 |
alfik |
<a name="l00326"></a><a class="code" href="ao68000_8v.html#aef36b93556fcdd45b5cf7e6e25b84688">00326</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">MICROPC_MAIN_LOOP</a> <span class="vhdllogic">9'd53</span>
|
| 355 |
|
|
<a name="l00327"></a><a class="code" href="ao68000_8v.html#ae1aa62002fb7e0be2dc9d98d0361bc65">00327</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a02c5cdffb720a762c8790dbc86ab1a18">MICROPC_ADDA_SUBA</a> <span class="vhdllogic">9'd268</span>
|
| 356 |
13 |
alfik |
<a name="l00328"></a><a class="code" href="ao68000_8v.html#af3ccebcba20d1b81f55e4648bbc6434f">00328</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a258ae200cc2cbeccddff03ba18b66a27">MICROPC_MOVE_TO_CCR_MOVE_TO_SR</a> <span class="vhdllogic">9'd391</span>
|
| 357 |
|
|
<a name="l00329"></a><a class="code" href="ao68000_8v.html#aebd7c1774f2faac02d954c85ad1c20f8">00329</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9527c313aa58c219b35f23dcfcd52a3a">MICROPC_MOVE_FROM_SR</a> <span class="vhdllogic">9'd388</span>
|
| 358 |
12 |
alfik |
<a name="l00330"></a><a class="code" href="ao68000_8v.html#a345af680bab5b74ddd0f1dd1777c65bc">00330</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a785fdbd62d5c0da122ada9db07753b74">MICROPC_LOAD_EA_d8_PC_Xn</a> <span class="vhdllogic">9'd79</span>
|
| 359 |
|
|
<a name="l00331"></a><a class="code" href="ao68000_8v.html#a124c8b977fd09ccc4cc2f58fe0952a09">00331</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a80e45e303a1ebe180eeb15b47454e13f">MICROPC_TRAP_ENTRY</a> <span class="vhdllogic">9'd35</span>
|
| 360 |
|
|
<a name="l00332"></a><a class="code" href="ao68000_8v.html#ae0b37fb9a4e02142fbdb70219bbef6a0">00332</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2c70544d287306914c57f360847a1abd">MICROPC_PERFORM_EA_READ_memory</a> <span class="vhdllogic">9'd89</span>
|
| 361 |
13 |
alfik |
<a name="l00333"></a><a class="code" href="ao68000_8v.html#a42a277bcfd7ef54779fed4a28847581c">00333</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a7ac5bfe9a8556912db6217142a3bb772">MICROPC_RESET</a> <span class="vhdllogic">9'd485</span>
|
| 362 |
12 |
alfik |
<a name="l00334"></a><a class="code" href="ao68000_8v.html#a61290d0f3b951962b5a80b0b843ad86f">00334</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#acb05778c30ee2acc522c18f823a678ff">MICROPC_PERFORM_EA_WRITE_Dn</a> <span class="vhdllogic">9'd91</span>
|
| 363 |
|
|
<a name="l00335"></a><a class="code" href="ao68000_8v.html#af11ba1e2cd2e0bb279bf935b3defc503">00335</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a28f22a27673dd123f2ae53ac00c27c47">MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory</a> <span class="vhdllogic">9'd225</span>
|
| 364 |
|
|
<a name="l00336"></a><a class="code" href="ao68000_8v.html#ad35aeb7821957c9eb79f4e294d7b66cf">00336</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a38b3d0769f31c2931ccc92e00af94884">MICROPC_MOVEA</a> <span class="vhdllogic">9'd239</span>
|
| 365 |
13 |
alfik |
<a name="l00337"></a><a class="code" href="ao68000_8v.html#a9363a6d109adcf7d456074edf17dddca">00337</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a0c416458c758702471d503b0dbeab5d8">MICROPC_TST</a> <span class="vhdllogic">9'd344</span>
|
| 366 |
|
|
<a name="l00338"></a><a class="code" href="ao68000_8v.html#aef60ac808758c220d9e048b86a36e406">00338</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa2684e7883f516fe90229d1a02585c7c">MICROPC_BTST_register</a> <span class="vhdllogic">9'd326</span>
|
| 367 |
12 |
alfik |
<a name="l00339"></a><a class="code" href="ao68000_8v.html#afd3dcba15bfb7747ea152700b7395898">00339</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa80bb2f21742a46f59c3b8401c9209a3">MICROPC_LOAD_EA_d8_An_Xn</a> <span class="vhdllogic">9'd68</span>
|
| 368 |
|
|
<a name="l00340"></a><a class="code" href="ao68000_8v.html#a58a0825eeeb1bd2340a0b7c92e36c325">00340</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#abff7613e058d71dedd233ff63a37a724">MICROPC_MULS_MULU_DIVS_DIVU</a> <span class="vhdllogic">9'd290</span>
|
| 369 |
13 |
alfik |
<a name="l00341"></a><a class="code" href="ao68000_8v.html#ae2dc5340c2232f74f46c35a5afd48b33">00341</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a06f670a9b840bc7dda392686b0b53b41">MICROPC_MOVEQ</a> <span class="vhdllogic">9'd307</span>
|
| 370 |
12 |
alfik |
<a name="l00342"></a><a class="code" href="ao68000_8v.html#ab928eae11a81b6d124a6f3909ce7b9f1">00342</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a853a2713ed61bd3e53e70297f62b654d">MICROPC_CMPA</a> <span class="vhdllogic">9'd275</span>
|
| 371 |
|
|
<a name="l00343"></a><a class="code" href="ao68000_8v.html#a8a3ee084648ac92e056b83f949fa05d6">00343</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#adaa788877b96a4c0cf1c9500aefc505a">MICROPC_EOR</a> <span class="vhdllogic">9'd245</span>
|
| 372 |
|
|
<a name="l00344"></a><a class="code" href="ao68000_8v.html#adf4cfc5358aa9dd825abfc8f7681e09d">00344</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ade20a2ce9d926ed45a0c6e2d4c2bffad">MICROPC_LOAD_EA_xxx_W</a> <span class="vhdllogic">9'd72</span>
|
| 373 |
13 |
alfik |
<a name="l00345"></a><a class="code" href="ao68000_8v.html#aa888e8868f9a35fb790e242c1ca553de">00345</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a3d6a33ee86f4d37516a8afb60957b7ee">MICROPC_DBcc</a> <span class="vhdllogic">9'd374</span>
|
| 374 |
12 |
alfik |
<a name="l00346"></a><a class="code" href="ao68000_8v.html#abb08e3177e65a08caeb9a11f0e05f1b7">00346</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5027ce5e621b327a8116e4ca0af34e90">MICROPC_CMPI</a> <span class="vhdllogic">9'd184</span>
|
| 375 |
|
|
<a name="l00347"></a><a class="code" href="ao68000_8v.html#af37bba837c3168729bd2c32d11607584">00347</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac3601da82892ec91bbc958628eb6ed03">MICROPC_LOAD_EA_xxx_L</a> <span class="vhdllogic">9'd74</span>
|
| 376 |
|
|
<a name="l00348"></a><a class="code" href="ao68000_8v.html#a1b25d4948e6b56628513b57270c88553">00348</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a118f99a150352cf71a51d13156218674">MICROPC_CMPM</a> <span class="vhdllogic">9'd205</span>
|
| 377 |
13 |
alfik |
<a name="l00349"></a><a class="code" href="ao68000_8v.html#a10dd3138063247ca8f12244bf4fe7111">00349</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a999737a0b112cb8f4691dfc97278bc7e">MICROPC_MOVE_USP_to_USP</a> <span class="vhdllogic">9'd395</span>
|
| 378 |
|
|
<a name="l00350"></a><a class="code" href="ao68000_8v.html#a95038a8726dc69a3f11930e16a4f4f6a">00350</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af6f7102b5f4972ae11cad584ed87de14">MICROPC_ADDQ_SUBQ_not_An</a> <span class="vhdllogic">9'd348</span>
|
| 379 |
|
|
<a name="l00351"></a><a class="code" href="ao68000_8v.html#a56cb4246d3da79cb059495cd6ffea506">00351</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a52c9810463f7dc671e021a7217259c04">MICROPC_ULNK</a> <span class="vhdllogic">9'd419</span>
|
| 380 |
12 |
alfik |
<a name="l00352"></a><a class="code" href="ao68000_8v.html#a9a7a60a90fd7b7a8f511fa58a5474209">00352</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5a514be119075b3c3ab64dfa849f3d9c">MICROPC_EXG</a> <span class="vhdllogic">9'd197</span>
|
| 381 |
|
|
<a name="l00353"></a><a class="code" href="ao68000_8v.html#a07444504629b99d3da8ebbeee3a594cc">00353</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa3942210285e132e0151143eca9103b4">MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem</a> <span class="vhdllogic">9'd250</span>
|
| 382 |
13 |
alfik |
<a name="l00354"></a><a class="code" href="ao68000_8v.html#aa2f8f7655984ca496c0c15c281956ee1">00354</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae56342916e5e608a0fdd3a01a11688b0">MICROPC_Bcc_BRA</a> <span class="vhdllogic">9'd362</span>
|
| 383 |
12 |
alfik |
<a name="l00355"></a><a class="code" href="ao68000_8v.html#a73d600c76e7d7cc2e664417176239da3">00355</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8d6dcbc97994c642a8da0be0fecc257a">MICROPC_PERFORM_EA_READ_An</a> <span class="vhdllogic">9'd86</span>
|
| 384 |
|
|
<a name="l00356"></a><a class="code" href="ao68000_8v.html#ab803dd137dec243c16bb4bf026c05bf0">00356</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a7cb86509757fa3419fbc8980724bd315">MICROPC_LOAD_EA_d16_PC</a> <span class="vhdllogic">9'd76</span>
|
| 385 |
13 |
alfik |
<a name="l00357"></a><a class="code" href="ao68000_8v.html#a54e7164c6c76b71ecb76a41df5b05f79">00357</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a836e1069d2a67eabcd01a92fcc2672f0">MICROPC_NOP</a> <span class="vhdllogic">9'd479</span>
|
| 386 |
12 |
alfik |
<a name="l00358"></a><a class="code" href="ao68000_8v.html#a245572b10dd3bb9beeefb9cb8908daf1">00358</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#affd3d4c8fd7cf2cbd78ecd99397f768b">MICROPC_MOVEM_register_to_memory_predecrement</a> <span class="vhdllogic">9'd131</span>
|
| 387 |
13 |
alfik |
<a name="l00359"></a><a class="code" href="ao68000_8v.html#a8e01300271dc2002fc972bde66808baa">00359</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a76b52a43dac42903243a54b46c4bd839">MICROPC_RTE_RTR</a> <span class="vhdllogic">9'd459</span>
|
| 388 |
|
|
<a name="l00360"></a><a class="code" href="ao68000_8v.html#adf4b73792af505dd78bc1b3dac6d2b85">00360</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa106c5a18e8252dc2ced5ec2f77650d9">MICROPC_TRAP</a> <span class="vhdllogic">9'd480</span>
|
| 389 |
|
|
<a name="l00361"></a><a class="code" href="ao68000_8v.html#a0e2906a8e705c899033a9467393c2ff2">00361</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae9cec5ce342a7d51efda687c24f35ab1">MICROPC_ADDQ_SUBQ_An</a> <span class="vhdllogic">9'd351</span>
|
| 390 |
12 |
alfik |
<a name="l00362"></a><a class="code" href="ao68000_8v.html#a78ec3f3a42f7b33f121d0a293b64ab2a">00362</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a775df2459596100b0e801ad20c24322b">MICROPC_MOVEM_register_to_memory_control</a> <span class="vhdllogic">9'd147</span>
|
| 391 |
13 |
alfik |
<a name="l00363"></a><a class="code" href="ao68000_8v.html#a1031f61a9539b8a68133920d39ba9762">00363</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5ec24a82d3f383ac90da0ad8cc7bb0e3">MICROPC_BTST_immediate</a> <span class="vhdllogic">9'd315</span>
|
| 392 |
12 |
alfik |
<a name="l00364"></a><a class="code" href="ao68000_8v.html#a139e02a56567bb2b2d56c2d69902cbd0">00364</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6827fab6e4b333e82a1de52cf6020b7a">MICROPC_MOVEP_memory_to_register</a> <span class="vhdllogic">9'd98</span>
|
| 393 |
|
|
<a name="l00365"></a><a class="code" href="ao68000_8v.html#ab452d1e828902e03197249bbd0db027a">00365</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a20c5aa2df0d23f8bbdaccfca2bfed9f8">MICROPC_PERFORM_EA_WRITE_An</a> <span class="vhdllogic">9'd92</span>
|
| 394 |
|
|
<a name="l00366"></a><a class="code" href="ao68000_8v.html#a3c6368d941d09f1a7700910a2b5fca4a">00366</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a09d3064b3da754163f244a861ce4c758">MICROPC_CHK</a> <span class="vhdllogic">9'd281</span>
|
| 395 |
13 |
alfik |
<a name="l00367"></a><a class="code" href="ao68000_8v.html#aecb6a98c1c371a8139043c62665381e1">00367</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac09a1b9ae5783634cc9228354105fc94">MICROPC_Scc</a> <span class="vhdllogic">9'd355</span>
|
| 396 |
|
|
<a name="l00368"></a><a class="code" href="ao68000_8v.html#a08c56739b00c2c2ecae742fb5c665fe6">00368</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a088577482bc02135d9aa7a58c1d0ed05">MICROPC_JMP</a> <span class="vhdllogic">9'd442</span>
|
| 397 |
12 |
alfik |
<a name="l00369"></a><a class="code" href="ao68000_8v.html#aa4bbe36abf9c594596048d77663e9e22">00369</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2ce22f23bd95ba0ee7690a059448a357">MICROPC_PEA</a> <span class="vhdllogic">9'd168</span>
|
| 398 |
|
|
<a name="l00370"></a><a class="code" href="ao68000_8v.html#a70aec9dda79b3867e770a4d250732030">00370</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae4c00f630c944a41db777f7b51ee052d">MICROPC_SAVE_EA_minus_An</a> <span class="vhdllogic">9'd97</span>
|
| 399 |
|
|
<a name="l00371"></a><a class="code" href="ao68000_8v.html#a0ea81f72abfe95073d6662c81c769433">00371</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a1508cd79053f2766a7bd8b7932ffdf0c">MICROPC_ANDI_EORI_ORI_ADDI_SUBI</a> <span class="vhdllogic">9'd174</span>
|
| 400 |
13 |
alfik |
<a name="l00372"></a><a class="code" href="ao68000_8v.html#adba77b4e840a8ed2af693f17640a4e69">00372</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a89a5e8fafa2da702e7c00cb6fe7c2066">MICROPC_BCHG_BCLR_BSET_immediate</a> <span class="vhdllogic">9'd310</span>
|
| 401 |
12 |
alfik |
<a name="l00373"></a><a class="code" href="ao68000_8v.html#ae43352e5e1db083c51d51faf3344e0ed">00373</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a52c9fefea5280f08cf24bac6373252ac">MICROPC_LOAD_EA_An</a> <span class="vhdllogic">9'd62</span>
|
| 402 |
|
|
<a name="l00374"></a><a class="code" href="ao68000_8v.html#a9482347a8cd5a694b7fbf3e7ab8ba863">00374</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac2394d0cf1bffca610b4c8fb77881207">MICROPC_PERFORM_EA_READ_imm</a> <span class="vhdllogic">9'd87</span>
|
| 403 |
|
|
<a name="l00375"></a><a class="code" href="ao68000_8v.html#a9a2dc7c44d3211c4cd147781c7ae046e">00375</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#acdb63549759af21684d2fd6e3dad8eb7">MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn</a> <span class="vhdllogic">9'd255</span>
|
| 404 |
|
|
<a name="l00376"></a><a class="code" href="ao68000_8v.html#ac8568f114d824e091d8acf4a589544e7">00376</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aced982dae609932df5af323a07349a2b">MICROPC_LEA</a> <span class="vhdllogic">9'd162</span>
|
| 405 |
13 |
alfik |
<a name="l00377"></a><a class="code" href="ao68000_8v.html#afd036d9ad787d0f27973473c948ac4de">00377</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5038c753fc668ac678fe18251202305e">MICROPC_TRAPV</a> <span class="vhdllogic">9'd482</span>
|
| 406 |
|
|
<a name="l00378"></a><a class="code" href="ao68000_8v.html#a4ac35c6768582e13cf2cfbec564a15c4">00378</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af1b92ab55a321f316faf654b5d284caf">MICROPC_LINK</a> <span class="vhdllogic">9'd403</span>
|
| 407 |
12 |
alfik |
<a name="l00379"></a><a class="code" href="ao68000_8v.html#a181564080da192ca96a54014049a8a6e">00379</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a52a25a790c5779d1d9c5d4b807f6e9e6">MICROPC_ABCD_SBCD_ADDX_SUBX</a> <span class="vhdllogic">9'd189</span>
|
| 408 |
13 |
alfik |
<a name="l00380"></a><a class="code" href="ao68000_8v.html#a96e203e1004b880c901a4e8b2f2f2429">00380</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a5aff7e16fcd8e2f83c6a684fb62506b3">MICROPC_BCHG_BCLR_BSET_register</a> <span class="vhdllogic">9'd321</span>
|
| 409 |
12 |
alfik |
<a name="l00381"></a><a class="code" href="ao68000_8v.html#a37d9332e76b096caceffcf06a711bda1">00381</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ae21eb6fc6455af78326135e407ee17eb">MICROPC_PERFORM_EA_READ_Dn</a> <span class="vhdllogic">9'd85</span>
|
| 410 |
|
|
<a name="l00382"></a><a class="code" href="ao68000_8v.html#a19027f3b9a58050a6c54fb6220d8c969">00382</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a92f21025346f2b9baad5ee3ea27c8833">MICROPC_LOAD_EA_illegal_command</a> <span class="vhdllogic">9'd83</span>
|
| 411 |
|
|
<a name="l00383"></a><a class="code" href="ao68000_8v.html#a6029c9775c2a59720aa441c066c874a9">00383</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#af7581a9c9f99af85388e542ad881d71f">MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR</a> <span class="vhdllogic">9'd178</span>
|
| 412 |
|
|
<a name="l00384"></a><a class="code" href="ao68000_8v.html#adaf4d54600ebc6c16fb64a2889f128dd">00384</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a2d30784cb012710f55727108a9b62cf1">MICROPC_CMP</a> <span class="vhdllogic">9'd262</span>
|
| 413 |
13 |
alfik |
<a name="l00385"></a><a class="code" href="ao68000_8v.html#a1d7f386ed0662150d0f6f30b9127da0f">00385</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a65ca31e571d56e8b7e92ecadd58c94e1">MICROPC_SWAP_EXT</a> <span class="vhdllogic">9'd340</span>
|
| 414 |
|
|
<a name="l00386"></a><a class="code" href="ao68000_8v.html#af2f78dd082b87ed1f681dcfd552aa1e5">00386</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aa23e89f5c79e7df7ff8ecf19a41ae572">MICROPC_STOP</a> <span class="vhdllogic">9'd488</span>
|
| 415 |
12 |
alfik |
<a name="l00387"></a><a class="code" href="ao68000_8v.html#aa71f860296e95d302e5773af83ce85f6">00387</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ab8383cdb4a1df6d5f3296bb4244c7bab">MICROPC_PERFORM_EA_WRITE_memory</a> <span class="vhdllogic">9'd93</span>
|
| 416 |
13 |
alfik |
<a name="l00388"></a><a class="code" href="ao68000_8v.html#a73d1379623370b7ac490fc7d0efd3b31">00388</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a4a79b8f0394c470bd67ba6442fa12395">MICROPC_JSR</a> <span class="vhdllogic">9'd450</span>
|
| 417 |
12 |
alfik |
<a name="l00389"></a><a class="code" href="ao68000_8v.html#a51c49e5c7ae416b63ce044212b9ab4b7">00389</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a9b094e5044be3be8167a5b80bd274433">MICROPC_LOAD_EA_minus_An</a> <span class="vhdllogic">9'd63</span>
|
| 418 |
|
|
<a name="l00390"></a><a class="code" href="ao68000_8v.html#a4e6626ea369de1da9de2bf93f33278dd">00390</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a8a505b33f1c42b903dcb264862dda090">MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register</a> <span class="vhdllogic">9'd212</span>
|
| 419 |
|
|
<a name="l00391"></a><a class="code" href="ao68000_8v.html#a1fc7f893ce96f66f9cd2ab9b54f5b319">00391</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a02dc58bcc0412d6c93647a1304f20443">MICROPC_SAVE_EA_An_plus</a> <span class="vhdllogic">9'd95</span>
|
| 420 |
|
|
<a name="l00392"></a><a class="code" href="ao68000_8v.html#aa6cccbccacb5da82328bfdeeb3c5c6fa">00392</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#a6e06b607b9a1a157e3753943d2b015e1">MICROPC_LOAD_EA_d16_An</a> <span class="vhdllogic">9'd65</span>
|
| 421 |
|
|
<a name="l00393"></a><a class="code" href="ao68000_8v.html#a43d41ce59902030032a09041c949465e">00393</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#aafdd46a7740d48b02e781d3136f7ce1d">MICROPC_LOAD_EA_An_plus</a> <span class="vhdllogic">9'd62</span>
|
| 422 |
|
|
<a name="l00394"></a><a class="code" href="ao68000_8v.html#a357bfb655a15b7d0f5ed5c9f8cb0543a">00394</a> <span class="preprocessor">`define</span> <a class="code" href="ao68000_8v.html#ac2e6ac139e91da76695b3f953c994a0d">MICROPC_MOVEM_memory_to_register</a> <span class="vhdllogic">9'd116</span>
|
| 423 |
|
|
<a name="l00395"></a>00395 <span class="keyword">// MICROCODE - DO NOT EDIT ABOVE</span>
|
| 424 |
|
|
<a name="l00396"></a>00396
|
| 425 |
|
|
<a name="l00397"></a>00397 <span class="keyword">/***********************************************************************************************************************</span>
|
| 426 |
|
|
<a name="l00398"></a>00398 <span class="keyword"> ao68000 top level module</span>
|
| 427 |
|
|
<a name="l00399"></a>00399 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 428 |
|
|
<a name="l00400"></a>00400
|
| 429 |
|
|
<a name="l00401"></a>00401
|
| 430 |
|
|
<a name="l00405"></a><a class="code" href="classao68000.html">00405</a> <span class="vhdlkeyword">module</span> <a class="code" href="classao68000.html">ao68000</a> (
|
| 431 |
|
|
<a name="l00406"></a>00406 <span class="keyword">//****************** WISHBONE</span>
|
| 432 |
|
|
<a name="l00407"></a><a class="code" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">00407</a> <span class="vhdlkeyword">input</span> <a class="code" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a>,
|
| 433 |
|
|
<a name="l00408"></a><a class="code" href="classao68000.html#a5c903f753511ea2ec94145415549a148">00408</a> <span class="vhdlkeyword">input</span> <a class="code" href="classao68000.html#a5c903f753511ea2ec94145415549a148">reset_n</a>,
|
| 434 |
|
|
<a name="l00409"></a>00409
|
| 435 |
|
|
<a name="l00410"></a><a class="code" href="classao68000.html#a61843aa9b51ba23ec6c8c35892366559">00410</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#a61843aa9b51ba23ec6c8c35892366559">CYC_O</a>,
|
| 436 |
|
|
<a name="l00411"></a><a class="code" href="classao68000.html#a277895ba6004986cf490068945998fd0">00411</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classao68000.html#a277895ba6004986cf490068945998fd0">ADR_O</a>,
|
| 437 |
|
|
<a name="l00412"></a><a class="code" href="classao68000.html#a801fbb1ae4c2812332242ce5d746cf36">00412</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a801fbb1ae4c2812332242ce5d746cf36">DAT_O</a>,
|
| 438 |
|
|
<a name="l00413"></a><a class="code" href="classao68000.html#abffdd6f5cefb3be32b6db5bfc6b56442">00413</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#abffdd6f5cefb3be32b6db5bfc6b56442">DAT_I</a>,
|
| 439 |
|
|
<a name="l00414"></a><a class="code" href="classao68000.html#ae636550dd8481fd101623d0c665e894c">00414</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ae636550dd8481fd101623d0c665e894c">SEL_O</a>,
|
| 440 |
|
|
<a name="l00415"></a><a class="code" href="classao68000.html#a0e045730861ed97d585a192fcbbfd8a5">00415</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#a0e045730861ed97d585a192fcbbfd8a5">STB_O</a>,
|
| 441 |
|
|
<a name="l00416"></a><a class="code" href="classao68000.html#a6cd0052d2c68597331280fe500366be4">00416</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#a6cd0052d2c68597331280fe500366be4">WE_O</a>,
|
| 442 |
|
|
<a name="l00417"></a>00417
|
| 443 |
|
|
<a name="l00418"></a><a class="code" href="classao68000.html#a818ab80622c2364eb33814a5ef1f33ba">00418</a> <span class="vhdlkeyword">input</span> <a class="code" href="classao68000.html#a818ab80622c2364eb33814a5ef1f33ba">ACK_I</a>,
|
| 444 |
|
|
<a name="l00419"></a><a class="code" href="classao68000.html#a2a1a525f5a12c4e4a67bdf9fdf6df2be">00419</a> <span class="vhdlkeyword">input</span> <a class="code" href="classao68000.html#a2a1a525f5a12c4e4a67bdf9fdf6df2be">ERR_I</a>,
|
| 445 |
|
|
<a name="l00420"></a><a class="code" href="classao68000.html#af26604192b486b62964b9fada0bc6aff">00420</a> <span class="vhdlkeyword">input</span> <a class="code" href="classao68000.html#af26604192b486b62964b9fada0bc6aff">RTY_I</a>,
|
| 446 |
|
|
<a name="l00421"></a>00421
|
| 447 |
|
|
<a name="l00422"></a>00422 <span class="keyword">// TAG_TYPE: TGC_O</span>
|
| 448 |
|
|
<a name="l00423"></a><a class="code" href="classao68000.html#a067f51b370f090178fbe8248b48f50b0">00423</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#a067f51b370f090178fbe8248b48f50b0">SGL_O</a>,
|
| 449 |
|
|
<a name="l00424"></a><a class="code" href="classao68000.html#af57b8a8680a72f392a1f2af3ee2b61a9">00424</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#af57b8a8680a72f392a1f2af3ee2b61a9">BLK_O</a>,
|
| 450 |
|
|
<a name="l00425"></a><a class="code" href="classao68000.html#a951678555b50fc9229fe9b553c7b09d0">00425</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#a951678555b50fc9229fe9b553c7b09d0">RMW_O</a>,
|
| 451 |
|
|
<a name="l00426"></a>00426
|
| 452 |
|
|
<a name="l00427"></a>00427 <span class="keyword">// TAG_TYPE: TGA_O</span>
|
| 453 |
|
|
<a name="l00428"></a><a class="code" href="classao68000.html#a02037d382851d62248a83cbc35dd1529">00428</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a02037d382851d62248a83cbc35dd1529">CTI_O</a>,
|
| 454 |
|
|
<a name="l00429"></a><a class="code" href="classao68000.html#a08f46078858b7e8b6f2dfe2f6ec20c84">00429</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a08f46078858b7e8b6f2dfe2f6ec20c84">BTE_O</a>,
|
| 455 |
|
|
<a name="l00430"></a>00430
|
| 456 |
|
|
<a name="l00431"></a>00431 <span class="keyword">// TAG_TYPE: TGC_O</span>
|
| 457 |
|
|
<a name="l00432"></a><a class="code" href="classao68000.html#a4b66c96fdd706df792811882b6f9fa9b">00432</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a4b66c96fdd706df792811882b6f9fa9b">fc_o</a>,
|
| 458 |
|
|
<a name="l00433"></a>00433
|
| 459 |
|
|
<a name="l00434"></a>00434 <span class="keyword">//****************** OTHER</span>
|
| 460 |
|
|
<a name="l00435"></a>00435 <span class="keyword">/* interrupt acknowlege:</span>
|
| 461 |
|
|
<a name="l00436"></a>00436 <span class="keyword"> ACK_I: interrupt vector on DAT_I[7:0]</span>
|
| 462 |
|
|
<a name="l00437"></a>00437 <span class="keyword"> ERR_I: spurious interrupt</span>
|
| 463 |
|
|
<a name="l00438"></a>00438 <span class="keyword"> RTY_I: autovector</span>
|
| 464 |
|
|
<a name="l00439"></a>00439 <span class="keyword"> */</span>
|
| 465 |
|
|
<a name="l00440"></a><a class="code" href="classao68000.html#a1ff11e699c0192bb533209bd3cf9d5ba">00440</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a1ff11e699c0192bb533209bd3cf9d5ba">ipl_i</a>,
|
| 466 |
|
|
<a name="l00441"></a><a class="code" href="classao68000.html#a8246303a982cd24ff7dcc7b36c3038e2">00441</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#a8246303a982cd24ff7dcc7b36c3038e2">reset_o</a>,
|
| 467 |
|
|
<a name="l00442"></a><a class="code" href="classao68000.html#a0a90a371e379531c8e466799ff5c3d49">00442</a> <span class="vhdlkeyword">output</span> <a class="code" href="classao68000.html#a0a90a371e379531c8e466799ff5c3d49">blocked_o</a>
|
| 468 |
|
|
<a name="l00443"></a>00443 );
|
| 469 |
|
|
<a name="l00444"></a>00444
|
| 470 |
|
|
<a name="l00445"></a><a class="code" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">00445</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a>;
|
| 471 |
13 |
alfik |
<a name="l00446"></a><a class="code" href="classao68000.html#a7e653ecba236b212b87d66d9e46f3914">00446</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a7e653ecba236b212b87d66d9e46f3914">size</a>;
|
| 472 |
12 |
alfik |
<a name="l00447"></a><a class="code" href="classao68000.html#aaf40157e76d59864abf62ffe1c4f605d">00447</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#aaf40157e76d59864abf62ffe1c4f605d">address</a>;
|
| 473 |
|
|
<a name="l00448"></a><a class="code" href="classao68000.html#a3da831ef8ac6ec75b132d8d299115092">00448</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a3da831ef8ac6ec75b132d8d299115092">address_type</a>;
|
| 474 |
|
|
<a name="l00449"></a><a class="code" href="classao68000.html#a4d00737f890e3080a8915e23668c2fe0">00449</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a4d00737f890e3080a8915e23668c2fe0">read_modify_write_flag</a>;
|
| 475 |
|
|
<a name="l00450"></a><a class="code" href="classao68000.html#a341be6a91dd12d14293eaa53c7c254d2">00450</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a341be6a91dd12d14293eaa53c7c254d2">data_read</a>;
|
| 476 |
|
|
<a name="l00451"></a><a class="code" href="classao68000.html#ac7098386bafc8ad2194743a7ebbc3928">00451</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ac7098386bafc8ad2194743a7ebbc3928">data_write</a>;
|
| 477 |
|
|
<a name="l00452"></a><a class="code" href="classao68000.html#a5e28cd1d3701cc3d88dd0df22e697108">00452</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a5e28cd1d3701cc3d88dd0df22e697108">pc</a>;
|
| 478 |
|
|
<a name="l00453"></a><a class="code" href="classao68000.html#a7f60c5a54b85d16a5daa159e3f93f3a2">00453</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a7f60c5a54b85d16a5daa159e3f93f3a2">prefetch_ir_valid</a>;
|
| 479 |
|
|
<a name="l00454"></a><a class="code" href="classao68000.html#a3403e55545d6a49c4a4fa6f16cfe7126">00454</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">79</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a3403e55545d6a49c4a4fa6f16cfe7126">prefetch_ir</a>;
|
| 480 |
|
|
<a name="l00455"></a><a class="code" href="classao68000.html#a63cc96be1f84432ea4b755f14c9801bd">00455</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a63cc96be1f84432ea4b755f14c9801bd">do_reset</a>;
|
| 481 |
|
|
<a name="l00456"></a><a class="code" href="classao68000.html#aaa926f4340d9533fa404ed2121e01add">00456</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#aaa926f4340d9533fa404ed2121e01add">do_read</a>;
|
| 482 |
|
|
<a name="l00457"></a><a class="code" href="classao68000.html#a2fd644eba6903b45558dba81d759d60a">00457</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a2fd644eba6903b45558dba81d759d60a">do_write</a>;
|
| 483 |
|
|
<a name="l00458"></a><a class="code" href="classao68000.html#a017afb5ca18639747617179cd4b5b9af">00458</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a017afb5ca18639747617179cd4b5b9af">do_interrupt</a>;
|
| 484 |
|
|
<a name="l00459"></a><a class="code" href="classao68000.html#a8d22354dba9690de7ed1f40174e7fac5">00459</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a8d22354dba9690de7ed1f40174e7fac5">do_blocked</a>;
|
| 485 |
|
|
<a name="l00460"></a><a class="code" href="classao68000.html#aa9b27c579ff3359c8722f33ddc218606">00460</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#aa9b27c579ff3359c8722f33ddc218606">jmp_address_trap</a>;
|
| 486 |
|
|
<a name="l00461"></a><a class="code" href="classao68000.html#a68c0830ee44827649eeece60ccb007a4">00461</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a68c0830ee44827649eeece60ccb007a4">jmp_bus_trap</a>;
|
| 487 |
|
|
<a name="l00462"></a><a class="code" href="classao68000.html#adc838dee1d3e5fb81b69d9cd825e2078">00462</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#adc838dee1d3e5fb81b69d9cd825e2078">finished</a>;
|
| 488 |
|
|
<a name="l00463"></a><a class="code" href="classao68000.html#ab31d9d61b3fb7b8cf2d2588943144c51">00463</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ab31d9d61b3fb7b8cf2d2588943144c51">interrupt_trap</a>;
|
| 489 |
|
|
<a name="l00464"></a><a class="code" href="classao68000.html#a48c24a88040f4bfdc6df4f6d44c74f02">00464</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a48c24a88040f4bfdc6df4f6d44c74f02">interrupt_mask</a>;
|
| 490 |
|
|
<a name="l00465"></a><a class="code" href="classao68000.html#aa64aa2047c9823a2b6354f945b7a1e91">00465</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#aa64aa2047c9823a2b6354f945b7a1e91">rw_state</a>;
|
| 491 |
|
|
<a name="l00466"></a><a class="code" href="classao68000.html#ad29c33a9347a9dc0ad7e6a38a9674cea">00466</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ad29c33a9347a9dc0ad7e6a38a9674cea">fc_state</a>;
|
| 492 |
|
|
<a name="l00467"></a><a class="code" href="classao68000.html#a2d3d54c5eadf71c6a422a5e9c3c1c0f0">00467</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a2d3d54c5eadf71c6a422a5e9c3c1c0f0">decoder_trap</a>;
|
| 493 |
|
|
<a name="l00468"></a><a class="code" href="classao68000.html#a0c5ac49d1bd4f956a99173ba8d76824e">00468</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a0c5ac49d1bd4f956a99173ba8d76824e">usp</a>;
|
| 494 |
|
|
<a name="l00469"></a><a class="code" href="classao68000.html#a9fbb4d38edd465bd6e91c844baa3cc32">00469</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a9fbb4d38edd465bd6e91c844baa3cc32">Dn_output</a>;
|
| 495 |
|
|
<a name="l00470"></a><a class="code" href="classao68000.html#a38819ff180e465048ac34fe24c17db2e">00470</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a38819ff180e465048ac34fe24c17db2e">An_output</a>;
|
| 496 |
|
|
<a name="l00471"></a><a class="code" href="classao68000.html#ae78165f07b720df4d51db101effc08c5">00471</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ae78165f07b720df4d51db101effc08c5">result</a>;
|
| 497 |
|
|
<a name="l00472"></a><a class="code" href="classao68000.html#ac4bdc1d7a8df2e5b24f92e8c47b87d31">00472</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ac4bdc1d7a8df2e5b24f92e8c47b87d31">An_address</a>;
|
| 498 |
|
|
<a name="l00473"></a><a class="code" href="classao68000.html#a314e14c9d14faca666d7282e70aec69e">00473</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a314e14c9d14faca666d7282e70aec69e">An_input</a>;
|
| 499 |
|
|
<a name="l00474"></a><a class="code" href="classao68000.html#a8ce376b6468188948a66dd3090b82303">00474</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a8ce376b6468188948a66dd3090b82303">Dn_address</a>;
|
| 500 |
|
|
<a name="l00475"></a><a class="code" href="classao68000.html#a88e0be4d7a8d7765fd81d2c7ecec034c">00475</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a88e0be4d7a8d7765fd81d2c7ecec034c">ir</a>;
|
| 501 |
|
|
<a name="l00476"></a><a class="code" href="classao68000.html#a986f73747582af0c6343b171a856a806">00476</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a986f73747582af0c6343b171a856a806">decoder_micropc</a>;
|
| 502 |
13 |
alfik |
<a name="l00477"></a><a class="code" href="classao68000.html#ad3946c0f11e87469fdc3601692a49317">00477</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#ad3946c0f11e87469fdc3601692a49317">alu_signal</a>;
|
| 503 |
|
|
<a name="l00478"></a><a class="code" href="classao68000.html#abc430119a2bec27890ed3564ab72ffc3">00478</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#abc430119a2bec27890ed3564ab72ffc3">alu_mult_div_ready</a>;
|
| 504 |
|
|
<a name="l00479"></a><a class="code" href="classao68000.html#ae69df823449aa74618aaf7f853d3f11e">00479</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ae69df823449aa74618aaf7f853d3f11e">load_ea</a>;
|
| 505 |
|
|
<a name="l00480"></a><a class="code" href="classao68000.html#a58cd92d0477a981c2008bd90817becc9">00480</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a58cd92d0477a981c2008bd90817becc9">perform_ea_read</a>;
|
| 506 |
|
|
<a name="l00481"></a><a class="code" href="classao68000.html#ab422cb8cd23d482adfd2aa9caa9761c5">00481</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ab422cb8cd23d482adfd2aa9caa9761c5">perform_ea_write</a>;
|
| 507 |
|
|
<a name="l00482"></a><a class="code" href="classao68000.html#a09f55857356fd236f8350946112ea688">00482</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a09f55857356fd236f8350946112ea688">save_ea</a>;
|
| 508 |
|
|
<a name="l00483"></a><a class="code" href="classao68000.html#a3cb489d55f80adb5d4cafd9f9f4679be">00483</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a3cb489d55f80adb5d4cafd9f9f4679be">trace_flag</a>;
|
| 509 |
|
|
<a name="l00484"></a><a class="code" href="classao68000.html#abf4182c32ee4bc817caa8b5d6772ab7a">00484</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#abf4182c32ee4bc817caa8b5d6772ab7a">group_0_flag</a>;
|
| 510 |
|
|
<a name="l00485"></a><a class="code" href="classao68000.html#aa7e62464a0cd6d4d476939a4ddcb7cb0">00485</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#aa7e62464a0cd6d4d476939a4ddcb7cb0">stop_flag</a>;
|
| 511 |
|
|
<a name="l00486"></a><a class="code" href="classao68000.html#ace8aff52b8f30690429b9936f07c97a0">00486</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ace8aff52b8f30690429b9936f07c97a0">micro_pc</a>;
|
| 512 |
|
|
<a name="l00487"></a><a class="code" href="classao68000.html#a2ce08034a6163ba919bc8671ab418925">00487</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a2ce08034a6163ba919bc8671ab418925">operand1</a>;
|
| 513 |
|
|
<a name="l00488"></a><a class="code" href="classao68000.html#abba9faff9213088a72a8ec33a43e7b88">00488</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#abba9faff9213088a72a8ec33a43e7b88">operand2</a>;
|
| 514 |
|
|
<a name="l00489"></a><a class="code" href="classao68000.html#a01988743194f85b63333d073c7fe68f7">00489</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a01988743194f85b63333d073c7fe68f7">movem_loop</a>;
|
| 515 |
|
|
<a name="l00490"></a><a class="code" href="classao68000.html#a280d638b17d688517b637ad90d6df376">00490</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a280d638b17d688517b637ad90d6df376">movem_reg</a>;
|
| 516 |
|
|
<a name="l00491"></a><a class="code" href="classao68000.html#a83b2f86d57930b08a8db6e9b8410837f">00491</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#a30446f4f602b6185a7ed25e5aa8e470e">condition</a>;
|
| 517 |
|
|
<a name="l00492"></a><a class="code" href="classao68000.html#ae4e21fd281172d5e74e527236b1519f2">00492</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">87</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ae4e21fd281172d5e74e527236b1519f2">micro_data</a>;
|
| 518 |
|
|
<a name="l00493"></a><a class="code" href="classao68000.html#ae552c0d79d4e728a385243f7339c4090">00493</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#ae552c0d79d4e728a385243f7339c4090">fault_address_state</a>;
|
| 519 |
|
|
<a name="l00494"></a><a class="code" href="classao68000.html#a71903694d8425f743a2f6e753a7e2e89">00494</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a71903694d8425f743a2f6e753a7e2e89">pc_change</a>;
|
| 520 |
|
|
<a name="l00495"></a><a class="code" href="classao68000.html#aeb25637923460dddbd88804a217e5ce5">00495</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classao68000.html#aeb25637923460dddbd88804a217e5ce5">prefetch_ir_valid_32</a>;
|
| 521 |
|
|
<a name="l00496"></a><a class="code" href="classao68000.html#a7e1ce5d495efd402ecaac1127691254b">00496</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a7e1ce5d495efd402ecaac1127691254b">ea_type</a>;
|
| 522 |
|
|
<a name="l00497"></a><a class="code" href="classao68000.html#abe4582e421ebfc379fc3e26b925783fa">00497</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#abe4582e421ebfc379fc3e26b925783fa">ea_mod</a>;
|
| 523 |
|
|
<a name="l00498"></a><a class="code" href="classao68000.html#a127110f55f7a36e476471f8860abc860">00498</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classao68000.html#a127110f55f7a36e476471f8860abc860">ea_reg</a>;
|
| 524 |
|
|
<a name="l00499"></a>00499
|
| 525 |
|
|
<a name="l00500"></a><a class="code" href="classao68000.html#a2c34e1b84d9fe30c49c5c814be3dc392">00500</a> <a class="code" href="classao68000.html#a2c34e1b84d9fe30c49c5c814be3dc392">bus_control</a> <span class="vhdlchar">bus_control_m</span>(
|
| 526 |
|
|
<a name="l00501"></a>00501 .<a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">ao68000</a> (<a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">ao68000</a>),
|
| 527 |
|
|
<a name="l00502"></a>00502 .<a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">ao68000</a> (<a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">ao68000</a>),
|
| 528 |
|
|
<a name="l00503"></a>00503 .<a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">ao68000</a> (<a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">ao68000</a>),
|
| 529 |
|
|
<a name="l00504"></a>00504 .<a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ao68000</a> (<a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ao68000</a>),
|
| 530 |
|
|
<a name="l00505"></a>00505 .<a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">ao68000</a> (<a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">ao68000</a>),
|
| 531 |
|
|
<a name="l00506"></a>00506 .<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">ao68000</a> (<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">ao68000</a>),
|
| 532 |
|
|
<a name="l00507"></a>00507 .<a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">ao68000</a> (<a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">ao68000</a>),
|
| 533 |
|
|
<a name="l00508"></a>00508 .<a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">ao68000</a> (<a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">ao68000</a>),
|
| 534 |
|
|
<a name="l00509"></a>00509 .<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">ao68000</a> (<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">ao68000</a>),
|
| 535 |
|
|
<a name="l00510"></a>00510 .<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ao68000</a> (<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ao68000</a>),
|
| 536 |
|
|
<a name="l00511"></a>00511 .<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ao68000</a> (<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ao68000</a>),
|
| 537 |
|
|
<a name="l00512"></a>00512 .<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">ao68000</a> (<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">ao68000</a>),
|
| 538 |
|
|
<a name="l00513"></a>00513 .<a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">ao68000</a> (<a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">ao68000</a>),
|
| 539 |
|
|
<a name="l00514"></a>00514 .<a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">ao68000</a> (<a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">ao68000</a>),
|
| 540 |
|
|
<a name="l00515"></a>00515 .<a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">ao68000</a> (<a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">ao68000</a>),
|
| 541 |
|
|
<a name="l00516"></a>00516 .<a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">ao68000</a> (<a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">ao68000</a>),
|
| 542 |
|
|
<a name="l00517"></a>00517 .<a class="code" href="classbus__control.html#ada8208aac77c8a5b2d937d050a85ded6">ao68000</a> (<a class="code" href="classbus__control.html#ada8208aac77c8a5b2d937d050a85ded6">ao68000</a>),
|
| 543 |
|
|
<a name="l00518"></a>00518 .<a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">ao68000</a> (<a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">ao68000</a>),
|
| 544 |
|
|
<a name="l00519"></a>00519 .<a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ao68000</a> (<a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ao68000</a>),
|
| 545 |
|
|
<a name="l00520"></a>00520 .<a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">ao68000</a> (<a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">ao68000</a>),
|
| 546 |
|
|
<a name="l00521"></a>00521 .<a class="code" href="classao68000.html#a0a90a371e379531c8e466799ff5c3d49">blocked_o</a> (<a class="code" href="classao68000.html#a0a90a371e379531c8e466799ff5c3d49">blocked_o</a>),
|
| 547 |
|
|
<a name="l00522"></a>00522
|
| 548 |
|
|
<a name="l00523"></a>00523 .<span class="vhdlchar">supervisor_i</span> (<a class="code" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a>[<span class="vhdllogic">13</span>]),
|
| 549 |
|
|
<a name="l00524"></a>00524 .<span class="vhdlchar">ipm_i</span> (<a class="code" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>]),
|
| 550 |
|
|
<a name="l00525"></a>00525 .<span class="vhdlchar">size_i</span> (<a class="code" href="classao68000.html#a7e653ecba236b212b87d66d9e46f3914">size</a>),
|
| 551 |
|
|
<a name="l00526"></a>00526 .<span class="vhdlchar">address_i</span> (<a class="code" href="classao68000.html#aaf40157e76d59864abf62ffe1c4f605d">address</a>),
|
| 552 |
|
|
<a name="l00527"></a>00527 .<span class="vhdlchar">address_type_i</span> (<a class="code" href="classao68000.html#a3da831ef8ac6ec75b132d8d299115092">address_type</a>),
|
| 553 |
|
|
<a name="l00528"></a>00528 .<span class="vhdlchar">read_modify_write_i</span> (<a class="code" href="classao68000.html#a4d00737f890e3080a8915e23668c2fe0">read_modify_write_flag</a>),
|
| 554 |
|
|
<a name="l00529"></a>00529 .<span class="vhdlchar">data_write_i</span> (<a class="code" href="classao68000.html#ac7098386bafc8ad2194743a7ebbc3928">data_write</a>),
|
| 555 |
|
|
<a name="l00530"></a>00530 .<span class="vhdlchar">data_read_o</span> (<a class="code" href="classao68000.html#a341be6a91dd12d14293eaa53c7c254d2">data_read</a>),
|
| 556 |
|
|
<a name="l00531"></a>00531 .<span class="vhdlchar">pc_i</span> (<a class="code" href="classao68000.html#a5e28cd1d3701cc3d88dd0df22e697108">pc</a>),
|
| 557 |
|
|
<a name="l00532"></a>00532 .<span class="vhdlchar">pc_change_i</span> (<a class="code" href="classao68000.html#a71903694d8425f743a2f6e753a7e2e89">pc_change</a>),
|
| 558 |
|
|
<a name="l00533"></a>00533 .<span class="vhdlchar">prefetch_ir_o</span> (<a class="code" href="classao68000.html#a3403e55545d6a49c4a4fa6f16cfe7126">prefetch_ir</a>),
|
| 559 |
|
|
<a name="l00534"></a>00534 .<span class="vhdlchar">prefetch_ir_valid_32_o</span> (<a class="code" href="classao68000.html#aeb25637923460dddbd88804a217e5ce5">prefetch_ir_valid_32</a>),
|
| 560 |
|
|
<a name="l00535"></a>00535 .<span class="vhdlchar">prefetch_ir_valid_o</span> (<a class="code" href="classao68000.html#a7f60c5a54b85d16a5daa159e3f93f3a2">prefetch_ir_valid</a>),
|
| 561 |
|
|
<a name="l00536"></a>00536 .<span class="vhdlchar">prefetch_ir_valid_80_o</span> (),
|
| 562 |
|
|
<a name="l00537"></a>00537 .<span class="vhdlchar">do_reset_i</span> (<a class="code" href="classao68000.html#a63cc96be1f84432ea4b755f14c9801bd">do_reset</a>),
|
| 563 |
|
|
<a name="l00538"></a>00538 .<span class="vhdlchar">do_blocked_i</span> (<a class="code" href="classao68000.html#a8d22354dba9690de7ed1f40174e7fac5">do_blocked</a>),
|
| 564 |
|
|
<a name="l00539"></a>00539 .<span class="vhdlchar">do_read_i</span> (<a class="code" href="classao68000.html#aaa926f4340d9533fa404ed2121e01add">do_read</a>),
|
| 565 |
|
|
<a name="l00540"></a>00540 .<span class="vhdlchar">do_write_i</span> (<a class="code" href="classao68000.html#a2fd644eba6903b45558dba81d759d60a">do_write</a>),
|
| 566 |
|
|
<a name="l00541"></a>00541 .<span class="vhdlchar">do_interrupt_i</span> (<a class="code" href="classao68000.html#a017afb5ca18639747617179cd4b5b9af">do_interrupt</a>),
|
| 567 |
|
|
<a name="l00542"></a>00542 .<span class="vhdlchar">jmp_address_trap_o</span> (<a class="code" href="classao68000.html#aa9b27c579ff3359c8722f33ddc218606">jmp_address_trap</a>),
|
| 568 |
|
|
<a name="l00543"></a>00543 .<span class="vhdlchar">jmp_bus_trap_o</span> (<a class="code" href="classao68000.html#a68c0830ee44827649eeece60ccb007a4">jmp_bus_trap</a>),
|
| 569 |
|
|
<a name="l00544"></a>00544 .<span class="vhdlchar">finished_o</span> (<a class="code" href="classao68000.html#adc838dee1d3e5fb81b69d9cd825e2078">finished</a>),
|
| 570 |
|
|
<a name="l00545"></a>00545 .<span class="vhdlchar">interrupt_trap_o</span> (<a class="code" href="classao68000.html#ab31d9d61b3fb7b8cf2d2588943144c51">interrupt_trap</a>),
|
| 571 |
|
|
<a name="l00546"></a>00546 .<span class="vhdlchar">interrupt_mask_o</span> (<a class="code" href="classao68000.html#a48c24a88040f4bfdc6df4f6d44c74f02">interrupt_mask</a>),
|
| 572 |
|
|
<a name="l00547"></a>00547 .<span class="vhdlchar">rw_state_o</span> (<a class="code" href="classao68000.html#aa64aa2047c9823a2b6354f945b7a1e91">rw_state</a>),
|
| 573 |
|
|
<a name="l00548"></a>00548 .<span class="vhdlchar">fc_state_o</span> (<a class="code" href="classao68000.html#ad29c33a9347a9dc0ad7e6a38a9674cea">fc_state</a>),
|
| 574 |
|
|
<a name="l00549"></a>00549 .<span class="vhdlchar">fault_address_state_o</span> (<a class="code" href="classao68000.html#ae552c0d79d4e728a385243f7339c4090">fault_address_state</a>)
|
| 575 |
|
|
<a name="l00550"></a>00550 );
|
| 576 |
|
|
<a name="l00551"></a>00551
|
| 577 |
|
|
<a name="l00552"></a><a class="code" href="classao68000.html#ad82deea9ab15d2e02890df123ad51fd9">00552</a> <a class="code" href="classao68000.html#ad82deea9ab15d2e02890df123ad51fd9">registers</a> <span class="vhdlchar">registers_m</span>(
|
| 578 |
|
|
<a name="l00553"></a>00553 .<a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">ao68000</a> (<a class="code" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a>),
|
| 579 |
|
|
<a name="l00554"></a>00554 .<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">ao68000</a> (<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">ao68000</a>),
|
| 580 |
|
|
<a name="l00555"></a>00555 .<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">ao68000</a> (<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">ao68000</a>),
|
| 581 |
|
|
<a name="l00556"></a>00556 .<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">ao68000</a> (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">ao68000</a>),
|
| 582 |
|
|
<a name="l00557"></a>00557 .<a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">ao68000</a> (<a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">ao68000</a>),
|
| 583 |
|
|
<a name="l00558"></a>00558 .<a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">ao68000</a> (<a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">ao68000</a>),
|
| 584 |
|
|
<a name="l00559"></a>00559 .<a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">ao68000</a> (<a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">ao68000</a>),
|
| 585 |
|
|
<a name="l00560"></a>00560 .<a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">ao68000</a> (<a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">ao68000</a>),
|
| 586 |
|
|
<a name="l00561"></a>00561 .<a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">ao68000</a> (<a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">ao68000</a>),
|
| 587 |
|
|
<a name="l00562"></a>00562 .<a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">ao68000</a> (<a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">ao68000</a>),
|
| 588 |
|
|
<a name="l00563"></a>00563 .<a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">ao68000</a> (<a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">ao68000</a>),
|
| 589 |
|
|
<a name="l00564"></a>00564 .<a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">ao68000</a> (<a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">ao68000</a>),
|
| 590 |
|
|
<a name="l00565"></a>00565 .<a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">ao68000</a> (<a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">ao68000</a>),
|
| 591 |
|
|
<a name="l00566"></a>00566 .<a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">ao68000</a> (<a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">ao68000</a>),
|
| 592 |
|
|
<a name="l00567"></a>00567 .<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">ao68000</a> (<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">ao68000</a>),
|
| 593 |
|
|
<a name="l00568"></a>00568 .<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">ao68000</a> (<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">ao68000</a>),
|
| 594 |
|
|
<a name="l00569"></a>00569
|
| 595 |
|
|
<a name="l00570"></a>00570 .<a class="code" href="classregisters.html#a73560eea6b21f10073a1131e3cffa801">ao68000</a> (<a class="code" href="classregisters.html#a73560eea6b21f10073a1131e3cffa801">ao68000</a>),
|
| 596 |
|
|
<a name="l00571"></a>00571
|
| 597 |
|
|
<a name="l00572"></a>00572 .<a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ao68000</a> (<a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ao68000</a>),
|
| 598 |
|
|
<a name="l00573"></a>00573 .<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ao68000</a> (<a class="code" href="ao68000_8v.html#a3a14e27ef3dcc344f66e5eb0aa93d38d">`MICRO_DATA_ea_reg</a><span class="vhdlchar"></span>),
|
| 599 |
|
|
<a name="l00574"></a>00574 .<a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ao68000</a> (<a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ao68000</a>),
|
| 600 |
|
|
<a name="l00575"></a>00575 .<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ao68000</a> (<a class="code" href="ao68000_8v.html#aa691c194246c2ac4def5609ba8963326">`MICRO_DATA_ea_mod</a><span class="vhdlchar"></span>),
|
| 601 |
|
|
<a name="l00576"></a>00576 .<a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ao68000</a> (<a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ao68000</a>),
|
| 602 |
|
|
<a name="l00577"></a>00577 .<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ao68000</a> (<a class="code" href="ao68000_8v.html#ae45014e01523ad88c7b7bd74cdb1b8db">`MICRO_DATA_ea_type</a><span class="vhdlchar"></span>),
|
| 603 |
|
|
<a name="l00578"></a>00578 .<a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">ao68000</a> (<a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">ao68000</a>),
|
| 604 |
|
|
<a name="l00579"></a>00579 .<span class="vhdlchar">operand1_control</span> (<a class="code" href="ao68000_8v.html#a80f755d97ef46590665dc161a3de3f60">`MICRO_DATA_op1</a><span class="vhdlchar"></span>),
|
| 605 |
|
|
<a name="l00580"></a>00580 .<a class="code" href="classao68000.html#abba9faff9213088a72a8ec33a43e7b88">operand2</a> (<a class="code" href="classao68000.html#abba9faff9213088a72a8ec33a43e7b88">operand2</a>),
|
| 606 |
|
|
<a name="l00581"></a>00581 .<span class="vhdlchar">operand2_control</span> (<a class="code" href="ao68000_8v.html#ab1641cfecafe6ff147522b68bd7f9c0d">`MICRO_DATA_op2</a><span class="vhdlchar"></span>),
|
| 607 |
|
|
<a name="l00582"></a>00582 .<a class="code" href="classao68000.html#aaf40157e76d59864abf62ffe1c4f605d">address</a> (<a class="code" href="classao68000.html#aaf40157e76d59864abf62ffe1c4f605d">address</a>),
|
| 608 |
|
|
<a name="l00583"></a>00583 .<a class="code" href="classao68000.html#a3da831ef8ac6ec75b132d8d299115092">address_type</a> (<a class="code" href="classao68000.html#a3da831ef8ac6ec75b132d8d299115092">address_type</a>),
|
| 609 |
|
|
<a name="l00584"></a>00584 .<span class="vhdlchar">address_control</span> (<a class="code" href="ao68000_8v.html#a600647e8ee417a6f81b00e53f101af5f">`MICRO_DATA_address</a><span class="vhdlchar"></span>),
|
| 610 |
|
|
<a name="l00585"></a>00585 .<a class="code" href="classao68000.html#a7e653ecba236b212b87d66d9e46f3914">size</a> (<a class="code" href="classao68000.html#a7e653ecba236b212b87d66d9e46f3914">size</a>),
|
| 611 |
|
|
<a name="l00586"></a>00586 .<span class="vhdlchar">size_control</span> (<a class="code" href="ao68000_8v.html#a73de1704db2fb003c3a2da4b3f1667de">`MICRO_DATA_size</a><span class="vhdlchar"></span>),
|
| 612 |
|
|
<a name="l00587"></a>00587 .<span class="vhdlchar">movem_modreg</span> (),
|
| 613 |
|
|
<a name="l00588"></a>00588 .<span class="vhdlchar">movem_modreg_control</span> (<a class="code" href="ao68000_8v.html#a73831c7c30f75ec6e263ce47f1a3fb64">`MICRO_DATA_movem_modreg</a><span class="vhdlchar"></span>),
|
| 614 |
|
|
<a name="l00589"></a>00589 .<a class="code" href="classao68000.html#a01988743194f85b63333d073c7fe68f7">movem_loop</a> (<a class="code" href="classao68000.html#a01988743194f85b63333d073c7fe68f7">movem_loop</a>),
|
| 615 |
|
|
<a name="l00590"></a>00590 .<span class="vhdlchar">movem_loop_control</span> (<a class="code" href="ao68000_8v.html#a93b7332d93eddbed779bba21295794f3">`MICRO_DATA_movem_loop</a><span class="vhdlchar"></span>),
|
| 616 |
|
|
<a name="l00591"></a>00591 .<a class="code" href="classao68000.html#a280d638b17d688517b637ad90d6df376">movem_reg</a> (<a class="code" href="classao68000.html#a280d638b17d688517b637ad90d6df376">movem_reg</a>),
|
| 617 |
|
|
<a name="l00592"></a>00592 .<span class="vhdlchar">movem_reg_control</span> (<a class="code" href="ao68000_8v.html#a5246b6d3ea1d05aa2d34597666a8da31">`MICRO_DATA_movem_reg</a><span class="vhdlchar"></span>),
|
| 618 |
|
|
<a name="l00593"></a>00593 .<a class="code" href="classao68000.html#a88e0be4d7a8d7765fd81d2c7ecec034c">ir</a> (<a class="code" href="classao68000.html#a88e0be4d7a8d7765fd81d2c7ecec034c">ir</a>),
|
| 619 |
|
|
<a name="l00594"></a>00594 .<span class="vhdlchar">ir_control</span> (<a class="code" href="ao68000_8v.html#a15830df6bfc267949eaeb9c862ec021a">`MICRO_DATA_ir</a><span class="vhdlchar"></span>),
|
| 620 |
|
|
<a name="l00595"></a>00595 .<a class="code" href="classao68000.html#a5e28cd1d3701cc3d88dd0df22e697108">pc</a> (<a class="code" href="classao68000.html#a5e28cd1d3701cc3d88dd0df22e697108">pc</a>),
|
| 621 |
|
|
<a name="l00596"></a>00596 .<span class="vhdlchar">pc_control</span> (<a class="code" href="ao68000_8v.html#a35a9274fdd4fa537efdb15f0b0b787e6">`MICRO_DATA_pc</a><span class="vhdlchar"></span>),
|
| 622 |
|
|
<a name="l00597"></a>00597 .<span class="vhdlchar">trap</span> (),
|
| 623 |
|
|
<a name="l00598"></a>00598 .<span class="vhdlchar">trap_control</span> (<a class="code" href="ao68000_8v.html#ac4878c2a7cf765d443c1c9da238b5ac9">`MICRO_DATA_trap</a><span class="vhdlchar"></span>),
|
| 624 |
|
|
<a name="l00599"></a>00599 .<span class="vhdlchar">offset</span> (),
|
| 625 |
|
|
<a name="l00600"></a>00600 .<span class="vhdlchar">offset_control</span> (<a class="code" href="ao68000_8v.html#a4deaea8bc3d376dac501f3a314f1490c">`MICRO_DATA_offset</a><span class="vhdlchar"></span>),
|
| 626 |
|
|
<a name="l00601"></a>00601 .<span class="vhdlchar">index</span> (),
|
| 627 |
|
|
<a name="l00602"></a>00602 .<span class="vhdlchar">index_control</span> (<a class="code" href="ao68000_8v.html#ad722ce87f573d9c6e1010e5a87005383">`MICRO_DATA_index</a><span class="vhdlchar"></span>),
|
| 628 |
|
|
<a name="l00603"></a>00603 .<a class="code" href="classao68000.html#aa7e62464a0cd6d4d476939a4ddcb7cb0">stop_flag</a> (<a class="code" href="classao68000.html#aa7e62464a0cd6d4d476939a4ddcb7cb0">stop_flag</a>),
|
| 629 |
|
|
<a name="l00604"></a>00604 .<span class="vhdlchar">stop_flag_control</span> (<a class="code" href="ao68000_8v.html#a5e820e2a23919cb4005a8cc9651c26c0">`MICRO_DATA_stop_flag</a><span class="vhdlchar"></span>),
|
| 630 |
|
|
<a name="l00605"></a>00605 .<a class="code" href="classao68000.html#a3cb489d55f80adb5d4cafd9f9f4679be">trace_flag</a> (<a class="code" href="classao68000.html#a3cb489d55f80adb5d4cafd9f9f4679be">trace_flag</a>),
|
| 631 |
|
|
<a name="l00606"></a>00606 .<span class="vhdlchar">trace_flag_control</span> (<a class="code" href="ao68000_8v.html#aa913e0fe5ccffe6e2d7e91d43f39f139">`MICRO_DATA_trace_flag</a><span class="vhdlchar"></span>),
|
| 632 |
|
|
<a name="l00607"></a>00607 .<a class="code" href="classao68000.html#abf4182c32ee4bc817caa8b5d6772ab7a">group_0_flag</a> (<a class="code" href="classao68000.html#abf4182c32ee4bc817caa8b5d6772ab7a">group_0_flag</a>),
|
| 633 |
|
|
<a name="l00608"></a>00608 .<span class="vhdlchar">group_0_flag_control</span> (<a class="code" href="ao68000_8v.html#a595e837c71d69c5a4d7c4a3c9d64ffb0">`MICRO_DATA_group_0_flag</a><span class="vhdlchar"></span>),
|
| 634 |
|
|
<a name="l00609"></a>00609 .<span class="vhdlchar">instruction_flag</span> (),
|
| 635 |
|
|
<a name="l00610"></a>00610 .<span class="vhdlchar">instruction_flag_control</span> (<a class="code" href="ao68000_8v.html#a188c9ee8d0adc5ec2fb732fdece9ea31">`MICRO_DATA_instruction_flag</a><span class="vhdlchar"></span>),
|
| 636 |
|
|
<a name="l00611"></a>00611 .<a class="code" href="classao68000.html#a4d00737f890e3080a8915e23668c2fe0">read_modify_write_flag</a> (<a class="code" href="classao68000.html#a4d00737f890e3080a8915e23668c2fe0">read_modify_write_flag</a>),
|
| 637 |
|
|
<a name="l00612"></a>00612 .<span class="vhdlchar">read_modify_write_flag_control</span> (<a class="code" href="ao68000_8v.html#ae152374d2c661e9bfcb222888087b18f">`MICRO_DATA_read_modify_write_flag</a><span class="vhdlchar"></span>),
|
| 638 |
|
|
<a name="l00613"></a>00613 .<span class="vhdlchar">do_reset_flag</span> (<a class="code" href="classao68000.html#a63cc96be1f84432ea4b755f14c9801bd">do_reset</a>),
|
| 639 |
|
|
<a name="l00614"></a>00614 .<span class="vhdlchar">do_reset_flag_control</span> (<a class="code" href="ao68000_8v.html#a05f6c84753b5b54fe61fe36a740b739d">`MICRO_DATA_do_reset_flag</a><span class="vhdlchar"></span>),
|
| 640 |
|
|
<a name="l00615"></a>00615 .<span class="vhdlchar">do_interrupt_flag</span> (<a class="code" href="classao68000.html#a017afb5ca18639747617179cd4b5b9af">do_interrupt</a>),
|
| 641 |
|
|
<a name="l00616"></a>00616 .<span class="vhdlchar">do_interrupt_flag_control</span> (<a class="code" href="ao68000_8v.html#a989be17e3392ddf7c87fcf41a9c1576b">`MICRO_DATA_do_interrupt_flag</a><span class="vhdlchar"></span>),
|
| 642 |
|
|
<a name="l00617"></a>00617 .<span class="vhdlchar">do_read_flag</span> (<a class="code" href="classao68000.html#aaa926f4340d9533fa404ed2121e01add">do_read</a>),
|
| 643 |
|
|
<a name="l00618"></a>00618 .<span class="vhdlchar">do_read_flag_control</span> (<a class="code" href="ao68000_8v.html#a3935f3fc6e20767fdeee079bdb08648f">`MICRO_DATA_do_read_flag</a><span class="vhdlchar"></span>),
|
| 644 |
|
|
<a name="l00619"></a>00619 .<span class="vhdlchar">do_write_flag</span> (<a class="code" href="classao68000.html#a2fd644eba6903b45558dba81d759d60a">do_write</a>),
|
| 645 |
|
|
<a name="l00620"></a>00620 .<span class="vhdlchar">do_write_flag_control</span> (<a class="code" href="ao68000_8v.html#a42e2926c262bd037f32951c89a51067e">`MICRO_DATA_do_write_flag</a><span class="vhdlchar"></span>),
|
| 646 |
|
|
<a name="l00621"></a>00621 .<span class="vhdlchar">do_blocked_flag</span> (<a class="code" href="classao68000.html#a8d22354dba9690de7ed1f40174e7fac5">do_blocked</a>),
|
| 647 |
|
|
<a name="l00622"></a>00622 .<span class="vhdlchar">do_blocked_flag_control</span> (<a class="code" href="ao68000_8v.html#adf7ac746fc276a0c3083d2606df75af4">`MICRO_DATA_do_blocked_flag</a><span class="vhdlchar"></span>),
|
| 648 |
|
|
<a name="l00623"></a>00623 .<a class="code" href="classao68000.html#ac7098386bafc8ad2194743a7ebbc3928">data_write</a> (<a class="code" href="classao68000.html#ac7098386bafc8ad2194743a7ebbc3928">data_write</a>),
|
| 649 |
|
|
<a name="l00624"></a>00624 .<span class="vhdlchar">data_write_control</span> (<a class="code" href="ao68000_8v.html#a0843baa7810722c7e1afd79aa615a9f0">`MICRO_DATA_data_write</a><span class="vhdlchar"></span>),
|
| 650 |
|
|
<a name="l00625"></a>00625 .<a class="code" href="classao68000.html#ac4bdc1d7a8df2e5b24f92e8c47b87d31">An_address</a> (<a class="code" href="classao68000.html#ac4bdc1d7a8df2e5b24f92e8c47b87d31">An_address</a>),
|
| 651 |
|
|
<a name="l00626"></a>00626 .<span class="vhdlchar">An_address_control</span> (<a class="code" href="ao68000_8v.html#a08e217a2a40544a7d5c4e916a3b4d6cf">`MICRO_DATA_an_address</a><span class="vhdlchar"></span>),
|
| 652 |
|
|
<a name="l00627"></a>00627 .<a class="code" href="classao68000.html#a314e14c9d14faca666d7282e70aec69e">An_input</a> (<a class="code" href="classao68000.html#a314e14c9d14faca666d7282e70aec69e">An_input</a>),
|
| 653 |
|
|
<a name="l00628"></a>00628 .<span class="vhdlchar">An_input_control</span> (<a class="code" href="ao68000_8v.html#aa6a6132c427e511630e6889582d48828">`MICRO_DATA_an_input</a><span class="vhdlchar"></span>),
|
| 654 |
|
|
<a name="l00629"></a>00629 .<a class="code" href="classao68000.html#a8ce376b6468188948a66dd3090b82303">Dn_address</a> (<a class="code" href="classao68000.html#a8ce376b6468188948a66dd3090b82303">Dn_address</a>),
|
| 655 |
|
|
<a name="l00630"></a>00630 .<span class="vhdlchar">Dn_address_control</span> (<a class="code" href="ao68000_8v.html#a1055ed2c94344c9b59a9061b451fd4b8">`MICRO_DATA_dn_address</a><span class="vhdlchar"></span>)
|
| 656 |
|
|
<a name="l00631"></a>00631 );
|
| 657 |
|
|
<a name="l00632"></a>00632
|
| 658 |
|
|
<a name="l00633"></a><a class="code" href="classao68000.html#ab85a25c3b08b1de81856944a16fafd5d">00633</a> <a class="code" href="classao68000.html#ab85a25c3b08b1de81856944a16fafd5d">memory_registers</a> <span class="vhdlchar">memory_registers_m</span>(
|
| 659 |
|
|
<a name="l00634"></a>00634 .<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">ao68000</a> (<a class="code" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a>),
|
| 660 |
|
|
<a name="l00635"></a>00635 .<a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">ao68000</a> (<a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">ao68000</a>),
|
| 661 |
|
|
<a name="l00636"></a>00636 .<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">ao68000</a> (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">ao68000</a>),
|
| 662 |
|
|
<a name="l00637"></a>00637 .<a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">ao68000</a> (<a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">ao68000</a>),
|
| 663 |
|
|
<a name="l00638"></a>00638 .<a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">ao68000</a> (<a class="code" href="ao68000_8v.html#af767fe70444603fdcde8beb39ef85c8c">`MICRO_DATA_an_write_enable</a><span class="vhdlchar"></span>),
|
| 664 |
|
|
<a name="l00639"></a>00639 .<a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">ao68000</a> (<a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">ao68000</a>),
|
| 665 |
|
|
<a name="l00640"></a>00640 .<a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">ao68000</a> (<a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">ao68000</a>),
|
| 666 |
|
|
<a name="l00641"></a>00641 .<a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">ao68000</a> (<a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">ao68000</a>),
|
| 667 |
|
|
<a name="l00642"></a>00642 .<a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">ao68000</a> (<a class="code" href="classao68000.html#ae78165f07b720df4d51db101effc08c5">result</a>),
|
| 668 |
|
|
<a name="l00643"></a>00643 .<a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">ao68000</a> (<a class="code" href="ao68000_8v.html#abb7709933320bf644d6a57c3040538a3">`MICRO_DATA_dn_write_enable</a><span class="vhdlchar"></span>),
|
| 669 |
|
|
<a name="l00644"></a>00644 .<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">ao68000</a> (<a class="code" href="classao68000.html#a7e653ecba236b212b87d66d9e46f3914">size</a>),
|
| 670 |
|
|
<a name="l00645"></a>00645 .<a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">ao68000</a> (<a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">ao68000</a>),
|
| 671 |
|
|
<a name="l00646"></a>00646 .<a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">ao68000</a> (<a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">ao68000</a>),
|
| 672 |
|
|
<a name="l00647"></a>00647 .<a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">ao68000</a> (<a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">ao68000</a>)
|
| 673 |
|
|
<a name="l00648"></a>00648 );
|
| 674 |
|
|
<a name="l00649"></a>00649
|
| 675 |
|
|
<a name="l00650"></a><a class="code" href="classao68000.html#a6f5a57c27d91cf2c4092c71adf13ae81">00650</a> <a class="code" href="classao68000.html#a6f5a57c27d91cf2c4092c71adf13ae81">decoder</a> <span class="vhdlchar">decoder_m</span>(
|
| 676 |
|
|
<a name="l00651"></a>00651 .<a class="code" href="classdecoder.html#a07ea698e43905b149515da25bf07d981">ao68000</a> (<a class="code" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a>),
|
| 677 |
|
|
<a name="l00652"></a>00652 .<a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">ao68000</a> (<a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">ao68000</a>),
|
| 678 |
|
|
<a name="l00653"></a>00653 .<a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">ao68000</a> (<a class="code" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a>[<span class="vhdllogic">13</span>]),
|
| 679 |
|
|
<a name="l00654"></a>00654 .<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ao68000</a> (<a class="code" href="classao68000.html#a3403e55545d6a49c4a4fa6f16cfe7126">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>]),
|
| 680 |
|
|
<a name="l00655"></a>00655 .<a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">ao68000</a> (<a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">ao68000</a>),
|
| 681 |
|
|
<a name="l00656"></a>00656 .<a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">ao68000</a> (<a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">ao68000</a>),
|
| 682 |
|
|
<a name="l00657"></a>00657
|
| 683 |
|
|
<a name="l00658"></a>00658 .<a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">ao68000</a> (<a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">ao68000</a>),
|
| 684 |
|
|
<a name="l00659"></a>00659 .<a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">ao68000</a> (<a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">ao68000</a>),
|
| 685 |
|
|
<a name="l00660"></a>00660 .<a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">ao68000</a> (<a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">ao68000</a>),
|
| 686 |
|
|
<a name="l00661"></a>00661 .<a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">ao68000</a> (<a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">ao68000</a>),
|
| 687 |
|
|
<a name="l00662"></a>00662
|
| 688 |
|
|
<a name="l00663"></a>00663 .<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ao68000</a> (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ao68000</a>),
|
| 689 |
|
|
<a name="l00664"></a>00664 .<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ao68000</a> (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ao68000</a>),
|
| 690 |
|
|
<a name="l00665"></a>00665 .<a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ao68000</a> (<a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ao68000</a>)
|
| 691 |
|
|
<a name="l00666"></a>00666 );
|
| 692 |
|
|
<a name="l00667"></a>00667
|
| 693 |
|
|
<a name="l00668"></a><a class="code" href="classao68000.html#a30446f4f602b6185a7ed25e5aa8e470e">00668</a> <a class="code" href="classao68000.html#a30446f4f602b6185a7ed25e5aa8e470e">condition</a> <span class="vhdlchar">condition_m</span>(
|
| 694 |
|
|
<a name="l00669"></a>00669 .<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">ao68000</a> (<a class="code" href="classao68000.html#a88e0be4d7a8d7765fd81d2c7ecec034c">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>]),
|
| 695 |
|
|
<a name="l00670"></a>00670 .<a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ao68000</a> (<a class="code" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>]),
|
| 696 |
|
|
<a name="l00671"></a>00671 .<a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">ao68000</a> (<a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">ao68000</a>)
|
| 697 |
|
|
<a name="l00672"></a>00672 );
|
| 698 |
|
|
<a name="l00673"></a>00673
|
| 699 |
|
|
<a name="l00674"></a><a class="code" href="classao68000.html#a63ee30297781426b4dd11d052490997f">00674</a> <a class="code" href="classao68000.html#a63ee30297781426b4dd11d052490997f">alu</a> <span class="vhdlchar">alu_m</span>(
|
| 700 |
|
|
<a name="l00675"></a>00675 .<a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">ao68000</a> (<a class="code" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a>),
|
| 701 |
|
|
<a name="l00676"></a>00676 .<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">ao68000</a> (<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">ao68000</a>),
|
| 702 |
|
|
<a name="l00677"></a>00677 .<a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">ao68000</a> (<a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">ao68000</a>),
|
| 703 |
|
|
<a name="l00678"></a>00678 .<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ao68000</a> (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ao68000</a>),
|
| 704 |
|
|
<a name="l00679"></a>00679 .<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">ao68000</a> (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">ao68000</a>),
|
| 705 |
|
|
<a name="l00680"></a>00680 .<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">ao68000</a> (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">ao68000</a>),
|
| 706 |
|
|
<a name="l00681"></a>00681 .<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">ao68000</a> (<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">ao68000</a>),
|
| 707 |
|
|
<a name="l00682"></a>00682 .<a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">ao68000</a> (<a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">ao68000</a>),
|
| 708 |
|
|
<a name="l00683"></a>00683 .<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">ao68000</a> (<a class="code" href="ao68000_8v.html#a6dde91e1905423f9fb4184ae3554b5cd">`MICRO_DATA_alu</a><span class="vhdlchar"></span>),
|
| 709 |
|
|
<a name="l00684"></a>00684 .<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">ao68000</a> (<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">ao68000</a>),
|
| 710 |
|
|
<a name="l00685"></a>00685 .<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">ao68000</a> (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">ao68000</a>),
|
| 711 |
|
|
<a name="l00686"></a>00686 .<a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">ao68000</a> (<a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">ao68000</a>),
|
| 712 |
|
|
<a name="l00687"></a>00687 .<a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">ao68000</a> (<a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">ao68000</a>)
|
| 713 |
|
|
<a name="l00688"></a>00688 );
|
| 714 |
|
|
<a name="l00689"></a>00689
|
| 715 |
|
|
<a name="l00690"></a><a class="code" href="classao68000.html#a753de474d4bdb41b494fed2539290cc4">00690</a> <a class="code" href="classao68000.html#a753de474d4bdb41b494fed2539290cc4">microcode_branch</a> <span class="vhdlchar">microcode_branch_m</span>(
|
| 716 |
|
|
<a name="l00691"></a>00691 .<a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">ao68000</a> (<a class="code" href="classao68000.html#a6bee7e749a667293d6fbea8fc1380d12">CLK_I</a>),
|
| 717 |
|
|
<a name="l00692"></a>00692 .<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">ao68000</a>),
|
| 718 |
|
|
<a name="l00693"></a>00693 .<a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">ao68000</a>),
|
| 719 |
|
|
<a name="l00694"></a>00694 .<a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">ao68000</a> (<a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">ao68000</a>),
|
| 720 |
|
|
<a name="l00695"></a>00695 .<a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">ao68000</a>),
|
| 721 |
|
|
<a name="l00696"></a>00696 .<a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">ao68000</a> (<a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">ao68000</a>),
|
| 722 |
|
|
<a name="l00697"></a>00697 .<a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">ao68000</a>),
|
| 723 |
|
|
<a name="l00698"></a>00698 .<a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">ao68000</a>),
|
| 724 |
|
|
<a name="l00699"></a>00699 .<a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">ao68000</a>),
|
| 725 |
|
|
<a name="l00700"></a>00700 .<a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">ao68000</a> (<a class="code" href="classao68000.html#abef0ede1a300bfe80eeecc8d51a0afe0">sr</a>[<span class="vhdllogic">1</span>]),
|
| 726 |
|
|
<a name="l00701"></a>00701 .<a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">ao68000</a>),
|
| 727 |
|
|
<a name="l00702"></a>00702 .<a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ao68000</a>),
|
| 728 |
|
|
<a name="l00703"></a>00703 .<a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">ao68000</a>),
|
| 729 |
|
|
<a name="l00704"></a>00704 .<a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">ao68000</a>),
|
| 730 |
|
|
<a name="l00705"></a>00705 .<a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">ao68000</a>),
|
| 731 |
|
|
<a name="l00706"></a>00706 .<a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">ao68000</a>),
|
| 732 |
|
|
<a name="l00707"></a>00707 .<a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">ao68000</a>),
|
| 733 |
|
|
<a name="l00708"></a>00708 .<a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">ao68000</a> (<a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">ao68000</a>),
|
| 734 |
|
|
<a name="l00709"></a>00709 .<a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">ao68000</a>),
|
| 735 |
|
|
<a name="l00710"></a>00710 .<a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">ao68000</a>),
|
| 736 |
|
|
<a name="l00711"></a>00711 .<a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">ao68000</a>),
|
| 737 |
|
|
<a name="l00712"></a>00712 .<a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">ao68000</a> (<a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">ao68000</a>),
|
| 738 |
|
|
<a name="l00713"></a>00713 .<a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">ao68000</a> (<a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">ao68000</a>),
|
| 739 |
|
|
<a name="l00714"></a>00714 .<a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">ao68000</a> (<a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">ao68000</a>),
|
| 740 |
|
|
<a name="l00715"></a>00715 .<a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">ao68000</a>),
|
| 741 |
|
|
<a name="l00716"></a>00716 .<a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">ao68000</a> (<a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">ao68000</a>),
|
| 742 |
|
|
<a name="l00717"></a>00717 .<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">ao68000</a> (<a class="code" href="ao68000_8v.html#a156b8e8011ac86392d0e47b50cc1bd12">`MICRO_DATA_branch</a><span class="vhdlchar"></span>),
|
| 743 |
|
|
<a name="l00718"></a>00718 .<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">ao68000</a> (<a class="code" href="ao68000_8v.html#a8356eb451657c128626552b5a360de3a">`MICRO_DATA_procedure</a><span class="vhdlchar"></span>),
|
| 744 |
|
|
<a name="l00719"></a>00719 .<a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">ao68000</a> (<a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">ao68000</a>)
|
| 745 |
|
|
<a name="l00720"></a>00720 );
|
| 746 |
|
|
<a name="l00721"></a>00721
|
| 747 |
|
|
<a name="l00722"></a>00722 <span class="vhdlkeyword">endmodule</span>
|
| 748 |
|
|
<a name="l00723"></a>00723
|
| 749 |
|
|
<a name="l00724"></a>00724 <span class="keyword">/***********************************************************************************************************************</span>
|
| 750 |
|
|
<a name="l00725"></a>00725 <span class="keyword"> Bus control</span>
|
| 751 |
|
|
<a name="l00726"></a>00726 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 752 |
|
|
<a name="l00727"></a>00727
|
| 753 |
|
|
<a name="l00728"></a>00728
|
| 754 |
|
|
<a name="l00751"></a><a class="code" href="classbus__control.html">00751</a> <span class="vhdlkeyword">module</span> <a class="code" href="classao68000.html#a2c34e1b84d9fe30c49c5c814be3dc392">bus_control</a>(
|
| 755 |
|
|
<a name="l00752"></a>00752 <span class="keyword">//******************************************* external</span>
|
| 756 |
|
|
<a name="l00753"></a>00753 <span class="keyword">//****************** WISHBONE</span>
|
| 757 |
|
|
<a name="l00754"></a><a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">00754</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a>,
|
| 758 |
|
|
<a name="l00755"></a><a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">00755</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a>,
|
| 759 |
|
|
<a name="l00756"></a>00756
|
| 760 |
|
|
<a name="l00757"></a><a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">00757</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a>,
|
| 761 |
|
|
<a name="l00758"></a><a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">00758</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>,
|
| 762 |
|
|
<a name="l00759"></a><a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">00759</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a>,
|
| 763 |
|
|
<a name="l00760"></a><a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">00760</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>,
|
| 764 |
|
|
<a name="l00761"></a><a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">00761</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a>,
|
| 765 |
|
|
<a name="l00762"></a><a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">00762</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a>,
|
| 766 |
|
|
<a name="l00763"></a><a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">00763</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>,
|
| 767 |
|
|
<a name="l00764"></a>00764
|
| 768 |
|
|
<a name="l00765"></a><a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">00765</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a>,
|
| 769 |
|
|
<a name="l00766"></a><a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">00766</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a>,
|
| 770 |
|
|
<a name="l00767"></a><a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">00767</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a>,
|
| 771 |
|
|
<a name="l00768"></a>00768
|
| 772 |
|
|
<a name="l00769"></a>00769 <span class="keyword">// TAG_TYPE: TGC_O</span>
|
| 773 |
|
|
<a name="l00770"></a><a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">00770</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a>,
|
| 774 |
|
|
<a name="l00771"></a><a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">00771</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a>,
|
| 775 |
|
|
<a name="l00772"></a><a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">00772</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a>,
|
| 776 |
|
|
<a name="l00773"></a>00773
|
| 777 |
|
|
<a name="l00774"></a>00774 <span class="keyword">// TAG_TYPE: TGA_O</span>
|
| 778 |
|
|
<a name="l00775"></a><a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">00775</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a>,
|
| 779 |
|
|
<a name="l00776"></a><a class="code" href="classbus__control.html#ada8208aac77c8a5b2d937d050a85ded6">00776</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#ada8208aac77c8a5b2d937d050a85ded6">BTE_O</a>,
|
| 780 |
12 |
alfik |
<a name="l00777"></a>00777
|
| 781 |
13 |
alfik |
<a name="l00778"></a>00778 <span class="keyword">// TAG_TYPE: TGC_O</span>
|
| 782 |
|
|
<a name="l00779"></a><a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">00779</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>,
|
| 783 |
|
|
<a name="l00780"></a>00780
|
| 784 |
|
|
<a name="l00781"></a>00781 <span class="keyword">//****************** OTHER</span>
|
| 785 |
|
|
<a name="l00782"></a><a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">00782</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ipl_i</a>,
|
| 786 |
|
|
<a name="l00783"></a><a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">00783</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a> = <span class="vhdllogic">1'b0</span>,
|
| 787 |
|
|
<a name="l00784"></a>00784 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> blocked_o = <span class="vhdllogic">1'b0</span>,
|
| 788 |
|
|
<a name="l00785"></a>00785
|
| 789 |
|
|
<a name="l00786"></a>00786 <span class="keyword">//******************************************* internal</span>
|
| 790 |
|
|
<a name="l00787"></a>00787 <span class="vhdlkeyword">input</span> supervisor_i,
|
| 791 |
|
|
<a name="l00788"></a>00788 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ipm_i,
|
| 792 |
|
|
<a name="l00789"></a>00789 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] size_i,
|
| 793 |
|
|
<a name="l00790"></a>00790 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] address_i,
|
| 794 |
|
|
<a name="l00791"></a>00791 <span class="vhdlkeyword">input</span> address_type_i,
|
| 795 |
|
|
<a name="l00792"></a>00792 <span class="vhdlkeyword">input</span> read_modify_write_i,
|
| 796 |
|
|
<a name="l00793"></a>00793 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] data_write_i,
|
| 797 |
|
|
<a name="l00794"></a>00794 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] data_read_o,
|
| 798 |
|
|
<a name="l00795"></a>00795
|
| 799 |
|
|
<a name="l00796"></a>00796 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] pc_i,
|
| 800 |
|
|
<a name="l00797"></a>00797 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] pc_change_i,
|
| 801 |
|
|
<a name="l00798"></a>00798 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">79</span>:<span class="vhdllogic">0</span>] prefetch_ir_o,
|
| 802 |
|
|
<a name="l00799"></a>00799 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> prefetch_ir_valid_32_o = <span class="vhdllogic">1'b0</span>,
|
| 803 |
|
|
<a name="l00800"></a>00800 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> prefetch_ir_valid_o = <span class="vhdllogic">1'b0</span>,
|
| 804 |
|
|
<a name="l00801"></a>00801 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> prefetch_ir_valid_80_o = <span class="vhdllogic">1'b0</span>,
|
| 805 |
|
|
<a name="l00802"></a>00802
|
| 806 |
|
|
<a name="l00803"></a>00803 <span class="vhdlkeyword">input</span> do_reset_i,
|
| 807 |
|
|
<a name="l00804"></a>00804 <span class="vhdlkeyword">input</span> do_blocked_i,
|
| 808 |
|
|
<a name="l00805"></a>00805 <span class="vhdlkeyword">input</span> do_read_i,
|
| 809 |
|
|
<a name="l00806"></a>00806 <span class="vhdlkeyword">input</span> do_write_i,
|
| 810 |
|
|
<a name="l00807"></a>00807 <span class="vhdlkeyword">input</span> do_interrupt_i,
|
| 811 |
|
|
<a name="l00808"></a>00808
|
| 812 |
|
|
<a name="l00809"></a>00809 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> jmp_address_trap_o = <span class="vhdllogic">1'b0</span>,
|
| 813 |
|
|
<a name="l00810"></a>00810 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> jmp_bus_trap_o = <span class="vhdllogic">1'b0</span>,
|
| 814 |
|
|
<a name="l00811"></a>00811 <span class="keyword">// read/write/interrupt</span>
|
| 815 |
|
|
<a name="l00812"></a>00812 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> finished_o,
|
| 816 |
12 |
alfik |
<a name="l00813"></a>00813
|
| 817 |
13 |
alfik |
<a name="l00814"></a>00814 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] interrupt_trap_o = <span class="vhdllogic">8'b0</span>,
|
| 818 |
|
|
<a name="l00815"></a>00815 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] interrupt_mask_o = <span class="vhdllogic">3'b0</span>,
|
| 819 |
|
|
<a name="l00816"></a>00816
|
| 820 |
|
|
<a name="l00817"></a>00817 <span class="keyword">/* mask==0 && trap==0 nothing</span>
|
| 821 |
|
|
<a name="l00818"></a>00818 <span class="keyword"> mask!=0 interrupt with spurious interrupt</span>
|
| 822 |
|
|
<a name="l00819"></a>00819 <span class="keyword"> */</span>
|
| 823 |
|
|
<a name="l00820"></a>00820
|
| 824 |
|
|
<a name="l00821"></a>00821 <span class="keyword">// write = 0/read = 1</span>
|
| 825 |
|
|
<a name="l00822"></a>00822 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> rw_state_o,
|
| 826 |
|
|
<a name="l00823"></a>00823 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] fc_state_o,
|
| 827 |
|
|
<a name="l00824"></a>00824 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] fault_address_state_o
|
| 828 |
|
|
<a name="l00825"></a>00825 );
|
| 829 |
|
|
<a name="l00826"></a>00826
|
| 830 |
|
|
<a name="l00827"></a>00827 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__control.html#ada8208aac77c8a5b2d937d050a85ded6">BTE_O</a> = <span class="vhdllogic">2'b00</span>;
|
| 831 |
|
|
<a name="l00828"></a>00828
|
| 832 |
|
|
<a name="l00829"></a><a class="code" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">00829</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a>;
|
| 833 |
|
|
<a name="l00830"></a>00830 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a> = <span class="vhdlchar">pc_i</span> + <span class="vhdllogic">32'd6</span>;
|
| 834 |
|
|
<a name="l00831"></a><a class="code" href="classbus__control.html#ad4e505c885a6c941198d653beff91bf1">00831</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#ad4e505c885a6c941198d653beff91bf1">pc_i_plus_4</a>;
|
| 835 |
|
|
<a name="l00832"></a>00832 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__control.html#ad4e505c885a6c941198d653beff91bf1">pc_i_plus_4</a> = <span class="vhdlchar">pc_i</span> + <span class="vhdllogic">32'd4</span>;
|
| 836 |
12 |
alfik |
<a name="l00833"></a>00833
|
| 837 |
13 |
alfik |
<a name="l00834"></a><a class="code" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">00834</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a>;
|
| 838 |
|
|
<a name="l00835"></a>00835 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a> = <span class="vhdlchar">address_i</span> + <span class="vhdllogic">32'd4</span>;
|
| 839 |
|
|
<a name="l00836"></a>00836
|
| 840 |
|
|
<a name="l00837"></a><a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">00837</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> = <span class="vhdllogic">2'b00</span>;
|
| 841 |
|
|
<a name="l00838"></a>00838
|
| 842 |
|
|
<a name="l00839"></a><a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">00839</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>]
|
| 843 |
|
|
<a name="l00840"></a>00840 <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a> = <span class="vhdllogic">5'd0</span>,
|
| 844 |
|
|
<a name="l00841"></a>00841 <a class="code" href="classbus__control.html#a21f9753bb3594dcc9d190ef5c54071e6">S_RESET</a> = <span class="vhdllogic">5'd1</span>,
|
| 845 |
|
|
<a name="l00842"></a>00842 <a class="code" href="classbus__control.html#a35c0778e16a225b839acc35705428b6a">S_BLOCKED</a> = <span class="vhdllogic">5'd2</span>,
|
| 846 |
|
|
<a name="l00843"></a>00843 <a class="code" href="classbus__control.html#a22028b6e9c3a87066084eeb7e3ea66dc">S_INT_1</a> = <span class="vhdllogic">5'd3</span>,
|
| 847 |
|
|
<a name="l00844"></a>00844 <a class="code" href="classbus__control.html#a0957d5175230f9062a95b56e1db2fc53">S_READ_1</a> = <span class="vhdllogic">5'd4</span>,
|
| 848 |
|
|
<a name="l00845"></a>00845 <a class="code" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a> = <span class="vhdllogic">5'd5</span>,
|
| 849 |
|
|
<a name="l00846"></a>00846 <a class="code" href="classbus__control.html#ae156bee4c9bdf06b34803d8d68d9f50f">S_READ_3</a> = <span class="vhdllogic">5'd6</span>,
|
| 850 |
|
|
<a name="l00847"></a>00847 <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a> = <span class="vhdllogic">5'd7</span>,
|
| 851 |
|
|
<a name="l00848"></a>00848 <a class="code" href="classbus__control.html#a47878ecd24d5368e7396dd97ec9f4077">S_WRITE_1</a> = <span class="vhdllogic">5'd8</span>,
|
| 852 |
|
|
<a name="l00849"></a>00849 <a class="code" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a> = <span class="vhdllogic">5'd9</span>,
|
| 853 |
|
|
<a name="l00850"></a>00850 <a class="code" href="classbus__control.html#a7c1c733e80689349399716f442a5db8d">S_WRITE_3</a> = <span class="vhdllogic">5'd10</span>,
|
| 854 |
|
|
<a name="l00851"></a>00851 <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a> = <span class="vhdllogic">5'd11</span>,
|
| 855 |
|
|
<a name="l00852"></a>00852 <a class="code" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a> = <span class="vhdllogic">5'd12</span>,
|
| 856 |
|
|
<a name="l00853"></a>00853 <a class="code" href="classbus__control.html#a4b9998b72c69db4dcd98755835413fda">S_PC_2</a> = <span class="vhdllogic">5'd13</span>,
|
| 857 |
|
|
<a name="l00854"></a>00854 <a class="code" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a> = <span class="vhdllogic">5'd14</span>,
|
| 858 |
|
|
<a name="l00855"></a>00855 <a class="code" href="classbus__control.html#aec52b8e16695194dcbfefab239d8a94a">S_PC_4</a> = <span class="vhdllogic">5'd15</span>,
|
| 859 |
|
|
<a name="l00856"></a>00856 <a class="code" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a> = <span class="vhdllogic">5'd16</span>,
|
| 860 |
|
|
<a name="l00857"></a>00857 <a class="code" href="classbus__control.html#a95ac5f10cc1642a474302d109678e2c2">S_PC_6</a> = <span class="vhdllogic">5'd17</span>;
|
| 861 |
|
|
<a name="l00858"></a>00858
|
| 862 |
|
|
<a name="l00859"></a><a class="code" href="classbus__control.html#aabcbc5528d37aad94c1c91f72abe9788">00859</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>]
|
| 863 |
|
|
<a name="l00860"></a>00860 <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a> = <span class="vhdllogic">3'd1</span>,
|
| 864 |
|
|
<a name="l00861"></a>00861 <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a> = <span class="vhdllogic">3'd2</span>,
|
| 865 |
|
|
<a name="l00862"></a>00862 <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a> = <span class="vhdllogic">3'd5</span>, <span class="keyword">// all exception vector entries except reset</span>
|
| 866 |
|
|
<a name="l00863"></a>00863 <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a> = <span class="vhdllogic">3'd6</span>, <span class="keyword">// exception vector for reset</span>
|
| 867 |
|
|
<a name="l00864"></a>00864 <a class="code" href="classbus__control.html#aabcbc5528d37aad94c1c91f72abe9788">FC_CPU_SPACE</a> = <span class="vhdllogic">3'd7</span>; <span class="keyword">// interrupt acknowlege bus cycle</span>
|
| 868 |
|
|
<a name="l00865"></a>00865
|
| 869 |
|
|
<a name="l00866"></a><a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">00866</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>]
|
| 870 |
|
|
<a name="l00867"></a>00867 <a class="code" href="classbus__control.html#ad3b1eccec1964a8067b4d458c0735bec">CTI_CLASSIC_CYCLE</a> = <span class="vhdllogic">3'd0</span>,
|
| 871 |
|
|
<a name="l00868"></a>00868 <a class="code" href="classbus__control.html#a965b59e7efe4fa822995720d75210d72">CTI_CONST_CYCLE</a> = <span class="vhdllogic">3'd1</span>,
|
| 872 |
|
|
<a name="l00869"></a>00869 <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a> = <span class="vhdllogic">3'd2</span>,
|
| 873 |
|
|
<a name="l00870"></a>00870 <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a> = <span class="vhdllogic">3'd7</span>;
|
| 874 |
|
|
<a name="l00871"></a>00871
|
| 875 |
|
|
<a name="l00872"></a><a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">00872</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>]
|
| 876 |
|
|
<a name="l00873"></a>00873 <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a> = <span class="vhdllogic">8'd2</span>,
|
| 877 |
|
|
<a name="l00874"></a>00874 <a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a> = <span class="vhdllogic">8'd3</span>;
|
| 878 |
12 |
alfik |
<a name="l00875"></a>00875
|
| 879 |
13 |
alfik |
<a name="l00876"></a><a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">00876</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a>;
|
| 880 |
|
|
<a name="l00877"></a><a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">00877</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a>;
|
| 881 |
|
|
<a name="l00878"></a>00878
|
| 882 |
|
|
<a name="l00879"></a><a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">00879</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a>;
|
| 883 |
|
|
<a name="l00880"></a><a class="code" href="classbus__control.html#ad06cdf24c29b1b82596011bac2c9169c">00880</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 884 |
|
|
<a name="l00881"></a>00881 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 885 |
|
|
<a name="l00882"></a>00882 <span class="vhdlchar">interrupt_mask_o</span> <= <span class="vhdllogic">3'b000</span>;
|
| 886 |
|
|
<a name="l00883"></a>00883 <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> <= <span class="vhdllogic">3'b000</span>;
|
| 887 |
|
|
<a name="l00884"></a>00884 <span class="vhdlkeyword">end</span>
|
| 888 |
|
|
<a name="l00885"></a>00885 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ipl_i</a> > <span class="vhdlchar">ipm_i</span> && <span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 889 |
|
|
<a name="l00886"></a>00886 <span class="vhdlchar">interrupt_mask_o</span> <= <a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ipl_i</a>;
|
| 890 |
|
|
<a name="l00887"></a>00887 <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> <= <span class="vhdlchar">interrupt_mask_o</span>;
|
| 891 |
12 |
alfik |
<a name="l00888"></a>00888 <span class="vhdlkeyword">end</span>
|
| 892 |
13 |
alfik |
<a name="l00889"></a>00889 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 893 |
|
|
<a name="l00890"></a>00890 <span class="vhdlchar">interrupt_mask_o</span> <= <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a>;
|
| 894 |
|
|
<a name="l00891"></a>00891 <span class="vhdlkeyword">end</span>
|
| 895 |
|
|
<a name="l00892"></a>00892 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 896 |
|
|
<a name="l00893"></a>00893 <span class="vhdlchar">interrupt_mask_o</span> <= <span class="vhdllogic">3'b000</span>;
|
| 897 |
|
|
<a name="l00894"></a>00894 <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> <= <span class="vhdllogic">3'b000</span>;
|
| 898 |
|
|
<a name="l00895"></a>00895 <span class="vhdlkeyword">end</span>
|
| 899 |
|
|
<a name="l00896"></a>00896 <span class="vhdlkeyword">end</span>
|
| 900 |
|
|
<a name="l00897"></a>00897
|
| 901 |
|
|
<a name="l00898"></a>00898 <span class="keyword">// change pc_i in middle of prefetch operation: undefined</span>
|
| 902 |
|
|
<a name="l00899"></a>00899
|
| 903 |
|
|
<a name="l00900"></a><a class="code" href="classbus__control.html#af34450e53e6fd2fd36db7dff17caf063">00900</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 904 |
|
|
<a name="l00901"></a>00901 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 905 |
|
|
<a name="l00902"></a>00902 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 906 |
|
|
<a name="l00903"></a>00903 <span class="vhdlchar">interrupt_trap_o</span> <= <span class="vhdllogic">8'd0</span>;
|
| 907 |
|
|
<a name="l00904"></a>00904 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 908 |
|
|
<a name="l00905"></a>00905 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 909 |
|
|
<a name="l00906"></a>00906 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 910 |
|
|
<a name="l00907"></a>00907
|
| 911 |
|
|
<a name="l00908"></a>00908 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 912 |
|
|
<a name="l00909"></a>00909 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 913 |
|
|
<a name="l00910"></a>00910
|
| 914 |
|
|
<a name="l00911"></a>00911 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 915 |
|
|
<a name="l00912"></a>00912 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdllogic">30'd0</span>;
|
| 916 |
|
|
<a name="l00913"></a>00913 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= <span class="vhdllogic">32'd0</span>;
|
| 917 |
|
|
<a name="l00914"></a>00914 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0</span>;
|
| 918 |
|
|
<a name="l00915"></a>00915 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 919 |
|
|
<a name="l00916"></a>00916 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 920 |
|
|
<a name="l00917"></a>00917 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 921 |
|
|
<a name="l00918"></a>00918 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 922 |
|
|
<a name="l00919"></a>00919 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 923 |
|
|
<a name="l00920"></a>00920 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <span class="vhdllogic">3'd0</span>;
|
| 924 |
|
|
<a name="l00921"></a>00921 <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <span class="vhdllogic">3'd0</span>;
|
| 925 |
|
|
<a name="l00922"></a>00922 <a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a> <= <span class="vhdllogic">1'b0</span>;
|
| 926 |
|
|
<a name="l00923"></a>00923 <span class="vhdlchar">blocked_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 927 |
|
|
<a name="l00924"></a>00924 <span class="vhdlchar">data_read_o</span> <= <span class="vhdllogic">32'd0</span>;
|
| 928 |
|
|
<a name="l00925"></a>00925 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 929 |
|
|
<a name="l00926"></a>00926 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 930 |
|
|
<a name="l00927"></a>00927 <span class="vhdlchar">fc_state_o</span> <= <span class="vhdllogic">3'd0</span>;
|
| 931 |
|
|
<a name="l00928"></a>00928 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdllogic">32'd0</span>;
|
| 932 |
|
|
<a name="l00929"></a>00929 <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> <= <span class="vhdllogic">2'b0</span>;
|
| 933 |
|
|
<a name="l00930"></a>00930 <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> <= <span class="vhdllogic">8'd0</span>;
|
| 934 |
|
|
<a name="l00931"></a>00931 <span class="vhdlkeyword">end</span>
|
| 935 |
|
|
<a name="l00932"></a>00932 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 936 |
|
|
<a name="l00933"></a>00933 <span class="vhdlkeyword">case</span>(<a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a>)
|
| 937 |
|
|
<a name="l00934"></a>00934 <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>: <span class="vhdlkeyword">begin</span>
|
| 938 |
|
|
<a name="l00935"></a>00935 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 939 |
|
|
<a name="l00936"></a>00936 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 940 |
|
|
<a name="l00937"></a>00937 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 941 |
|
|
<a name="l00938"></a>00938 <a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a> <= <span class="vhdllogic">1'b0</span>;
|
| 942 |
|
|
<a name="l00939"></a>00939 <span class="vhdlchar">blocked_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 943 |
|
|
<a name="l00940"></a>00940
|
| 944 |
|
|
<a name="l00941"></a>00941 <span class="keyword">// block</span>
|
| 945 |
|
|
<a name="l00942"></a>00942 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_blocked_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 946 |
|
|
<a name="l00943"></a>00943 <span class="vhdlchar">blocked_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 947 |
|
|
<a name="l00944"></a>00944 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a35c0778e16a225b839acc35705428b6a">S_BLOCKED</a>;
|
| 948 |
|
|
<a name="l00945"></a>00945 <span class="vhdlkeyword">end</span>
|
| 949 |
|
|
<a name="l00946"></a>00946 <span class="keyword">// reset</span>
|
| 950 |
|
|
<a name="l00947"></a>00947 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 951 |
|
|
<a name="l00948"></a>00948 <a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a> <= <span class="vhdllogic">1'b1</span>;
|
| 952 |
|
|
<a name="l00949"></a>00949 <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> <= <span class="vhdllogic">8'd124</span>;
|
| 953 |
|
|
<a name="l00950"></a>00950 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a21f9753bb3594dcc9d190ef5c54071e6">S_RESET</a>;
|
| 954 |
|
|
<a name="l00951"></a>00951 <span class="vhdlkeyword">end</span>
|
| 955 |
|
|
<a name="l00952"></a>00952 <span class="keyword">// read</span>
|
| 956 |
|
|
<a name="l00953"></a>00953 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 957 |
|
|
<a name="l00954"></a>00954 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 958 |
|
|
<a name="l00955"></a>00955 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= (<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a> : <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a>;
|
| 959 |
|
|
<a name="l00956"></a>00956 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= (<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a> : <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>;
|
| 960 |
|
|
<a name="l00957"></a>00957
|
| 961 |
|
|
<a name="l00958"></a>00958 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span>)) <span class="vhdlkeyword">begin</span> <span class="keyword">// WORD or LONG WORD</span>
|
| 962 |
|
|
<a name="l00959"></a>00959 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdlchar">address_i</span>;
|
| 963 |
|
|
<a name="l00960"></a>00960 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 964 |
|
|
<a name="l00961"></a>00961 <span class="vhdlchar">fc_state_o</span> <= (<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) ? ((<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a> : <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a>) :
|
| 965 |
|
|
<a name="l00962"></a>00962 ((<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a> : <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>);
|
| 966 |
|
|
<a name="l00963"></a>00963 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a>;
|
| 967 |
|
|
<a name="l00964"></a>00964
|
| 968 |
|
|
<a name="l00965"></a>00965 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 969 |
|
|
<a name="l00966"></a>00966 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 970 |
|
|
<a name="l00967"></a>00967 <span class="vhdlkeyword">end</span>
|
| 971 |
|
|
<a name="l00968"></a>00968 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 972 |
|
|
<a name="l00969"></a>00969 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 973 |
|
|
<a name="l00970"></a>00970 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdlchar">address_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 974 |
|
|
<a name="l00971"></a>00971 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span>)? <span class="vhdllogic">4'b1000</span> :
|
| 975 |
|
|
<a name="l00972"></a>00972 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b01</span>)? <span class="vhdllogic">4'b0100</span> :
|
| 976 |
|
|
<a name="l00973"></a>00973 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>)? <span class="vhdllogic">4'b0010</span> :
|
| 977 |
|
|
<a name="l00974"></a>00974 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span>)? <span class="vhdllogic">4'b0001</span> :
|
| 978 |
|
|
<a name="l00975"></a>00975 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">2'b0</span>)? <span class="vhdllogic">4'b1100</span> :
|
| 979 |
|
|
<a name="l00976"></a>00976 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">2'b1</span>)? <span class="vhdllogic">4'b0011</span> :
|
| 980 |
|
|
<a name="l00977"></a>00977 <span class="vhdllogic">4'b1111</span>;
|
| 981 |
|
|
<a name="l00978"></a>00978 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 982 |
|
|
<a name="l00979"></a>00979
|
| 983 |
|
|
<a name="l00980"></a>00980 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 984 |
|
|
<a name="l00981"></a>00981 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 985 |
|
|
<a name="l00982"></a>00982 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 986 |
|
|
<a name="l00983"></a>00983 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 987 |
|
|
<a name="l00984"></a>00984 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 988 |
|
|
<a name="l00985"></a>00985 <span class="vhdlkeyword">end</span>
|
| 989 |
|
|
<a name="l00986"></a>00986 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 990 |
|
|
<a name="l00987"></a>00987 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 991 |
|
|
<a name="l00988"></a>00988 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 992 |
|
|
<a name="l00989"></a>00989 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 993 |
|
|
<a name="l00990"></a>00990 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 994 |
|
|
<a name="l00991"></a>00991 <span class="vhdlkeyword">end</span>
|
| 995 |
|
|
<a name="l00992"></a>00992 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 996 |
|
|
<a name="l00993"></a>00993 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 997 |
|
|
<a name="l00994"></a>00994 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 998 |
|
|
<a name="l00995"></a>00995 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 999 |
|
|
<a name="l00996"></a>00996 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1000 |
|
|
<a name="l00997"></a>00997 <span class="vhdlkeyword">end</span>
|
| 1001 |
|
|
<a name="l00998"></a>00998
|
| 1002 |
|
|
<a name="l00999"></a>00999 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a0957d5175230f9062a95b56e1db2fc53">S_READ_1</a>;
|
| 1003 |
|
|
<a name="l01000"></a>01000 <span class="vhdlkeyword">end</span>
|
| 1004 |
|
|
<a name="l01001"></a>01001 <span class="vhdlkeyword">end</span>
|
| 1005 |
|
|
<a name="l01002"></a>01002 <span class="keyword">// write</span>
|
| 1006 |
|
|
<a name="l01003"></a>01003 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1007 |
|
|
<a name="l01004"></a>01004 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1008 |
|
|
<a name="l01005"></a>01005 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a>;
|
| 1009 |
|
|
<a name="l01006"></a>01006 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a>;
|
| 1010 |
|
|
<a name="l01007"></a>01007
|
| 1011 |
|
|
<a name="l01008"></a>01008 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span> <span class="keyword">// WORD or LONG WORD</span>
|
| 1012 |
|
|
<a name="l01009"></a>01009 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdlchar">address_i</span>;
|
| 1013 |
|
|
<a name="l01010"></a>01010 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1014 |
|
|
<a name="l01011"></a>01011 <span class="vhdlchar">fc_state_o</span> <= (<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a> : <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a>;
|
| 1015 |
|
|
<a name="l01012"></a>01012 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a>;
|
| 1016 |
|
|
<a name="l01013"></a>01013
|
| 1017 |
|
|
<a name="l01014"></a>01014 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1018 |
|
|
<a name="l01015"></a>01015 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1019 |
|
|
<a name="l01016"></a>01016 <span class="vhdlkeyword">end</span>
|
| 1020 |
|
|
<a name="l01017"></a>01017 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1021 |
|
|
<a name="l01018"></a>01018 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1022 |
|
|
<a name="l01019"></a>01019 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdlchar">address_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 1023 |
|
|
<a name="l01020"></a>01020 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1024 |
|
|
<a name="l01021"></a>01021
|
| 1025 |
|
|
<a name="l01022"></a>01022 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1026 |
|
|
<a name="l01023"></a>01023 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 1027 |
|
|
<a name="l01024"></a>01024 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0011</span>;
|
| 1028 |
|
|
<a name="l01025"></a>01025 <span class="vhdlkeyword">end</span>
|
| 1029 |
|
|
<a name="l01026"></a>01026 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1030 |
|
|
<a name="l01027"></a>01027 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 1031 |
|
|
<a name="l01028"></a>01028 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 1032 |
|
|
<a name="l01029"></a>01029 <span class="vhdlkeyword">end</span>
|
| 1033 |
|
|
<a name="l01030"></a>01030 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1034 |
|
|
<a name="l01031"></a>01031 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 1035 |
|
|
<a name="l01032"></a>01032 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0011</span>;
|
| 1036 |
|
|
<a name="l01033"></a>01033 <span class="vhdlkeyword">end</span>
|
| 1037 |
|
|
<a name="l01034"></a>01034 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1038 |
|
|
<a name="l01035"></a>01035 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1039 |
|
|
<a name="l01036"></a>01036 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1100</span>;
|
| 1040 |
|
|
<a name="l01037"></a>01037 <span class="vhdlkeyword">end</span>
|
| 1041 |
|
|
<a name="l01038"></a>01038 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1042 |
|
|
<a name="l01039"></a>01039 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">24'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 1043 |
|
|
<a name="l01040"></a>01040 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0001</span>;
|
| 1044 |
|
|
<a name="l01041"></a>01041 <span class="vhdlkeyword">end</span>
|
| 1045 |
|
|
<a name="l01042"></a>01042 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1046 |
|
|
<a name="l01043"></a>01043 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">8'b0</span> };
|
| 1047 |
|
|
<a name="l01044"></a>01044 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0010</span>;
|
| 1048 |
|
|
<a name="l01045"></a>01045 <span class="vhdlkeyword">end</span>
|
| 1049 |
|
|
<a name="l01046"></a>01046 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b01</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1050 |
|
|
<a name="l01047"></a>01047 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">8'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1051 |
|
|
<a name="l01048"></a>01048 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0100</span>;
|
| 1052 |
|
|
<a name="l01049"></a>01049 <span class="vhdlkeyword">end</span>
|
| 1053 |
|
|
<a name="l01050"></a>01050 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1054 |
|
|
<a name="l01051"></a>01051 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">24'b0</span> };
|
| 1055 |
|
|
<a name="l01052"></a>01052 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1000</span>;
|
| 1056 |
|
|
<a name="l01053"></a>01053 <span class="vhdlkeyword">end</span>
|
| 1057 |
|
|
<a name="l01054"></a>01054
|
| 1058 |
|
|
<a name="l01055"></a>01055 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1059 |
|
|
<a name="l01056"></a>01056 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1060 |
|
|
<a name="l01057"></a>01057 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1061 |
|
|
<a name="l01058"></a>01058 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1062 |
|
|
<a name="l01059"></a>01059 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1063 |
|
|
<a name="l01060"></a>01060 <span class="vhdlkeyword">end</span>
|
| 1064 |
|
|
<a name="l01061"></a>01061 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1065 |
|
|
<a name="l01062"></a>01062 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1066 |
|
|
<a name="l01063"></a>01063 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1067 |
|
|
<a name="l01064"></a>01064 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1068 |
|
|
<a name="l01065"></a>01065 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 1069 |
|
|
<a name="l01066"></a>01066 <span class="vhdlkeyword">end</span>
|
| 1070 |
|
|
<a name="l01067"></a>01067 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1071 |
|
|
<a name="l01068"></a>01068 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1072 |
|
|
<a name="l01069"></a>01069 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1073 |
|
|
<a name="l01070"></a>01070 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1074 |
|
|
<a name="l01071"></a>01071 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1075 |
|
|
<a name="l01072"></a>01072 <span class="vhdlkeyword">end</span>
|
| 1076 |
|
|
<a name="l01073"></a>01073
|
| 1077 |
|
|
<a name="l01074"></a>01074 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a47878ecd24d5368e7396dd97ec9f4077">S_WRITE_1</a>;
|
| 1078 |
|
|
<a name="l01075"></a>01075 <span class="vhdlkeyword">end</span>
|
| 1079 |
|
|
<a name="l01076"></a>01076 <span class="vhdlkeyword">end</span>
|
| 1080 |
|
|
<a name="l01077"></a>01077 <span class="keyword">// pc</span>
|
| 1081 |
|
|
<a name="l01078"></a>01078 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_o</span> == <span class="vhdllogic">1'b0</span> || <span class="vhdlchar">pc_change_i</span> != <span class="vhdllogic">2'b00</span>) <span class="vhdlkeyword">begin</span>
|
| 1082 |
|
|
<a name="l01079"></a>01079
|
| 1083 |
|
|
<a name="l01080"></a>01080 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_o</span> == <span class="vhdllogic">1'b0</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b10</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
|
| 1084 |
|
|
<a name="l01081"></a>01081 <span class="keyword">// load 4 words: [79:16] in 2,3 cycles</span>
|
| 1085 |
|
|
<a name="l01082"></a>01082 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1086 |
|
|
<a name="l01083"></a>01083 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1087 |
|
|
<a name="l01084"></a>01084 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1088 |
|
|
<a name="l01085"></a>01085
|
| 1089 |
|
|
<a name="l01086"></a>01086 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>;
|
| 1090 |
|
|
<a name="l01087"></a>01087 <span class="vhdlkeyword">end</span>
|
| 1091 |
|
|
<a name="l01088"></a>01088 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_80_o</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b01</span>) <span class="vhdlkeyword">begin</span>
|
| 1092 |
|
|
<a name="l01089"></a>01089 <span class="keyword">// load 2 words: [31:0] in 1 cycle</span>
|
| 1093 |
|
|
<a name="l01090"></a>01090 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1094 |
|
|
<a name="l01091"></a>01091 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1095 |
|
|
<a name="l01092"></a>01092 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1096 |
|
|
<a name="l01093"></a>01093
|
| 1097 |
|
|
<a name="l01094"></a>01094 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">63</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1098 |
|
|
<a name="l01095"></a>01095 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>;
|
| 1099 |
|
|
<a name="l01096"></a>01096 <span class="vhdlkeyword">end</span>
|
| 1100 |
|
|
<a name="l01097"></a>01097 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1101 |
|
|
<a name="l01098"></a>01098 <span class="keyword">// do not load any words</span>
|
| 1102 |
|
|
<a name="l01099"></a>01099 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1103 |
|
|
<a name="l01100"></a>01100 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1104 |
|
|
<a name="l01101"></a>01101 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1105 |
12 |
alfik |
<a name="l01102"></a>01102
|
| 1106 |
13 |
alfik |
<a name="l01103"></a>01103 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">63</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1107 |
|
|
<a name="l01104"></a>01104 <span class="vhdlkeyword">end</span>
|
| 1108 |
|
|
<a name="l01105"></a>01105
|
| 1109 |
|
|
<a name="l01106"></a>01106
|
| 1110 |
|
|
<a name="l01107"></a>01107 <span class="vhdlkeyword">end</span>
|
| 1111 |
|
|
<a name="l01108"></a>01108 <span class="keyword">// interrupt</span>
|
| 1112 |
|
|
<a name="l01109"></a>01109 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1113 |
|
|
<a name="l01110"></a>01110 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1114 |
|
|
<a name="l01111"></a>01111 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= { <span class="vhdllogic">27'b111_1111_1111_1111_1111_1111_1111</span>, <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> };
|
| 1115 |
|
|
<a name="l01112"></a>01112 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 1116 |
|
|
<a name="l01113"></a>01113 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1117 |
|
|
<a name="l01114"></a>01114 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1118 |
|
|
<a name="l01115"></a>01115
|
| 1119 |
|
|
<a name="l01116"></a>01116 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1120 |
|
|
<a name="l01117"></a>01117 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1121 |
|
|
<a name="l01118"></a>01118 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1122 |
|
|
<a name="l01119"></a>01119 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1123 |
|
|
<a name="l01120"></a>01120
|
| 1124 |
|
|
<a name="l01121"></a>01121 <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#aabcbc5528d37aad94c1c91f72abe9788">FC_CPU_SPACE</a>;
|
| 1125 |
|
|
<a name="l01122"></a>01122
|
| 1126 |
|
|
<a name="l01123"></a>01123 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a22028b6e9c3a87066084eeb7e3ea66dc">S_INT_1</a>;
|
| 1127 |
|
|
<a name="l01124"></a>01124 <span class="vhdlkeyword">end</span>
|
| 1128 |
|
|
<a name="l01125"></a>01125 <span class="vhdlkeyword">end</span>
|
| 1129 |
12 |
alfik |
<a name="l01126"></a>01126
|
| 1130 |
13 |
alfik |
<a name="l01127"></a>01127 <a class="code" href="classbus__control.html#a21f9753bb3594dcc9d190ef5c54071e6">S_RESET</a>: <span class="vhdlkeyword">begin</span>
|
| 1131 |
|
|
<a name="l01128"></a>01128 <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> <= <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> - <span class="vhdllogic">8'd1</span>;
|
| 1132 |
|
|
<a name="l01129"></a>01129
|
| 1133 |
|
|
<a name="l01130"></a>01130 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> == <span class="vhdllogic">8'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 1134 |
|
|
<a name="l01131"></a>01131 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1135 |
|
|
<a name="l01132"></a>01132 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1136 |
|
|
<a name="l01133"></a>01133 <span class="vhdlkeyword">end</span>
|
| 1137 |
12 |
alfik |
<a name="l01134"></a>01134 <span class="vhdlkeyword">end</span>
|
| 1138 |
|
|
<a name="l01135"></a>01135
|
| 1139 |
13 |
alfik |
<a name="l01136"></a>01136 <a class="code" href="classbus__control.html#a35c0778e16a225b839acc35705428b6a">S_BLOCKED</a>: <span class="vhdlkeyword">begin</span>
|
| 1140 |
|
|
<a name="l01137"></a>01137 <span class="vhdlkeyword">end</span>
|
| 1141 |
|
|
<a name="l01138"></a>01138
|
| 1142 |
|
|
<a name="l01139"></a>01139 <a class="code" href="classbus__control.html#a22028b6e9c3a87066084eeb7e3ea66dc">S_INT_1</a>: <span class="vhdlkeyword">begin</span>
|
| 1143 |
|
|
<a name="l01140"></a>01140 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1144 |
|
|
<a name="l01141"></a>01141 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1145 |
|
|
<a name="l01142"></a>01142 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1146 |
|
|
<a name="l01143"></a>01143
|
| 1147 |
|
|
<a name="l01144"></a>01144 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 1148 |
|
|
<a name="l01145"></a>01145
|
| 1149 |
|
|
<a name="l01146"></a>01146 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1150 |
|
|
<a name="l01147"></a>01147 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1151 |
|
|
<a name="l01148"></a>01148 <span class="vhdlkeyword">end</span>
|
| 1152 |
|
|
<a name="l01149"></a>01149 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1153 |
|
|
<a name="l01150"></a>01150 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1154 |
|
|
<a name="l01151"></a>01151 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1155 |
|
|
<a name="l01152"></a>01152
|
| 1156 |
|
|
<a name="l01153"></a>01153 <span class="vhdlchar">interrupt_trap_o</span> <= <span class="vhdllogic">8'd24</span> + { <span class="vhdllogic">5'b0</span>, <span class="vhdlchar">interrupt_mask_o</span> };
|
| 1157 |
|
|
<a name="l01154"></a>01154
|
| 1158 |
|
|
<a name="l01155"></a>01155 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1159 |
|
|
<a name="l01156"></a>01156 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1160 |
|
|
<a name="l01157"></a>01157 <span class="vhdlkeyword">end</span>
|
| 1161 |
|
|
<a name="l01158"></a>01158 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1162 |
|
|
<a name="l01159"></a>01159 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1163 |
|
|
<a name="l01160"></a>01160 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1164 |
|
|
<a name="l01161"></a>01161
|
| 1165 |
|
|
<a name="l01162"></a>01162 <span class="vhdlchar">interrupt_trap_o</span> <= <span class="vhdllogic">8'd24</span>; <span class="keyword">// spurious interrupt</span>
|
| 1166 |
|
|
<a name="l01163"></a>01163
|
| 1167 |
|
|
<a name="l01164"></a>01164 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1168 |
|
|
<a name="l01165"></a>01165 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1169 |
|
|
<a name="l01166"></a>01166 <span class="vhdlkeyword">end</span>
|
| 1170 |
|
|
<a name="l01167"></a>01167 <span class="vhdlkeyword">end</span>
|
| 1171 |
|
|
<a name="l01168"></a>01168
|
| 1172 |
|
|
<a name="l01169"></a>01169 <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>: <span class="vhdlkeyword">begin</span>
|
| 1173 |
|
|
<a name="l01170"></a>01170 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1174 |
|
|
<a name="l01171"></a>01171 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a>;
|
| 1175 |
|
|
<a name="l01172"></a>01172 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>;
|
| 1176 |
|
|
<a name="l01173"></a>01173
|
| 1177 |
|
|
<a name="l01174"></a>01174 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1178 |
|
|
<a name="l01175"></a>01175 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1179 |
|
|
<a name="l01176"></a>01176 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1180 |
|
|
<a name="l01177"></a>01177 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1181 |
|
|
<a name="l01178"></a>01178
|
| 1182 |
|
|
<a name="l01179"></a>01179 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdlchar">pc_i</span>;
|
| 1183 |
|
|
<a name="l01180"></a>01180 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1184 |
|
|
<a name="l01181"></a>01181 <span class="vhdlchar">fc_state_o</span> <= (<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a> : <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>;
|
| 1185 |
|
|
<a name="l01182"></a>01182 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a>;
|
| 1186 |
|
|
<a name="l01183"></a>01183
|
| 1187 |
|
|
<a name="l01184"></a>01184 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1188 |
|
|
<a name="l01185"></a>01185 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1189 |
|
|
<a name="l01186"></a>01186 <span class="vhdlkeyword">end</span>
|
| 1190 |
|
|
<a name="l01187"></a>01187 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1191 |
|
|
<a name="l01188"></a>01188 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1192 |
12 |
alfik |
<a name="l01189"></a>01189
|
| 1193 |
13 |
alfik |
<a name="l01190"></a>01190 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_32_o</span> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdlchar">pc_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 1194 |
|
|
<a name="l01191"></a>01191 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 1195 |
|
|
<a name="l01192"></a>01192
|
| 1196 |
|
|
<a name="l01193"></a>01193 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= (<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>)? <span class="vhdllogic">4'b0011</span> :
|
| 1197 |
|
|
<a name="l01194"></a>01194 <span class="vhdllogic">4'b1111</span>;
|
| 1198 |
|
|
<a name="l01195"></a>01195 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1199 |
|
|
<a name="l01196"></a>01196
|
| 1200 |
|
|
<a name="l01197"></a>01197 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_32_o</span> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 1201 |
|
|
<a name="l01198"></a>01198 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1202 |
|
|
<a name="l01199"></a>01199 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1203 |
|
|
<a name="l01200"></a>01200 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1204 |
|
|
<a name="l01201"></a>01201 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 1205 |
|
|
<a name="l01202"></a>01202 <span class="vhdlkeyword">end</span>
|
| 1206 |
|
|
<a name="l01203"></a>01203 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1207 |
|
|
<a name="l01204"></a>01204 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1208 |
|
|
<a name="l01205"></a>01205 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1209 |
|
|
<a name="l01206"></a>01206 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1210 |
|
|
<a name="l01207"></a>01207 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1211 |
|
|
<a name="l01208"></a>01208 <span class="vhdlkeyword">end</span>
|
| 1212 |
12 |
alfik |
<a name="l01209"></a>01209
|
| 1213 |
13 |
alfik |
<a name="l01210"></a>01210 <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> <= <span class="vhdlchar">pc_change_i</span>;
|
| 1214 |
|
|
<a name="l01211"></a>01211 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1215 |
|
|
<a name="l01212"></a>01212
|
| 1216 |
|
|
<a name="l01213"></a>01213 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a>;
|
| 1217 |
|
|
<a name="l01214"></a>01214 <span class="vhdlkeyword">end</span>
|
| 1218 |
|
|
<a name="l01215"></a>01215 <span class="vhdlkeyword">end</span>
|
| 1219 |
12 |
alfik |
<a name="l01216"></a>01216
|
| 1220 |
13 |
alfik |
<a name="l01217"></a>01217 <a class="code" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a>: <span class="vhdlkeyword">begin</span>
|
| 1221 |
|
|
<a name="l01218"></a>01218 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_change_i</span> != <span class="vhdllogic">2'b00</span>) <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> <= <span class="vhdlchar">pc_change_i</span>;
|
| 1222 |
|
|
<a name="l01219"></a>01219
|
| 1223 |
|
|
<a name="l01220"></a>01220 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1224 |
|
|
<a name="l01221"></a>01221 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> == <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>) <span class="vhdlkeyword">begin</span>
|
| 1225 |
|
|
<a name="l01222"></a>01222 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 1226 |
|
|
<a name="l01223"></a>01223 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#ad4e505c885a6c941198d653beff91bf1">pc_i_plus_4</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 1227 |
|
|
<a name="l01224"></a>01224 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 1228 |
|
|
<a name="l01225"></a>01225 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 1229 |
|
|
<a name="l01226"></a>01226 <span class="keyword">//WE_O <= 1'b0;</span>
|
| 1230 |
|
|
<a name="l01227"></a>01227
|
| 1231 |
|
|
<a name="l01228"></a>01228 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>) <span class="vhdlkeyword">begin</span>
|
| 1232 |
|
|
<a name="l01229"></a>01229 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1233 |
|
|
<a name="l01230"></a>01230 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1234 |
|
|
<a name="l01231"></a>01231 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1235 |
|
|
<a name="l01232"></a>01232 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 1236 |
|
|
<a name="l01233"></a>01233 <span class="vhdlkeyword">end</span>
|
| 1237 |
|
|
<a name="l01234"></a>01234 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1238 |
|
|
<a name="l01235"></a>01235 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1239 |
|
|
<a name="l01236"></a>01236 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1240 |
|
|
<a name="l01237"></a>01237 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1241 |
|
|
<a name="l01238"></a>01238 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1242 |
|
|
<a name="l01239"></a>01239 <span class="vhdlkeyword">end</span>
|
| 1243 |
12 |
alfik |
<a name="l01240"></a>01240
|
| 1244 |
13 |
alfik |
<a name="l01241"></a>01241 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;</span>
|
| 1245 |
|
|
<a name="l01242"></a>01242 <span class="keyword">//else fc_o <= FC_USER_PROGRAM;</span>
|
| 1246 |
12 |
alfik |
<a name="l01243"></a>01243
|
| 1247 |
13 |
alfik |
<a name="l01244"></a>01244 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>) <span class="vhdlchar">prefetch_ir_o</span> <= { <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">64'b0</span> };
|
| 1248 |
|
|
<a name="l01245"></a>01245 <span class="vhdlkeyword">else</span> <span class="vhdlchar">prefetch_ir_o</span> <= { <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">48'b0</span> };
|
| 1249 |
|
|
<a name="l01246"></a>01246
|
| 1250 |
|
|
<a name="l01247"></a>01247 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a>;
|
| 1251 |
|
|
<a name="l01248"></a>01248 <span class="vhdlkeyword">end</span>
|
| 1252 |
|
|
<a name="l01249"></a>01249 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1253 |
|
|
<a name="l01250"></a>01250 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1254 |
|
|
<a name="l01251"></a>01251 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1255 |
|
|
<a name="l01252"></a>01252
|
| 1256 |
|
|
<a name="l01253"></a>01253 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> == <span class="vhdllogic">2'b10</span> || <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> == <span class="vhdllogic">2'b11</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b10</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
|
| 1257 |
|
|
<a name="l01254"></a>01254 <span class="keyword">// load 4 words: [79:16] in 2,3 cycles</span>
|
| 1258 |
|
|
<a name="l01255"></a>01255 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1259 |
|
|
<a name="l01256"></a>01256 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1260 |
|
|
<a name="l01257"></a>01257 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1261 |
|
|
<a name="l01258"></a>01258
|
| 1262 |
|
|
<a name="l01259"></a>01259 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>;
|
| 1263 |
|
|
<a name="l01260"></a>01260 <span class="vhdlkeyword">end</span>
|
| 1264 |
|
|
<a name="l01261"></a>01261 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> == <span class="vhdllogic">2'b01</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b01</span>) <span class="vhdlkeyword">begin</span>
|
| 1265 |
|
|
<a name="l01262"></a>01262 <span class="keyword">// do not load any words</span>
|
| 1266 |
|
|
<a name="l01263"></a>01263 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1267 |
|
|
<a name="l01264"></a>01264 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1268 |
|
|
<a name="l01265"></a>01265 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1269 |
|
|
<a name="l01266"></a>01266
|
| 1270 |
|
|
<a name="l01267"></a>01267 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">63</span>:<span class="vhdllogic">32</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1271 |
|
|
<a name="l01268"></a>01268 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 1272 |
|
|
<a name="l01269"></a>01269 <span class="vhdlkeyword">end</span>
|
| 1273 |
|
|
<a name="l01270"></a>01270 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1274 |
|
|
<a name="l01271"></a>01271 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1275 |
|
|
<a name="l01272"></a>01272 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1276 |
|
|
<a name="l01273"></a>01273 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1277 |
|
|
<a name="l01274"></a>01274
|
| 1278 |
|
|
<a name="l01275"></a>01275 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">32</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] };
|
| 1279 |
|
|
<a name="l01276"></a>01276 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 1280 |
|
|
<a name="l01277"></a>01277 <span class="vhdlkeyword">end</span>
|
| 1281 |
|
|
<a name="l01278"></a>01278 <span class="vhdlkeyword">end</span>
|
| 1282 |
|
|
<a name="l01279"></a>01279 <span class="vhdlkeyword">end</span>
|
| 1283 |
|
|
<a name="l01280"></a>01280 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1284 |
|
|
<a name="l01281"></a>01281 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1285 |
|
|
<a name="l01282"></a>01282 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1286 |
|
|
<a name="l01283"></a>01283
|
| 1287 |
|
|
<a name="l01284"></a>01284 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a4b9998b72c69db4dcd98755835413fda">S_PC_2</a>;
|
| 1288 |
|
|
<a name="l01285"></a>01285 <span class="vhdlkeyword">end</span>
|
| 1289 |
|
|
<a name="l01286"></a>01286 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1290 |
|
|
<a name="l01287"></a>01287 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1291 |
|
|
<a name="l01288"></a>01288 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1292 |
|
|
<a name="l01289"></a>01289
|
| 1293 |
|
|
<a name="l01290"></a>01290 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 1294 |
|
|
<a name="l01291"></a>01291 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 1295 |
|
|
<a name="l01292"></a>01292 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 1296 |
|
|
<a name="l01293"></a>01293 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 1297 |
|
|
<a name="l01294"></a>01294
|
| 1298 |
|
|
<a name="l01295"></a>01295 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1299 |
|
|
<a name="l01296"></a>01296 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1300 |
|
|
<a name="l01297"></a>01297 <span class="vhdlkeyword">end</span>
|
| 1301 |
|
|
<a name="l01298"></a>01298 <span class="vhdlkeyword">end</span>
|
| 1302 |
|
|
<a name="l01299"></a>01299 <a class="code" href="classbus__control.html#a4b9998b72c69db4dcd98755835413fda">S_PC_2</a>: <span class="vhdlkeyword">begin</span>
|
| 1303 |
|
|
<a name="l01300"></a>01300 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1304 |
|
|
<a name="l01301"></a>01301 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1305 |
|
|
<a name="l01302"></a>01302
|
| 1306 |
|
|
<a name="l01303"></a>01303 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a>;
|
| 1307 |
|
|
<a name="l01304"></a>01304 <span class="vhdlkeyword">end</span>
|
| 1308 |
|
|
<a name="l01305"></a>01305 <a class="code" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a>: <span class="vhdlkeyword">begin</span>
|
| 1309 |
|
|
<a name="l01306"></a>01306 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1310 |
|
|
<a name="l01307"></a>01307 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>) <span class="vhdlkeyword">begin</span>
|
| 1311 |
|
|
<a name="l01308"></a>01308 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 1312 |
|
|
<a name="l01309"></a>01309 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 1313 |
|
|
<a name="l01310"></a>01310 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 1314 |
|
|
<a name="l01311"></a>01311 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 1315 |
|
|
<a name="l01312"></a>01312 <span class="keyword">//WE_O <= 1'b0;</span>
|
| 1316 |
|
|
<a name="l01313"></a>01313
|
| 1317 |
|
|
<a name="l01314"></a>01314 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1318 |
|
|
<a name="l01315"></a>01315 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1319 |
|
|
<a name="l01316"></a>01316 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1320 |
|
|
<a name="l01317"></a>01317 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1321 |
12 |
alfik |
<a name="l01318"></a>01318
|
| 1322 |
13 |
alfik |
<a name="l01319"></a>01319 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;</span>
|
| 1323 |
|
|
<a name="l01320"></a>01320 <span class="keyword">//else fc_o <= FC_USER_PROGRAM;</span>
|
| 1324 |
|
|
<a name="l01321"></a>01321
|
| 1325 |
|
|
<a name="l01322"></a>01322 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">32'b0</span> };
|
| 1326 |
|
|
<a name="l01323"></a>01323
|
| 1327 |
|
|
<a name="l01324"></a>01324 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a>;
|
| 1328 |
|
|
<a name="l01325"></a>01325 <span class="vhdlkeyword">end</span>
|
| 1329 |
|
|
<a name="l01326"></a>01326 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1330 |
|
|
<a name="l01327"></a>01327 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1331 |
|
|
<a name="l01328"></a>01328 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1332 |
|
|
<a name="l01329"></a>01329
|
| 1333 |
|
|
<a name="l01330"></a>01330 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1334 |
|
|
<a name="l01331"></a>01331
|
| 1335 |
|
|
<a name="l01332"></a>01332 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1336 |
|
|
<a name="l01333"></a>01333 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1337 |
|
|
<a name="l01334"></a>01334 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1338 |
|
|
<a name="l01335"></a>01335 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 1339 |
|
|
<a name="l01336"></a>01336 <span class="vhdlkeyword">end</span>
|
| 1340 |
|
|
<a name="l01337"></a>01337 <span class="vhdlkeyword">end</span>
|
| 1341 |
|
|
<a name="l01338"></a>01338 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1342 |
|
|
<a name="l01339"></a>01339 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1343 |
|
|
<a name="l01340"></a>01340 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1344 |
|
|
<a name="l01341"></a>01341
|
| 1345 |
|
|
<a name="l01342"></a>01342 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#aec52b8e16695194dcbfefab239d8a94a">S_PC_4</a>;
|
| 1346 |
|
|
<a name="l01343"></a>01343 <span class="vhdlkeyword">end</span>
|
| 1347 |
|
|
<a name="l01344"></a>01344 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1348 |
|
|
<a name="l01345"></a>01345 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1349 |
|
|
<a name="l01346"></a>01346 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1350 |
|
|
<a name="l01347"></a>01347
|
| 1351 |
|
|
<a name="l01348"></a>01348 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 1352 |
|
|
<a name="l01349"></a>01349 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 1353 |
|
|
<a name="l01350"></a>01350 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 1354 |
|
|
<a name="l01351"></a>01351 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 1355 |
|
|
<a name="l01352"></a>01352
|
| 1356 |
|
|
<a name="l01353"></a>01353 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1357 |
|
|
<a name="l01354"></a>01354 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1358 |
|
|
<a name="l01355"></a>01355 <span class="vhdlkeyword">end</span>
|
| 1359 |
|
|
<a name="l01356"></a>01356 <span class="vhdlkeyword">end</span>
|
| 1360 |
|
|
<a name="l01357"></a>01357 <a class="code" href="classbus__control.html#aec52b8e16695194dcbfefab239d8a94a">S_PC_4</a>: <span class="vhdlkeyword">begin</span>
|
| 1361 |
|
|
<a name="l01358"></a>01358 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1362 |
|
|
<a name="l01359"></a>01359 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1363 |
|
|
<a name="l01360"></a>01360
|
| 1364 |
|
|
<a name="l01361"></a>01361 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a>;
|
| 1365 |
|
|
<a name="l01362"></a>01362 <span class="vhdlkeyword">end</span>
|
| 1366 |
|
|
<a name="l01363"></a>01363 <a class="code" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a>: <span class="vhdlkeyword">begin</span>
|
| 1367 |
|
|
<a name="l01364"></a>01364 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1368 |
|
|
<a name="l01365"></a>01365 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1369 |
|
|
<a name="l01366"></a>01366 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1370 |
|
|
<a name="l01367"></a>01367
|
| 1371 |
|
|
<a name="l01368"></a>01368 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">32</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] };
|
| 1372 |
|
|
<a name="l01369"></a>01369
|
| 1373 |
|
|
<a name="l01370"></a>01370 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1374 |
|
|
<a name="l01371"></a>01371 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1375 |
|
|
<a name="l01372"></a>01372 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1376 |
|
|
<a name="l01373"></a>01373 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 1377 |
|
|
<a name="l01374"></a>01374 <span class="vhdlkeyword">end</span>
|
| 1378 |
|
|
<a name="l01375"></a>01375 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1379 |
|
|
<a name="l01376"></a>01376 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1380 |
|
|
<a name="l01377"></a>01377 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1381 |
|
|
<a name="l01378"></a>01378
|
| 1382 |
|
|
<a name="l01379"></a>01379 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a95ac5f10cc1642a474302d109678e2c2">S_PC_6</a>;
|
| 1383 |
|
|
<a name="l01380"></a>01380 <span class="vhdlkeyword">end</span>
|
| 1384 |
|
|
<a name="l01381"></a>01381 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1385 |
|
|
<a name="l01382"></a>01382 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1386 |
|
|
<a name="l01383"></a>01383 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1387 |
|
|
<a name="l01384"></a>01384
|
| 1388 |
|
|
<a name="l01385"></a>01385 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 1389 |
|
|
<a name="l01386"></a>01386 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 1390 |
|
|
<a name="l01387"></a>01387 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 1391 |
|
|
<a name="l01388"></a>01388 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 1392 |
|
|
<a name="l01389"></a>01389
|
| 1393 |
|
|
<a name="l01390"></a>01390 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1394 |
|
|
<a name="l01391"></a>01391 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1395 |
|
|
<a name="l01392"></a>01392 <span class="vhdlkeyword">end</span>
|
| 1396 |
|
|
<a name="l01393"></a>01393 <span class="vhdlkeyword">end</span>
|
| 1397 |
|
|
<a name="l01394"></a>01394 <a class="code" href="classbus__control.html#a95ac5f10cc1642a474302d109678e2c2">S_PC_6</a>: <span class="vhdlkeyword">begin</span>
|
| 1398 |
|
|
<a name="l01395"></a>01395 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1399 |
|
|
<a name="l01396"></a>01396 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1400 |
12 |
alfik |
<a name="l01397"></a>01397
|
| 1401 |
13 |
alfik |
<a name="l01398"></a>01398 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a>;
|
| 1402 |
|
|
<a name="l01399"></a>01399 <span class="vhdlkeyword">end</span>
|
| 1403 |
|
|
<a name="l01400"></a>01400
|
| 1404 |
|
|
<a name="l01401"></a>01401 <span class="keyword">//*******************</span>
|
| 1405 |
|
|
<a name="l01402"></a>01402 <a class="code" href="classbus__control.html#a0957d5175230f9062a95b56e1db2fc53">S_READ_1</a>: <span class="vhdlkeyword">begin</span>
|
| 1406 |
|
|
<a name="l01403"></a>01403 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1407 |
|
|
<a name="l01404"></a>01404 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1408 |
|
|
<a name="l01405"></a>01405 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 1409 |
|
|
<a name="l01406"></a>01406 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 1410 |
|
|
<a name="l01407"></a>01407 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1100</span>;
|
| 1411 |
|
|
<a name="l01408"></a>01408 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 1412 |
|
|
<a name="l01409"></a>01409 <span class="keyword">//WE_O <= 1'b0;</span>
|
| 1413 |
|
|
<a name="l01410"></a>01410
|
| 1414 |
|
|
<a name="l01411"></a>01411 <span class="keyword">//SGL_O <= 1'b0;</span>
|
| 1415 |
|
|
<a name="l01412"></a>01412 <span class="keyword">//BLK_O <= 1'b1;</span>
|
| 1416 |
|
|
<a name="l01413"></a>01413 <span class="keyword">//RMW_O <= 1'b0;</span>
|
| 1417 |
|
|
<a name="l01414"></a>01414 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1418 |
12 |
alfik |
<a name="l01415"></a>01415
|
| 1419 |
13 |
alfik |
<a name="l01416"></a>01416 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;</span>
|
| 1420 |
|
|
<a name="l01417"></a>01417 <span class="keyword">//else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;</span>
|
| 1421 |
|
|
<a name="l01418"></a>01418
|
| 1422 |
|
|
<a name="l01419"></a>01419 <span class="vhdlchar">data_read_o</span> <= { <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1423 |
|
|
<a name="l01420"></a>01420
|
| 1424 |
|
|
<a name="l01421"></a>01421 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a>;
|
| 1425 |
|
|
<a name="l01422"></a>01422 <span class="vhdlkeyword">end</span>
|
| 1426 |
|
|
<a name="l01423"></a>01423 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1427 |
|
|
<a name="l01424"></a>01424 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1428 |
|
|
<a name="l01425"></a>01425 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1429 |
|
|
<a name="l01426"></a>01426 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1430 |
|
|
<a name="l01427"></a>01427 <span class="vhdlkeyword">end</span>
|
| 1431 |
|
|
<a name="l01428"></a>01428 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1432 |
|
|
<a name="l01429"></a>01429 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1433 |
|
|
<a name="l01430"></a>01430 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1434 |
|
|
<a name="l01431"></a>01431 <span class="vhdlkeyword">end</span>
|
| 1435 |
|
|
<a name="l01432"></a>01432
|
| 1436 |
|
|
<a name="l01433"></a>01433 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 1437 |
|
|
<a name="l01434"></a>01434 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 1438 |
|
|
<a name="l01435"></a>01435 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 1439 |
|
|
<a name="l01436"></a>01436 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 1440 |
|
|
<a name="l01437"></a>01437 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] };
|
| 1441 |
|
|
<a name="l01438"></a>01438 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b01</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">23</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] };
|
| 1442 |
|
|
<a name="l01439"></a>01439 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] };
|
| 1443 |
|
|
<a name="l01440"></a>01440
|
| 1444 |
|
|
<a name="l01441"></a>01441 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1445 |
|
|
<a name="l01442"></a>01442 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1446 |
|
|
<a name="l01443"></a>01443 <span class="vhdlkeyword">end</span>
|
| 1447 |
|
|
<a name="l01444"></a>01444 <span class="vhdlkeyword">end</span>
|
| 1448 |
|
|
<a name="l01445"></a>01445 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1449 |
|
|
<a name="l01446"></a>01446 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1450 |
|
|
<a name="l01447"></a>01447 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1451 |
|
|
<a name="l01448"></a>01448
|
| 1452 |
|
|
<a name="l01449"></a>01449 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 1453 |
|
|
<a name="l01450"></a>01450 <span class="vhdlkeyword">end</span>
|
| 1454 |
|
|
<a name="l01451"></a>01451 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1455 |
|
|
<a name="l01452"></a>01452 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1456 |
|
|
<a name="l01453"></a>01453 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1457 |
|
|
<a name="l01454"></a>01454
|
| 1458 |
|
|
<a name="l01455"></a>01455 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 1459 |
|
|
<a name="l01456"></a>01456 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 1460 |
|
|
<a name="l01457"></a>01457 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 1461 |
|
|
<a name="l01458"></a>01458 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 1462 |
|
|
<a name="l01459"></a>01459
|
| 1463 |
|
|
<a name="l01460"></a>01460 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1464 |
|
|
<a name="l01461"></a>01461 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1465 |
|
|
<a name="l01462"></a>01462 <span class="vhdlkeyword">end</span>
|
| 1466 |
|
|
<a name="l01463"></a>01463 <span class="vhdlkeyword">end</span>
|
| 1467 |
|
|
<a name="l01464"></a>01464 <a class="code" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a>: <span class="vhdlkeyword">begin</span>
|
| 1468 |
|
|
<a name="l01465"></a>01465 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1469 |
|
|
<a name="l01466"></a>01466 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1470 |
|
|
<a name="l01467"></a>01467 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1471 |
|
|
<a name="l01468"></a>01468
|
| 1472 |
|
|
<a name="l01469"></a>01469 <span class="vhdlchar">data_read_o</span> <= { <span class="vhdlchar">data_read_o</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 1473 |
12 |
alfik |
<a name="l01470"></a>01470
|
| 1474 |
13 |
alfik |
<a name="l01471"></a>01471 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1475 |
|
|
<a name="l01472"></a>01472 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1476 |
|
|
<a name="l01473"></a>01473
|
| 1477 |
|
|
<a name="l01474"></a>01474 <span class="vhdlkeyword">end</span>
|
| 1478 |
|
|
<a name="l01475"></a>01475 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1479 |
|
|
<a name="l01476"></a>01476 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1480 |
|
|
<a name="l01477"></a>01477 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1481 |
|
|
<a name="l01478"></a>01478
|
| 1482 |
|
|
<a name="l01479"></a>01479 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#ae156bee4c9bdf06b34803d8d68d9f50f">S_READ_3</a>;
|
| 1483 |
|
|
<a name="l01480"></a>01480 <span class="vhdlkeyword">end</span>
|
| 1484 |
|
|
<a name="l01481"></a>01481 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1485 |
|
|
<a name="l01482"></a>01482 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1486 |
|
|
<a name="l01483"></a>01483 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1487 |
|
|
<a name="l01484"></a>01484
|
| 1488 |
|
|
<a name="l01485"></a>01485 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 1489 |
|
|
<a name="l01486"></a>01486 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 1490 |
|
|
<a name="l01487"></a>01487 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 1491 |
|
|
<a name="l01488"></a>01488 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 1492 |
|
|
<a name="l01489"></a>01489
|
| 1493 |
|
|
<a name="l01490"></a>01490 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1494 |
|
|
<a name="l01491"></a>01491 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1495 |
|
|
<a name="l01492"></a>01492 <span class="vhdlkeyword">end</span>
|
| 1496 |
|
|
<a name="l01493"></a>01493
|
| 1497 |
|
|
<a name="l01494"></a>01494 <span class="vhdlkeyword">end</span>
|
| 1498 |
|
|
<a name="l01495"></a>01495 <a class="code" href="classbus__control.html#ae156bee4c9bdf06b34803d8d68d9f50f">S_READ_3</a>: <span class="vhdlkeyword">begin</span>
|
| 1499 |
|
|
<a name="l01496"></a>01496 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1500 |
|
|
<a name="l01497"></a>01497 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1501 |
12 |
alfik |
<a name="l01498"></a>01498
|
| 1502 |
13 |
alfik |
<a name="l01499"></a>01499 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a>;
|
| 1503 |
|
|
<a name="l01500"></a>01500 <span class="vhdlkeyword">end</span>
|
| 1504 |
|
|
<a name="l01501"></a>01501
|
| 1505 |
|
|
<a name="l01502"></a>01502
|
| 1506 |
|
|
<a name="l01503"></a>01503 <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>: <span class="vhdlkeyword">begin</span>
|
| 1507 |
|
|
<a name="l01504"></a>01504 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1508 |
|
|
<a name="l01505"></a>01505 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1509 |
|
|
<a name="l01506"></a>01506
|
| 1510 |
|
|
<a name="l01507"></a>01507 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_i</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">do_write_i</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">do_reset_i</span> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 1511 |
|
|
<a name="l01508"></a>01508 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1512 |
|
|
<a name="l01509"></a>01509 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 1513 |
|
|
<a name="l01510"></a>01510 <span class="vhdlkeyword">end</span>
|
| 1514 |
|
|
<a name="l01511"></a>01511 <span class="vhdlkeyword">end</span>
|
| 1515 |
|
|
<a name="l01512"></a>01512
|
| 1516 |
|
|
<a name="l01513"></a>01513 <span class="keyword">//**********************</span>
|
| 1517 |
|
|
<a name="l01514"></a>01514 <a class="code" href="classbus__control.html#a47878ecd24d5368e7396dd97ec9f4077">S_WRITE_1</a>: <span class="vhdlkeyword">begin</span>
|
| 1518 |
|
|
<a name="l01515"></a>01515 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1519 |
|
|
<a name="l01516"></a>01516 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1520 |
|
|
<a name="l01517"></a>01517 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 1521 |
|
|
<a name="l01518"></a>01518 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 1522 |
|
|
<a name="l01519"></a>01519 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 1523 |
|
|
<a name="l01520"></a>01520 <span class="keyword">//WE_O <= 1'b1;</span>
|
| 1524 |
12 |
alfik |
<a name="l01521"></a>01521
|
| 1525 |
13 |
alfik |
<a name="l01522"></a>01522 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 1526 |
|
|
<a name="l01523"></a>01523 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1100</span>;
|
| 1527 |
|
|
<a name="l01524"></a>01524
|
| 1528 |
|
|
<a name="l01525"></a>01525 <span class="keyword">//SGL_O <= 1'b0;</span>
|
| 1529 |
|
|
<a name="l01526"></a>01526 <span class="keyword">//BLK_O <= 1'b1;</span>
|
| 1530 |
|
|
<a name="l01527"></a>01527 <span class="keyword">//RMW_O <= 1'b0;</span>
|
| 1531 |
|
|
<a name="l01528"></a>01528 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 1532 |
12 |
alfik |
<a name="l01529"></a>01529
|
| 1533 |
13 |
alfik |
<a name="l01530"></a>01530 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;</span>
|
| 1534 |
|
|
<a name="l01531"></a>01531 <span class="keyword">//else fc_o <= FC_USER_DATA;</span>
|
| 1535 |
|
|
<a name="l01532"></a>01532
|
| 1536 |
|
|
<a name="l01533"></a>01533 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a>;
|
| 1537 |
|
|
<a name="l01534"></a>01534 <span class="vhdlkeyword">end</span>
|
| 1538 |
|
|
<a name="l01535"></a>01535 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1539 |
|
|
<a name="l01536"></a>01536 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1540 |
|
|
<a name="l01537"></a>01537 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1541 |
|
|
<a name="l01538"></a>01538
|
| 1542 |
|
|
<a name="l01539"></a>01539 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1543 |
|
|
<a name="l01540"></a>01540 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1544 |
|
|
<a name="l01541"></a>01541 <span class="vhdlkeyword">end</span>
|
| 1545 |
|
|
<a name="l01542"></a>01542 <span class="vhdlkeyword">end</span>
|
| 1546 |
|
|
<a name="l01543"></a>01543 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1547 |
|
|
<a name="l01544"></a>01544 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1548 |
|
|
<a name="l01545"></a>01545 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1549 |
|
|
<a name="l01546"></a>01546
|
| 1550 |
|
|
<a name="l01547"></a>01547 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 1551 |
|
|
<a name="l01548"></a>01548 <span class="vhdlkeyword">end</span>
|
| 1552 |
|
|
<a name="l01549"></a>01549 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1553 |
|
|
<a name="l01550"></a>01550 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1554 |
|
|
<a name="l01551"></a>01551 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1555 |
|
|
<a name="l01552"></a>01552
|
| 1556 |
|
|
<a name="l01553"></a>01553 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 1557 |
|
|
<a name="l01554"></a>01554 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 1558 |
|
|
<a name="l01555"></a>01555 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 1559 |
|
|
<a name="l01556"></a>01556 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 1560 |
|
|
<a name="l01557"></a>01557
|
| 1561 |
|
|
<a name="l01558"></a>01558 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1562 |
|
|
<a name="l01559"></a>01559 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1563 |
|
|
<a name="l01560"></a>01560 <span class="vhdlkeyword">end</span>
|
| 1564 |
|
|
<a name="l01561"></a>01561
|
| 1565 |
|
|
<a name="l01562"></a>01562 <span class="vhdlkeyword">end</span>
|
| 1566 |
|
|
<a name="l01563"></a>01563 <a class="code" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a>: <span class="vhdlkeyword">begin</span>
|
| 1567 |
|
|
<a name="l01564"></a>01564 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1568 |
|
|
<a name="l01565"></a>01565 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1569 |
|
|
<a name="l01566"></a>01566 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1570 |
12 |
alfik |
<a name="l01567"></a>01567
|
| 1571 |
13 |
alfik |
<a name="l01568"></a>01568 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1572 |
|
|
<a name="l01569"></a>01569 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1573 |
|
|
<a name="l01570"></a>01570
|
| 1574 |
|
|
<a name="l01571"></a>01571 <span class="vhdlkeyword">end</span>
|
| 1575 |
|
|
<a name="l01572"></a>01572 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1576 |
|
|
<a name="l01573"></a>01573 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1577 |
|
|
<a name="l01574"></a>01574 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1578 |
|
|
<a name="l01575"></a>01575
|
| 1579 |
|
|
<a name="l01576"></a>01576 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a7c1c733e80689349399716f442a5db8d">S_WRITE_3</a>;
|
| 1580 |
|
|
<a name="l01577"></a>01577 <span class="vhdlkeyword">end</span>
|
| 1581 |
|
|
<a name="l01578"></a>01578 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 1582 |
|
|
<a name="l01579"></a>01579 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1583 |
|
|
<a name="l01580"></a>01580 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 1584 |
|
|
<a name="l01581"></a>01581
|
| 1585 |
|
|
<a name="l01582"></a>01582 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 1586 |
|
|
<a name="l01583"></a>01583 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 1587 |
|
|
<a name="l01584"></a>01584 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 1588 |
|
|
<a name="l01585"></a>01585 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 1589 |
|
|
<a name="l01586"></a>01586
|
| 1590 |
|
|
<a name="l01587"></a>01587 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1591 |
|
|
<a name="l01588"></a>01588 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 1592 |
|
|
<a name="l01589"></a>01589 <span class="vhdlkeyword">end</span>
|
| 1593 |
|
|
<a name="l01590"></a>01590
|
| 1594 |
|
|
<a name="l01591"></a>01591 <span class="vhdlkeyword">end</span>
|
| 1595 |
|
|
<a name="l01592"></a>01592 <a class="code" href="classbus__control.html#a7c1c733e80689349399716f442a5db8d">S_WRITE_3</a>: <span class="vhdlkeyword">begin</span>
|
| 1596 |
|
|
<a name="l01593"></a>01593 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1597 |
|
|
<a name="l01594"></a>01594 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 1598 |
12 |
alfik |
<a name="l01595"></a>01595
|
| 1599 |
13 |
alfik |
<a name="l01596"></a>01596 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a>;
|
| 1600 |
|
|
<a name="l01597"></a>01597 <span class="vhdlkeyword">end</span>
|
| 1601 |
|
|
<a name="l01598"></a>01598
|
| 1602 |
|
|
<a name="l01599"></a>01599 <span class="vhdlkeyword">endcase</span>
|
| 1603 |
|
|
<a name="l01600"></a>01600 <span class="vhdlkeyword">end</span>
|
| 1604 |
|
|
<a name="l01601"></a>01601 <span class="vhdlkeyword">end</span>
|
| 1605 |
|
|
<a name="l01602"></a>01602
|
| 1606 |
|
|
<a name="l01603"></a>01603 <span class="vhdlkeyword">endmodule</span>
|
| 1607 |
|
|
<a name="l01604"></a>01604
|
| 1608 |
|
|
<a name="l01605"></a>01605 <span class="keyword">/***********************************************************************************************************************</span>
|
| 1609 |
|
|
<a name="l01606"></a>01606 <span class="keyword"> Registers</span>
|
| 1610 |
|
|
<a name="l01607"></a>01607 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 1611 |
|
|
<a name="l01608"></a>01608
|
| 1612 |
|
|
<a name="l01609"></a>01609
|
| 1613 |
|
|
<a name="l01620"></a><a class="code" href="classregisters.html">01620</a> <span class="vhdlkeyword">module</span> <a class="code" href="classregisters.html">registers</a>(
|
| 1614 |
|
|
<a name="l01621"></a><a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">01621</a> <span class="vhdlkeyword">input</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a>,
|
| 1615 |
|
|
<a name="l01622"></a><a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">01622</a> <span class="vhdlkeyword">input</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>,
|
| 1616 |
|
|
<a name="l01623"></a>01623
|
| 1617 |
|
|
<a name="l01624"></a><a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">01624</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>,
|
| 1618 |
|
|
<a name="l01625"></a><a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">01625</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">79</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>,
|
| 1619 |
|
|
<a name="l01626"></a><a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">01626</a> <span class="vhdlkeyword">input</span> <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a>,
|
| 1620 |
|
|
<a name="l01627"></a><a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">01627</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>,
|
| 1621 |
|
|
<a name="l01628"></a><a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">01628</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>,
|
| 1622 |
|
|
<a name="l01629"></a><a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">01629</a> <span class="vhdlkeyword">input</span> <a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">rw_state</a>,
|
| 1623 |
|
|
<a name="l01630"></a><a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">01630</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">fc_state</a>,
|
| 1624 |
|
|
<a name="l01631"></a><a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">01631</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">fault_address_state</a>,
|
| 1625 |
|
|
<a name="l01632"></a><a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">01632</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">interrupt_trap</a>,
|
| 1626 |
|
|
<a name="l01633"></a><a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">01633</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">interrupt_mask</a>,
|
| 1627 |
|
|
<a name="l01634"></a><a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">01634</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a>,
|
| 1628 |
|
|
<a name="l01635"></a>01635
|
| 1629 |
|
|
<a name="l01636"></a><a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">01636</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">usp</a>,
|
| 1630 |
|
|
<a name="l01637"></a><a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">01637</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>,
|
| 1631 |
|
|
<a name="l01638"></a><a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">01638</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>,
|
| 1632 |
|
|
<a name="l01639"></a>01639
|
| 1633 |
|
|
<a name="l01640"></a><a class="code" href="classregisters.html#a73560eea6b21f10073a1131e3cffa801">01640</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a73560eea6b21f10073a1131e3cffa801">pc_change</a>,
|
| 1634 |
12 |
alfik |
<a name="l01641"></a>01641
|
| 1635 |
13 |
alfik |
<a name="l01642"></a><a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">01642</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a>,
|
| 1636 |
|
|
<a name="l01643"></a><a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">01643</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a>,
|
| 1637 |
12 |
alfik |
<a name="l01644"></a>01644
|
| 1638 |
13 |
alfik |
<a name="l01645"></a><a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">01645</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a>,
|
| 1639 |
|
|
<a name="l01646"></a><a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">01646</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a>,
|
| 1640 |
12 |
alfik |
<a name="l01647"></a>01647
|
| 1641 |
13 |
alfik |
<a name="l01648"></a><a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">01648</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a>,
|
| 1642 |
|
|
<a name="l01649"></a><a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">01649</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a>,
|
| 1643 |
|
|
<a name="l01650"></a>01650
|
| 1644 |
|
|
<a name="l01651"></a>01651 <span class="keyword">// for DIVU/DIVS simulation, register must be not zero</span>
|
| 1645 |
|
|
<a name="l01652"></a><a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">01652</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> = <span class="vhdllogic">32'hFFFFFFFF</span>,
|
| 1646 |
|
|
<a name="l01653"></a>01653 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] operand1_control,
|
| 1647 |
12 |
alfik |
<a name="l01654"></a>01654
|
| 1648 |
13 |
alfik |
<a name="l01655"></a>01655 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] operand2 = <span class="vhdllogic">32'hFFFFFFFF</span>,
|
| 1649 |
|
|
<a name="l01656"></a>01656 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] operand2_control,
|
| 1650 |
|
|
<a name="l01657"></a>01657
|
| 1651 |
|
|
<a name="l01658"></a>01658 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] address,
|
| 1652 |
|
|
<a name="l01659"></a>01659 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> address_type,
|
| 1653 |
|
|
<a name="l01660"></a>01660 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] address_control,
|
| 1654 |
12 |
alfik |
<a name="l01661"></a>01661
|
| 1655 |
13 |
alfik |
<a name="l01662"></a>01662 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] size,
|
| 1656 |
|
|
<a name="l01663"></a>01663 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] size_control,
|
| 1657 |
12 |
alfik |
<a name="l01664"></a>01664
|
| 1658 |
13 |
alfik |
<a name="l01665"></a>01665 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] movem_modreg,
|
| 1659 |
|
|
<a name="l01666"></a>01666 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] movem_modreg_control,
|
| 1660 |
12 |
alfik |
<a name="l01667"></a>01667
|
| 1661 |
13 |
alfik |
<a name="l01668"></a>01668 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] movem_loop,
|
| 1662 |
|
|
<a name="l01669"></a>01669 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] movem_loop_control,
|
| 1663 |
12 |
alfik |
<a name="l01670"></a>01670
|
| 1664 |
13 |
alfik |
<a name="l01671"></a>01671 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] movem_reg,
|
| 1665 |
|
|
<a name="l01672"></a>01672 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] movem_reg_control,
|
| 1666 |
12 |
alfik |
<a name="l01673"></a>01673
|
| 1667 |
13 |
alfik |
<a name="l01674"></a>01674 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] ir,
|
| 1668 |
|
|
<a name="l01675"></a>01675 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] ir_control,
|
| 1669 |
12 |
alfik |
<a name="l01676"></a>01676
|
| 1670 |
13 |
alfik |
<a name="l01677"></a>01677 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] pc,
|
| 1671 |
|
|
<a name="l01678"></a>01678 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] pc_control,
|
| 1672 |
12 |
alfik |
<a name="l01679"></a>01679
|
| 1673 |
13 |
alfik |
<a name="l01680"></a>01680 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] trap,
|
| 1674 |
|
|
<a name="l01681"></a>01681 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] trap_control,
|
| 1675 |
12 |
alfik |
<a name="l01682"></a>01682
|
| 1676 |
13 |
alfik |
<a name="l01683"></a>01683 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] offset,
|
| 1677 |
|
|
<a name="l01684"></a>01684 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] offset_control,
|
| 1678 |
12 |
alfik |
<a name="l01685"></a>01685
|
| 1679 |
13 |
alfik |
<a name="l01686"></a>01686 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] index,
|
| 1680 |
|
|
<a name="l01687"></a>01687 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] index_control,
|
| 1681 |
|
|
<a name="l01688"></a>01688
|
| 1682 |
12 |
alfik |
<a name="l01689"></a>01689
|
| 1683 |
13 |
alfik |
<a name="l01690"></a>01690 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> stop_flag,
|
| 1684 |
|
|
<a name="l01691"></a>01691 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] stop_flag_control,
|
| 1685 |
12 |
alfik |
<a name="l01692"></a>01692
|
| 1686 |
13 |
alfik |
<a name="l01693"></a>01693 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> trace_flag,
|
| 1687 |
|
|
<a name="l01694"></a>01694 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] trace_flag_control,
|
| 1688 |
12 |
alfik |
<a name="l01695"></a>01695
|
| 1689 |
13 |
alfik |
<a name="l01696"></a>01696 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> group_0_flag,
|
| 1690 |
|
|
<a name="l01697"></a>01697 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] group_0_flag_control,
|
| 1691 |
12 |
alfik |
<a name="l01698"></a>01698
|
| 1692 |
13 |
alfik |
<a name="l01699"></a>01699 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> instruction_flag,
|
| 1693 |
|
|
<a name="l01700"></a>01700 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] instruction_flag_control,
|
| 1694 |
12 |
alfik |
<a name="l01701"></a>01701
|
| 1695 |
13 |
alfik |
<a name="l01702"></a>01702 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> read_modify_write_flag,
|
| 1696 |
|
|
<a name="l01703"></a>01703 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] read_modify_write_flag_control,
|
| 1697 |
12 |
alfik |
<a name="l01704"></a>01704
|
| 1698 |
13 |
alfik |
<a name="l01705"></a>01705 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> do_reset_flag,
|
| 1699 |
|
|
<a name="l01706"></a>01706 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] do_reset_flag_control,
|
| 1700 |
12 |
alfik |
<a name="l01707"></a>01707
|
| 1701 |
13 |
alfik |
<a name="l01708"></a>01708 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> do_interrupt_flag,
|
| 1702 |
|
|
<a name="l01709"></a>01709 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] do_interrupt_flag_control,
|
| 1703 |
12 |
alfik |
<a name="l01710"></a>01710
|
| 1704 |
13 |
alfik |
<a name="l01711"></a>01711 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> do_read_flag,
|
| 1705 |
|
|
<a name="l01712"></a>01712 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] do_read_flag_control,
|
| 1706 |
12 |
alfik |
<a name="l01713"></a>01713
|
| 1707 |
13 |
alfik |
<a name="l01714"></a>01714 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> do_write_flag,
|
| 1708 |
|
|
<a name="l01715"></a>01715 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] do_write_flag_control,
|
| 1709 |
12 |
alfik |
<a name="l01716"></a>01716
|
| 1710 |
13 |
alfik |
<a name="l01717"></a>01717 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> do_blocked_flag,
|
| 1711 |
|
|
<a name="l01718"></a>01718 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] do_blocked_flag_control,
|
| 1712 |
12 |
alfik |
<a name="l01719"></a>01719
|
| 1713 |
13 |
alfik |
<a name="l01720"></a>01720 <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] data_write,
|
| 1714 |
|
|
<a name="l01721"></a>01721 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] data_write_control,
|
| 1715 |
|
|
<a name="l01722"></a>01722
|
| 1716 |
12 |
alfik |
<a name="l01723"></a>01723
|
| 1717 |
13 |
alfik |
<a name="l01724"></a>01724 <span class="vhdlkeyword">output</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] An_address,
|
| 1718 |
|
|
<a name="l01725"></a>01725 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] An_address_control,
|
| 1719 |
12 |
alfik |
<a name="l01726"></a>01726
|
| 1720 |
13 |
alfik |
<a name="l01727"></a>01727 <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] An_input,
|
| 1721 |
|
|
<a name="l01728"></a>01728 <span class="vhdlkeyword">input</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] An_input_control,
|
| 1722 |
|
|
<a name="l01729"></a>01729
|
| 1723 |
|
|
<a name="l01730"></a>01730 <span class="vhdlkeyword">output</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] Dn_address,
|
| 1724 |
|
|
<a name="l01731"></a>01731 <span class="vhdlkeyword">input</span> Dn_address_control
|
| 1725 |
|
|
<a name="l01732"></a>01732 );
|
| 1726 |
|
|
<a name="l01733"></a>01733
|
| 1727 |
|
|
<a name="l01734"></a><a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">01734</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a>;
|
| 1728 |
|
|
<a name="l01735"></a>01735
|
| 1729 |
|
|
<a name="l01736"></a>01736 <span class="keyword">// pc_change connected</span>
|
| 1730 |
|
|
<a name="l01737"></a><a class="code" href="classregisters.html#a1634ef9b02cbeb72da694a9145e2d276">01737</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1731 |
|
|
<a name="l01738"></a>01738 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 1732 |
|
|
<a name="l01739"></a>01739 <span class="vhdlchar">pc</span> <= <span class="vhdllogic">32'd0</span>;
|
| 1733 |
|
|
<a name="l01740"></a>01740 <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> <= <span class="vhdllogic">32'd0</span>;
|
| 1734 |
|
|
<a name="l01741"></a>01741 <span class="vhdlkeyword">end</span>
|
| 1735 |
|
|
<a name="l01742"></a>01742 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 1736 |
|
|
<a name="l01743"></a>01743 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a63d3becb9e2a770cfd9df4a70298c30a">`PC_FROM_RESULT</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
| 1737 |
|
|
<a name="l01744"></a>01744 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a023942fcdb1eb88002847e9730cf62c2">`PC_INCR_BY_2</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd2</span>;
|
| 1738 |
|
|
<a name="l01745"></a>01745 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6b8aff09ca5bd77e19e6d7a5076a58bd">`PC_INCR_BY_4</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd4</span>;
|
| 1739 |
|
|
<a name="l01746"></a>01746 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#aefc526541d0911ae626689caead407ab">`PC_INCR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = (<span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd4</span>;
|
| 1740 |
|
|
<a name="l01747"></a>01747 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a48c2827ab160beae0aab354b09b59e1a">`PC_FROM_PREFETCH_IR</a><span class="vhdlchar"></span>) <span class="vhdlchar">pc</span> = <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">47</span>:<span class="vhdllogic">16</span>];
|
| 1741 |
|
|
<a name="l01748"></a>01748 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6f1c276d75adca2b0290b7936476fde8">`PC_INCR_BY_2_IN_MAIN_LOOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
| 1742 |
|
|
<a name="l01749"></a>01749 <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32'd2</span>;
|
| 1743 |
|
|
<a name="l01750"></a>01750 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> <= <span class="vhdlchar">pc</span>;
|
| 1744 |
|
|
<a name="l01751"></a>01751 <span class="vhdlkeyword">end</span>
|
| 1745 |
|
|
<a name="l01752"></a>01752 <span class="vhdlkeyword">end</span>
|
| 1746 |
|
|
<a name="l01753"></a>01753
|
| 1747 |
|
|
<a name="l01754"></a>01754 <span class="vhdlkeyword">assign</span> <a class="code" href="classregisters.html#a73560eea6b21f10073a1131e3cffa801">pc_change</a> =
|
| 1748 |
|
|
<a name="l01755"></a>01755 ( <span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a63d3becb9e2a770cfd9df4a70298c30a">`PC_FROM_RESULT</a><span class="vhdlchar"></span> || <span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a48c2827ab160beae0aab354b09b59e1a">`PC_FROM_PREFETCH_IR</a><span class="vhdlchar"></span>
|
| 1749 |
|
|
<a name="l01756"></a>01756 ) ? <span class="vhdllogic">2'b11</span> :
|
| 1750 |
|
|
<a name="l01757"></a>01757 ( <span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6b8aff09ca5bd77e19e6d7a5076a58bd">`PC_INCR_BY_4</a><span class="vhdlchar"></span> || (<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#aefc526541d0911ae626689caead407ab">`PC_INCR_BY_SIZE</a><span class="vhdlchar"></span> && <span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>)
|
| 1751 |
|
|
<a name="l01758"></a>01758 ) ? <span class="vhdllogic">2'b10</span> :
|
| 1752 |
|
|
<a name="l01759"></a>01759 ( <span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a023942fcdb1eb88002847e9730cf62c2">`PC_INCR_BY_2</a><span class="vhdlchar"></span> || (<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#aefc526541d0911ae626689caead407ab">`PC_INCR_BY_SIZE</a><span class="vhdlchar"></span> && <span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b0</span>) ||
|
| 1753 |
|
|
<a name="l01760"></a>01760 (<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6f1c276d75adca2b0290b7936476fde8">`PC_INCR_BY_2_IN_MAIN_LOOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
| 1754 |
|
|
<a name="l01761"></a>01761 ) ? <span class="vhdllogic">2'b01</span> :
|
| 1755 |
|
|
<a name="l01762"></a>01762 <span class="vhdllogic">2'b00</span>;
|
| 1756 |
|
|
<a name="l01763"></a>01763
|
| 1757 |
|
|
<a name="l01764"></a><a class="code" href="classregisters.html#a160e4dadb225ac705317bf8de0c78277">01764</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1758 |
|
|
<a name="l01765"></a>01765 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 1759 |
|
|
<a name="l01766"></a>01766 <span class="vhdlchar">size</span> <= <span class="vhdllogic">2'b00</span>;
|
| 1760 |
|
|
<a name="l01767"></a>01767 <span class="vhdlkeyword">end</span>
|
| 1761 |
15 |
alfik |
<a name="l01768"></a>01768 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">size_control</span> != <a class="code" href="ao68000_8v.html#a85698146140d774ffe2b54e5be255726">`SIZE_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
| 1762 |
13 |
alfik |
<a name="l01769"></a>01769 <span class="keyword">// BYTE</span>
|
| 1763 |
|
|
<a name="l01770"></a>01770 <span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">`SIZE_BYTE</a><span class="vhdlchar"></span>)
|
| 1764 |
|
|
<a name="l01771"></a>01771 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span>))
|
| 1765 |
|
|
<a name="l01772"></a>01772 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b01</span>))
|
| 1766 |
|
|
<a name="l01773"></a>01773 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span>));
|
| 1767 |
|
|
<a name="l01774"></a>01774 <span class="keyword">// WORD</span>
|
| 1768 |
|
|
<a name="l01775"></a>01775 <span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a9da3fa515a6d6e5949573714c5682999">`SIZE_WORD</a><span class="vhdlchar"></span>)
|
| 1769 |
|
|
<a name="l01776"></a>01776 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">`SIZE_1</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span>))
|
| 1770 |
|
|
<a name="l01777"></a>01777 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">`SIZE_1_PLUS</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>))
|
| 1771 |
|
|
<a name="l01778"></a>01778 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">`SIZE_2</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b0</span>))
|
| 1772 |
|
|
<a name="l01779"></a>01779 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>))
|
| 1773 |
|
|
<a name="l01780"></a>01780 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b11</span>))
|
| 1774 |
|
|
<a name="l01781"></a>01781 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>));
|
| 1775 |
|
|
<a name="l01782"></a>01782 <span class="keyword">// LONG</span>
|
| 1776 |
|
|
<a name="l01783"></a>01783 <span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] <= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ae54bb350f5d3a019211af2a214f46273">`SIZE_LONG</a><span class="vhdlchar"></span>)
|
| 1777 |
|
|
<a name="l01784"></a>01784 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">`SIZE_1</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span>))
|
| 1778 |
|
|
<a name="l01785"></a>01785 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">`SIZE_1_PLUS</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b10</span>))
|
| 1779 |
|
|
<a name="l01786"></a>01786 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">`SIZE_2</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>))
|
| 1780 |
|
|
<a name="l01787"></a>01787 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>))
|
| 1781 |
|
|
<a name="l01788"></a>01788 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b0</span>))
|
| 1782 |
|
|
<a name="l01789"></a>01789 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>))
|
| 1783 |
|
|
<a name="l01790"></a>01790 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) && (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span>));
|
| 1784 |
|
|
<a name="l01791"></a>01791 <span class="vhdlkeyword">end</span>
|
| 1785 |
|
|
<a name="l01792"></a>01792 <span class="vhdlkeyword">end</span>
|
| 1786 |
14 |
alfik |
<a name="l01793"></a>01793
|
| 1787 |
|
|
<a name="l01794"></a><a class="code" href="classregisters.html#a098bb8c5f886c173a49d1e015dd37289">01794</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1788 |
|
|
<a name="l01795"></a>01795 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b000</span>;
|
| 1789 |
|
|
<a name="l01796"></a>01796 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab608c5385657295b902b8ffc21c43d03">`EA_REG_IR_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
| 1790 |
|
|
<a name="l01797"></a>01797 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#a56f29ecaaf69843219c88d8e0f252048">`EA_REG_IR_11_9</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>];
|
| 1791 |
|
|
<a name="l01798"></a>01798 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#af2b8ce7c793c79dee8394ad309a1ef71">`EA_REG_MOVEM_REG_2_0</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
| 1792 |
|
|
<a name="l01799"></a>01799 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#aa5ef414e1c0f769a38cdd8b3aeef5184">`EA_REG_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b111</span>;
|
| 1793 |
|
|
<a name="l01800"></a>01800 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a87fed6b8d7f55252c49ab2fc43d39d9a">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab4936576a8613273a6487d2b78812c55">`EA_REG_3b100</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> <= <span class="vhdllogic">3'b100</span>;
|
| 1794 |
|
|
<a name="l01801"></a>01801 <span class="vhdlkeyword">end</span>
|
| 1795 |
|
|
<a name="l01802"></a>01802
|
| 1796 |
|
|
<a name="l01803"></a><a class="code" href="classregisters.html#a6fc98500064486297076cc7c8e99e16f">01803</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1797 |
|
|
<a name="l01804"></a>01804 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
|
| 1798 |
|
|
<a name="l01805"></a>01805 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a0c094175d5b6718611708b08af5e6342">`EA_MOD_IR_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
|
| 1799 |
|
|
<a name="l01806"></a>01806 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a45b520ba3dd813510ddca0ebe0a652f4">`EA_MOD_MOVEM_MOD_5_3</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
|
| 1800 |
|
|
<a name="l01807"></a>01807 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a46d304e545e3f136f9bc7fe83ffe61df">`EA_MOD_IR_8_6</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>];
|
| 1801 |
|
|
<a name="l01808"></a>01808 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a2e15ad20aa0f28ef9042982260a21316">`EA_MOD_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b100</span>;
|
| 1802 |
|
|
<a name="l01809"></a>01809 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ae4ecbd320f11539d132c8e6aa3fdcb5c">`EA_MOD_3b111</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b111</span>;
|
| 1803 |
|
|
<a name="l01810"></a>01810 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#aee18d2c3a30bdec23a7de0889deb0d94">`EA_MOD_DN_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* -(An) **/</span> <span class="vhdllogic">3'b100</span>;
|
| 1804 |
|
|
<a name="l01811"></a>01811 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ac190b9646213ddb87ec06a5858d479b3">`EA_MOD_DN_AN_EXG</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b01000</span> || <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5'b10001</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3'b000</span> : <span class="keyword">/* An **/</span> <span class="vhdllogic">3'b001</span>;
|
| 1805 |
|
|
<a name="l01812"></a>01812 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a51a36024571aca1d7d7c7fa928956589">`EA_MOD_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b011</span>;
|
| 1806 |
|
|
<a name="l01813"></a>01813 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a7a6ccf87a21e66605e4672e95a6578e4">`EA_MOD_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b001</span>;
|
| 1807 |
|
|
<a name="l01814"></a>01814 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a8a000a242ea6cc51ac97ec35753faf7b">`EA_MOD_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b000</span>;
|
| 1808 |
|
|
<a name="l01815"></a>01815 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ab630b141208b16db686f800d53dc41eb">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a88ded717145b6f89a3cd3416577225f0">`EA_MOD_INDIRECTOFFSET</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#aafe87b4d917fd589612b82802a4c838b">ea_mod</a> <= <span class="vhdllogic">3'b101</span>;
|
| 1809 |
|
|
<a name="l01816"></a>01816 <span class="vhdlkeyword">end</span>
|
| 1810 |
|
|
<a name="l01817"></a>01817
|
| 1811 |
|
|
<a name="l01818"></a><a class="code" href="classregisters.html#aa536be1ed88148e7c828c0183e8a0757">01818</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1812 |
|
|
<a name="l01819"></a>01819 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a30b69aee8fb5af4ab38fc9f0d92a28d3">`EA_TYPE_IDLE</a><span class="vhdlchar"></span>;
|
| 1813 |
|
|
<a name="l01820"></a>01820 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>;
|
| 1814 |
|
|
<a name="l01821"></a>01821 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>;
|
| 1815 |
|
|
<a name="l01822"></a>01822 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>;
|
| 1816 |
|
|
<a name="l01823"></a>01823 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>;
|
| 1817 |
|
|
<a name="l01824"></a>01824 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>;
|
| 1818 |
|
|
<a name="l01825"></a>01825 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>;
|
| 1819 |
|
|
<a name="l01826"></a>01826 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>;
|
| 1820 |
|
|
<a name="l01827"></a>01827 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a6fe315cf4e9805733719db71cf630847">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a531a4ea89d5bde45780adeeda7d42bb4">ea_type</a> <= <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>;
|
| 1821 |
|
|
<a name="l01828"></a>01828 <span class="vhdlkeyword">end</span>
|
| 1822 |
|
|
<a name="l01829"></a>01829
|
| 1823 |
|
|
<a name="l01830"></a><a class="code" href="classregisters.html#a8fa9503b229756474eafc4b087aa6511">01830</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1824 |
|
|
<a name="l01831"></a>01831 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
| 1825 |
|
|
<a name="l01832"></a>01832 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a29e287eda5813f253f9f1cd527021533">`OP1_FROM_OP2</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">operand2</span>;
|
| 1826 |
|
|
<a name="l01833"></a>01833 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ab601cf0d52e5fe6ae155ab8084b236e1">`OP1_FROM_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdlchar">address</span>;
|
| 1827 |
|
|
<a name="l01834"></a>01834 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aec7f41507eab6c659f5d544c942b441e">`OP1_FROM_DATA</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
| 1828 |
|
|
<a name="l01835"></a>01835 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
|
| 1829 |
|
|
<a name="l01836"></a>01836 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
| 1830 |
|
|
<a name="l01837"></a>01837 <a class="code" href="classregisters.html#a015db9817045d85028931bbb036f7b59">data_read</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 1831 |
|
|
<a name="l01838"></a>01838 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#abc0874c9141535c9c6a071653810c8fc">`OP1_FROM_IMMEDIATE</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
| 1832 |
|
|
<a name="l01839"></a>01839 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] } :
|
| 1833 |
|
|
<a name="l01840"></a>01840 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] } :
|
| 1834 |
|
|
<a name="l01841"></a>01841 <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
|
| 1835 |
|
|
<a name="l01842"></a>01842 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a2adbf20e4776f4f5449563560fcfea3e">`OP1_FROM_RESULT</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
| 1836 |
|
|
<a name="l01843"></a>01843 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ac2bd7be96e464a7a06affeb71024f266">`OP1_MOVEQ</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 1837 |
|
|
<a name="l01844"></a>01844 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aade66d4090f1aea9ed568a4e17ff1eae">`OP1_FROM_PC</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a>;
|
| 1838 |
|
|
<a name="l01845"></a>01845 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4db6f8d952dd7d7cfffeb0de4ad4a08b">`OP1_LOAD_ZEROS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'b0</span>;
|
| 1839 |
|
|
<a name="l01846"></a>01846 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ae8489ec12e458975d614347191ba2004">`OP1_LOAD_ONES</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
| 1840 |
|
|
<a name="l01847"></a>01847 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a9e1d49d77f5b144fff6cc8c0c021e5d2">`OP1_FROM_SR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
| 1841 |
|
|
<a name="l01848"></a>01848 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a1a44c33265ec779ad10e437621cda43b">`OP1_FROM_USP</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#ae8312cd504b37ae6dc199537ddf93bcb">usp</a>;
|
| 1842 |
|
|
<a name="l01849"></a>01849 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4900ac90de9fd53eaeb1acddf51a9008">`OP1_FROM_AN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
| 1843 |
|
|
<a name="l01850"></a>01850 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
| 1844 |
|
|
<a name="l01851"></a>01851 <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 1845 |
|
|
<a name="l01852"></a>01852 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a3aa722db3503e9370be36b3d409f3e17">`OP1_FROM_DN</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <=
|
| 1846 |
|
|
<a name="l01853"></a>01853 (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
|
| 1847 |
|
|
<a name="l01854"></a>01854 (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
|
| 1848 |
|
|
<a name="l01855"></a>01855 <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 1849 |
|
|
<a name="l01856"></a>01856 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a083db35259f035ab10f606d2c7dd82c6">`OP1_FROM_IR</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 1850 |
|
|
<a name="l01857"></a>01857 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a707f0ca7fa1a08446ba113ede9d5d8a4">`OP1_FROM_FAULT_ADDRESS</a><span class="vhdlchar"></span>) <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a> <= <a class="code" href="classregisters.html#a2975efdebb48903a858f0558c58d31c2">fault_address_state</a>;
|
| 1851 |
|
|
<a name="l01858"></a>01858 <span class="vhdlkeyword">end</span>
|
| 1852 |
|
|
<a name="l01859"></a>01859
|
| 1853 |
|
|
<a name="l01860"></a><a class="code" href="classregisters.html#ae6143c84411ad159cbe1662f3909e726">01860</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1854 |
|
|
<a name="l01861"></a>01861 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'hFFFFFFFF</span>;
|
| 1855 |
|
|
<a name="l01862"></a>01862 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a092ca695ecfa2de9e4d4a27bbd89d40f">`OP2_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>;
|
| 1856 |
|
|
<a name="l01863"></a>01863 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a5c2c8ed577b6ab91a5ae3861643575e7">`OP2_LOAD_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdllogic">32'd1</span>;
|
| 1857 |
|
|
<a name="l01864"></a>01864 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a7c904b70c2347aaee330105f74a69fc1">`OP2_LOAD_COUNT</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <=
|
| 1858 |
|
|
<a name="l01865"></a>01865 (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>] == <span class="vhdllogic">1'b0</span>) ? ( (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] } ) :
|
| 1859 |
|
|
<a name="l01866"></a>01866 { <span class="vhdllogic">26'b0</span>, <span class="vhdlchar">operand2</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] };
|
| 1860 |
|
|
<a name="l01867"></a>01867 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#aacec01f4da467eb6785c611710c1219d">`OP2_ADDQ_SUBQ</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">32'b1000</span> : { <span class="vhdllogic">29'b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] };
|
| 1861 |
|
|
<a name="l01868"></a>01868 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#ad8cdca7f0cbac16e09b4e1a1e3ab4f11">`OP2_MOVE_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>) ? <span class="vhdlchar">operand2</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] : { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 1862 |
|
|
<a name="l01869"></a>01869 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a041be53a35bc1a415713d34c839c81c5">`OP2_MOVE_ADDRESS_BUS_INFO</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdllogic">11'b0</span>, <a class="code" href="classregisters.html#a881b6927205941e0691b73906a7cfdd9">rw_state</a>, <span class="vhdlchar">instruction_flag</span>, <a class="code" href="classregisters.html#af336bd0ea96aad806fdb36dcd673a9c2">fc_state</a>};
|
| 1863 |
|
|
<a name="l01870"></a>01870 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a81d303d3fcf43bd2ed3b99072571f816">`OP2_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">operand2</span> <= <span class="vhdlchar">operand2</span> - <span class="vhdllogic">32'b1</span>;
|
| 1864 |
13 |
alfik |
<a name="l01871"></a>01871 <span class="vhdlkeyword">end</span>
|
| 1865 |
|
|
<a name="l01872"></a>01872
|
| 1866 |
14 |
alfik |
<a name="l01873"></a><a class="code" href="classregisters.html#ae04888e60d745f9f64ca5c52d0969adb">01873</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1867 |
|
|
<a name="l01874"></a>01874 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address</span> <= <span class="vhdllogic">32'b0</span>;
|
| 1868 |
|
|
<a name="l01875"></a>01875 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a864e0b06304816dec2d4658503d97495">`ADDRESS_INCR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> + {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
|
| 1869 |
|
|
<a name="l01876"></a>01876 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa479827c57933eb9ff03788bbe9d6e3a">`ADDRESS_DECR_BY_SIZE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) && <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> == <span class="vhdllogic">3'b111</span>) ? <span class="vhdlchar">address</span> - <span class="vhdllogic">32'd2</span> : <span class="vhdlchar">address</span> - {<span class="vhdllogic">29'd0</span>,<span class="vhdlchar">size</span>};
|
| 1870 |
|
|
<a name="l01877"></a>01877 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac4044068e496c3393c6336b72873a958">`ADDRESS_INCR_BY_2</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdllogic">32'd2</span>;
|
| 1871 |
|
|
<a name="l01878"></a>01878 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#afc15ad5da6b4afd71eb879476c603fe3">`ADDRESS_FROM_AN_OUTPUT</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>;
|
| 1872 |
|
|
<a name="l01879"></a>01879 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac1143ff5a059fc5609c9419fcd402ae1">`ADDRESS_FROM_BASE_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <span class="vhdlchar">address</span> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
|
| 1873 |
|
|
<a name="l01880"></a>01880 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa6ba908e680fe87e46ac1cf014eed463">`ADDRESS_FROM_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
|
| 1874 |
|
|
<a name="l01881"></a>01881 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa688332c940cad3a10561a5c9f74698a">`ADDRESS_FROM_IMM_32</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
|
| 1875 |
|
|
<a name="l01882"></a>01882 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= <a class="code" href="classregisters.html#a87b4409ca50b4ccad122fad79a9d6665">pc_valid</a> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
|
| 1876 |
|
|
<a name="l01883"></a>01883 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a2a30a0ecfa48e96cc5be837e7db71cab">`ADDRESS_FROM_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> <= {<span class="vhdllogic">22'b0</span>, <span class="vhdlchar">trap</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">2'b0</span>};
|
| 1877 |
13 |
alfik |
<a name="l01884"></a>01884 <span class="vhdlkeyword">end</span>
|
| 1878 |
|
|
<a name="l01885"></a>01885
|
| 1879 |
14 |
alfik |
<a name="l01886"></a><a class="code" href="classregisters.html#a7943ebd2393533b177f2cc9471614403">01886</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1880 |
|
|
<a name="l01887"></a>01887 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1881 |
|
|
<a name="l01888"></a>01888 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1882 |
|
|
<a name="l01889"></a>01889 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> != <a class="code" href="ao68000_8v.html#a3f7506465d358bddd4692916e422237d">`ADDRESS_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlchar">address_type</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1883 |
|
|
<a name="l01890"></a>01890 <span class="vhdlkeyword">end</span>
|
| 1884 |
|
|
<a name="l01891"></a>01891
|
| 1885 |
|
|
<a name="l01892"></a><a class="code" href="classregisters.html#a57a4884a23011ba445e6a69044c0b0bc">01892</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1886 |
|
|
<a name="l01893"></a>01893 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
|
| 1887 |
|
|
<a name="l01894"></a>01894 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a59e6a074af6fbcf3490ecdb2d277e452">`MOVEM_MODREG_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b0</span>;
|
| 1888 |
|
|
<a name="l01895"></a>01895 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a96857bc6f8514765cf6add0567891646">`MOVEM_MODREG_LOAD_6b001111</a><span class="vhdlchar"></span>)<span class="vhdlchar">movem_modreg</span> <= <span class="vhdllogic">6'b001111</span>;
|
| 1889 |
|
|
<a name="l01896"></a>01896 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#ab865a06c214356bb8906149ad6beebf2">`MOVEM_MODREG_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> + <span class="vhdllogic">6'd1</span>;
|
| 1890 |
|
|
<a name="l01897"></a>01897 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#afc15f893a792d1af5e5c90f8ed788662">`MOVEM_MODREG_DECR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_modreg</span> <= <span class="vhdlchar">movem_modreg</span> - <span class="vhdllogic">6'd1</span>;
|
| 1891 |
|
|
<a name="l01898"></a>01898 <span class="vhdlkeyword">end</span>
|
| 1892 |
|
|
<a name="l01899"></a>01899
|
| 1893 |
|
|
<a name="l01900"></a><a class="code" href="classregisters.html#a84ce568fcbe169cc02a3dc5c5bdbced2">01900</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1894 |
|
|
<a name="l01901"></a>01901 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
|
| 1895 |
|
|
<a name="l01902"></a>01902 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#a8465e4a24e72c1cb6e12015c4ff806c5">`MOVEM_LOOP_LOAD_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdllogic">5'b0</span>;
|
| 1896 |
|
|
<a name="l01903"></a>01903 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#add999e8b65307d6d46547d776999f215">`MOVEM_LOOP_INCR_BY_1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_loop</span> <= <span class="vhdlchar">movem_loop</span> + <span class="vhdllogic">5'd1</span>;
|
| 1897 |
|
|
<a name="l01904"></a>01904 <span class="vhdlkeyword">end</span>
|
| 1898 |
|
|
<a name="l01905"></a>01905
|
| 1899 |
|
|
<a name="l01906"></a><a class="code" href="classregisters.html#a5ca9e5ee3853a6c58d80397ee08dcdfb">01906</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1900 |
|
|
<a name="l01907"></a>01907 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">movem_reg</span> <= <span class="vhdllogic">16'b0</span>;
|
| 1901 |
|
|
<a name="l01908"></a>01908 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#aa7d78c26e9e37f761c7a0b178fe13cf8">`MOVEM_REG_FROM_OP1</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= <a class="code" href="classregisters.html#a6d53621114d007f65c3159fd3cad4ea1">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 1902 |
|
|
<a name="l01909"></a>01909 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#ac34150d75e16d155befcfcb8a95e45a3">`MOVEM_REG_SHIFT_RIGHT</a><span class="vhdlchar"></span>) <span class="vhdlchar">movem_reg</span> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdlchar">movem_reg</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
| 1903 |
|
|
<a name="l01910"></a>01910 <span class="vhdlkeyword">end</span>
|
| 1904 |
|
|
<a name="l01911"></a>01911
|
| 1905 |
|
|
<a name="l01912"></a><a class="code" href="classregisters.html#a670e4db98926f8ddddaa84356173ff1a">01912</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1906 |
|
|
<a name="l01913"></a>01913 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">ir</span> <= <span class="vhdllogic">16'b0</span>;
|
| 1907 |
|
|
<a name="l01914"></a>01914 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">ir_control</span> == <a class="code" href="ao68000_8v.html#a987216cfc97019736d0251dcd5470e68">`IR_LOAD_WHEN_PREFETCH_VALID</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
| 1908 |
|
|
<a name="l01915"></a>01915 <span class="vhdlchar">ir</span> <= <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>];
|
| 1909 |
|
|
<a name="l01916"></a>01916 <span class="vhdlkeyword">end</span>
|
| 1910 |
|
|
<a name="l01917"></a>01917
|
| 1911 |
|
|
<a name="l01918"></a><a class="code" href="classregisters.html#a3a2e5a5ea0bbf7d06bee2afef1124393">01918</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1912 |
|
|
<a name="l01919"></a>01919 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd0</span>;
|
| 1913 |
|
|
<a name="l01920"></a>01920 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4267c71337dc6963db47aba754396f48">`TRAP_ILLEGAL_INSTR</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd4</span>;
|
| 1914 |
|
|
<a name="l01921"></a>01921 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a111476f2c18a4085c9a5cea3692dc990">`TRAP_DIV_BY_ZERO</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd5</span>;
|
| 1915 |
|
|
<a name="l01922"></a>01922 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a7d97a1e77166d92c1d69452c3e836682">`TRAP_CHK</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd6</span>;
|
| 1916 |
|
|
<a name="l01923"></a>01923 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a66a7d33a63851daa49e101494acd6118">`TRAP_TRAPV</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd7</span>;
|
| 1917 |
|
|
<a name="l01924"></a>01924 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a940b41a2a1e4c585e15f1c2bef5d5c6f">`TRAP_PRIVIL_VIOLAT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd8</span>;
|
| 1918 |
|
|
<a name="l01925"></a>01925 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a84705ced93a01047ec829b7ea942cee0">`TRAP_TRACE</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <span class="vhdllogic">8'd9</span>;
|
| 1919 |
|
|
<a name="l01926"></a>01926 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4d09227bd9de91efc1a40bf676e10c72">`TRAP_TRAP</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= { <span class="vhdllogic">4'b0010</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] };
|
| 1920 |
|
|
<a name="l01927"></a>01927 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a8d6c015903e3a60339a6e8cc196bb440">`TRAP_FROM_DECODER</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a>;
|
| 1921 |
|
|
<a name="l01928"></a>01928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a57812c3cf3905152a60361ae979a4c2d">`TRAP_FROM_INTERRUPT</a><span class="vhdlchar"></span>) <span class="vhdlchar">trap</span> <= <a class="code" href="classregisters.html#ad7009ed104b0324325f2ebe297edc9b4">interrupt_trap</a>;
|
| 1922 |
|
|
<a name="l01929"></a>01929 <span class="vhdlkeyword">end</span>
|
| 1923 |
|
|
<a name="l01930"></a>01930
|
| 1924 |
|
|
<a name="l01931"></a><a class="code" href="classregisters.html#a931eb6b9c3c3c002a0eea00a7f10e10f">01931</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1925 |
|
|
<a name="l01932"></a>01932 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">offset</span> <= <span class="vhdllogic">32'd0</span>;
|
| 1926 |
|
|
<a name="l01933"></a>01933 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#ad904ffb95a59f475e446877344adb415">`OFFSET_IMM_8</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] };
|
| 1927 |
|
|
<a name="l01934"></a>01934 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#a87c5da2d7633077683260709d88602e0">`OFFSET_IMM_16</a><span class="vhdlchar"></span>) <span class="vhdlchar">offset</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
|
| 1928 |
|
|
<a name="l01935"></a>01935 <span class="vhdlkeyword">end</span>
|
| 1929 |
|
|
<a name="l01936"></a>01936
|
| 1930 |
|
|
<a name="l01937"></a><a class="code" href="classregisters.html#a2a04a4a12e64f1ffb3ec95095716fee7">01937</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1931 |
|
|
<a name="l01938"></a>01938 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
|
| 1932 |
|
|
<a name="l01939"></a>01939 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#a1db54bd70d82cea2a77c6d5c823f04db">`INDEX_0</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <= <span class="vhdllogic">32'd0</span>;
|
| 1933 |
|
|
<a name="l01940"></a>01940 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#af05405b84ee28262882d3c7ac7a5a80c">`INDEX_LOAD_EXTENDED</a><span class="vhdlchar"></span>) <span class="vhdlchar">index</span> <=
|
| 1934 |
|
|
<a name="l01941"></a>01941 (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>] == <span class="vhdllogic">1'b0</span>) ?
|
| 1935 |
|
|
<a name="l01942"></a>01942 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
|
| 1936 |
|
|
<a name="l01943"></a>01943 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a0376be737f05fcad48a8057caa2f1fcf">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
|
| 1937 |
|
|
<a name="l01944"></a>01944 ) :
|
| 1938 |
|
|
<a name="l01945"></a>01945 ( (<a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1'b0</span>) ?
|
| 1939 |
|
|
<a name="l01946"></a>01946 { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a4076832588fccdd9d5d0cc1b4b8dd0b0">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
|
| 1940 |
|
|
<a name="l01947"></a>01947 );
|
| 1941 |
|
|
<a name="l01948"></a>01948 <span class="vhdlkeyword">end</span>
|
| 1942 |
|
|
<a name="l01949"></a>01949
|
| 1943 |
|
|
<a name="l01950"></a><a class="code" href="classregisters.html#af284685eb0240e8fc444c84618b1af67">01950</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1944 |
|
|
<a name="l01951"></a>01951 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1945 |
|
|
<a name="l01952"></a>01952 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a5131e7ee341cd6f2ea5350a89b19a488">`STOP_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1946 |
|
|
<a name="l01953"></a>01953 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a0e63684fc863d639423c2d9f0f8e6cd9">`STOP_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">stop_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1947 |
|
|
<a name="l01954"></a>01954 <span class="vhdlkeyword">end</span>
|
| 1948 |
|
|
<a name="l01955"></a>01955
|
| 1949 |
|
|
<a name="l01956"></a><a class="code" href="classregisters.html#a12d4c2e0121456bcb2b23e7444c1da06">01956</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1950 |
|
|
<a name="l01957"></a>01957 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">trace_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1951 |
|
|
<a name="l01958"></a>01958 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trace_flag_control</span> == <a class="code" href="ao68000_8v.html#a3cb5bcdd68537f527007213efe5c2d4f">`TRACE_FLAG_COPY_WHEN_NO_STOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
| 1952 |
|
|
<a name="l01959"></a>01959 <span class="vhdlchar">trace_flag</span> <= <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">15</span>];
|
| 1953 |
|
|
<a name="l01960"></a>01960 <span class="vhdlkeyword">end</span>
|
| 1954 |
|
|
<a name="l01961"></a>01961
|
| 1955 |
|
|
<a name="l01962"></a><a class="code" href="classregisters.html#acf180186b03cdc0ad93be0efb7fa2815">01962</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1956 |
|
|
<a name="l01963"></a>01963 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1957 |
|
|
<a name="l01964"></a>01964 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a5333b31d43f3c7de70d3cad313720ef4">`GROUP_0_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1958 |
|
|
<a name="l01965"></a>01965 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a28adb393ace594d548dfe7f070fd837b">`GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
| 1959 |
|
|
<a name="l01966"></a>01966 <span class="vhdlchar">group_0_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1960 |
|
|
<a name="l01967"></a>01967 <span class="vhdlkeyword">end</span>
|
| 1961 |
|
|
<a name="l01968"></a>01968
|
| 1962 |
|
|
<a name="l01969"></a><a class="code" href="classregisters.html#a328ee93f9ab0ed3ebab4dc5936a7c5a0">01969</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1963 |
|
|
<a name="l01970"></a>01970 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1964 |
|
|
<a name="l01971"></a>01971 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#a6882447365cc7940c16017ee13305875">`INSTRUCTION_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1965 |
|
|
<a name="l01972"></a>01972 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#adaf70d0e1aaa9fe89fc79971d67bc172">`INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP</a><span class="vhdlchar"></span> && <a class="code" href="classregisters.html#aabb30e872d04701c156a70c4e1e7a3ba">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classregisters.html#a1444e3b474fdf49e5ab8a0283060ceab">decoder_trap</a> == <span class="vhdllogic">8'd0</span> && <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1'b0</span>)
|
| 1966 |
|
|
<a name="l01973"></a>01973 <span class="vhdlchar">instruction_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1967 |
|
|
<a name="l01974"></a>01974 <span class="vhdlkeyword">end</span>
|
| 1968 |
|
|
<a name="l01975"></a>01975
|
| 1969 |
|
|
<a name="l01976"></a><a class="code" href="classregisters.html#ad172a9061d9bb3653a3996dc4a74e101">01976</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1970 |
|
|
<a name="l01977"></a>01977 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1971 |
|
|
<a name="l01978"></a>01978 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a2ba2dbb4697aa9a3559b775da0ade761">`READ_MODIFY_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1972 |
|
|
<a name="l01979"></a>01979 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ace5de6cd5ad33427e8efd5ec8191c297">`READ_MODIFY_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">read_modify_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1973 |
|
|
<a name="l01980"></a>01980 <span class="vhdlkeyword">end</span>
|
| 1974 |
|
|
<a name="l01981"></a>01981
|
| 1975 |
|
|
<a name="l01982"></a><a class="code" href="classregisters.html#a34326a20d0a44ce95c7da4da53005097">01982</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1976 |
|
|
<a name="l01983"></a>01983 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1977 |
|
|
<a name="l01984"></a>01984 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#a682472d63f131aa31c38abd6f2d577ab">`DO_RESET_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1978 |
|
|
<a name="l01985"></a>01985 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#afd7c962bcd95f3629d247e7790f9cf95">`DO_RESET_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_reset_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1979 |
|
|
<a name="l01986"></a>01986 <span class="vhdlkeyword">end</span>
|
| 1980 |
|
|
<a name="l01987"></a>01987
|
| 1981 |
|
|
<a name="l01988"></a><a class="code" href="classregisters.html#ad881b4aebf8b3df42129f9731b6f6098">01988</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1982 |
|
|
<a name="l01989"></a>01989 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1983 |
|
|
<a name="l01990"></a>01990 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#acc420165ae00aa63b4d40c220dc1ed79">`DO_INTERRUPT_FLAG_SET_IF_ACTIVE</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= (<a class="code" href="classregisters.html#aaa89ede670fdc60f2b18c637c50f0dff">interrupt_mask</a> != <span class="vhdllogic">3'b000</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 1984 |
|
|
<a name="l01991"></a>01991 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#abe668eeea71491f898b31b9c66a4db96">`DO_INTERRUPT_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_interrupt_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1985 |
|
|
<a name="l01992"></a>01992 <span class="vhdlkeyword">end</span>
|
| 1986 |
|
|
<a name="l01993"></a>01993
|
| 1987 |
|
|
<a name="l01994"></a><a class="code" href="classregisters.html#aa69b93f001339d4b8ae1295a5cb215ec">01994</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1988 |
|
|
<a name="l01995"></a>01995 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1989 |
|
|
<a name="l01996"></a>01996 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a210a4746c070617bd4272cf091ce4977">`DO_READ_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1990 |
|
|
<a name="l01997"></a>01997 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a3186ce27b4c9202d124c4bee6b07e2fd">`DO_READ_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_read_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1991 |
|
|
<a name="l01998"></a>01998 <span class="vhdlkeyword">end</span>
|
| 1992 |
|
|
<a name="l01999"></a>01999
|
| 1993 |
|
|
<a name="l02000"></a><a class="code" href="classregisters.html#a63d22bb9298a179653d09d6b21e6c68b">02000</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 1994 |
|
|
<a name="l02001"></a>02001 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1995 |
|
|
<a name="l02002"></a>02002 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a97fc325edc48a555daf24f1757c5e7bf">`DO_WRITE_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 1996 |
|
|
<a name="l02003"></a>02003 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ad6f9aea669c0c0233f4155f29afc4d1d">`DO_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_write_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 1997 |
|
|
<a name="l02004"></a>02004 <span class="vhdlkeyword">end</span>
|
| 1998 |
|
|
<a name="l02005"></a>02005
|
| 1999 |
|
|
<a name="l02006"></a><a class="code" href="classregisters.html#a66ffba6d56dd08fe7b968605c3b68465">02006</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 2000 |
|
|
<a name="l02007"></a>02007 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b0</span>;
|
| 2001 |
|
|
<a name="l02008"></a>02008 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_blocked_flag_control</span> == <a class="code" href="ao68000_8v.html#ac69029fe984c3090537ed247a8106344">`DO_BLOCKED_FLAG_SET</a><span class="vhdlchar"></span>) <span class="vhdlchar">do_blocked_flag</span> <= <span class="vhdllogic">1'b1</span>;
|
| 2002 |
|
|
<a name="l02009"></a>02009 <span class="vhdlkeyword">end</span>
|
| 2003 |
|
|
<a name="l02010"></a>02010
|
| 2004 |
|
|
<a name="l02011"></a><a class="code" href="classregisters.html#ab3c53c1dc1763e2d051eaa736e429d58">02011</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#addbaa332878673f1c1192d8c2c9cd83e">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 2005 |
|
|
<a name="l02012"></a>02012 <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a7e3a00b7da8ae2fbd8336c34673c64a8">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlchar">data_write</span> <= <span class="vhdllogic">32'd0</span>;
|
| 2006 |
|
|
<a name="l02013"></a>02013 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">data_write_control</span> == <a class="code" href="ao68000_8v.html#ab576808298f9e1938241b8843e55c54e">`DATA_WRITE_FROM_RESULT</a><span class="vhdlchar"></span>) <span class="vhdlchar">data_write</span> <= <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
| 2007 |
|
|
<a name="l02014"></a>02014 <span class="vhdlkeyword">end</span>
|
| 2008 |
|
|
<a name="l02015"></a>02015
|
| 2009 |
|
|
<a name="l02016"></a>02016 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">An_address</span> =
|
| 2010 |
|
|
<a name="l02017"></a>02017 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#a50986c5b3afb053fcb3841dce7a93115">`AN_ADDRESS_FROM_EXTENDED</a><span class="vhdlchar"></span>) ? { <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">78</span>:<span class="vhdllogic">76</span>] } :
|
| 2011 |
|
|
<a name="l02018"></a>02018 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#ad5d4b9f48266549b9e8e5ac0c3ad239a">`AN_ADDRESS_USP</a><span class="vhdlchar"></span>) ? <span class="vhdllogic">4'b0111</span> :
|
| 2012 |
|
|
<a name="l02019"></a>02019 (<span class="vhdlchar">An_address_control</span> == <a class="code" href="ao68000_8v.html#a0dff5098fabf2afeac419c2e3c69b452">`AN_ADDRESS_SSP</a><span class="vhdlchar"></span>) ? <span class="vhdllogic">4'b1111</span> :
|
| 2013 |
|
|
<a name="l02020"></a>02020 { <a class="code" href="classregisters.html#ad583f99f893a13448ecd261e637ad56b">sr</a>[<span class="vhdllogic">13</span>], <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a> };
|
| 2014 |
|
|
<a name="l02021"></a>02021
|
| 2015 |
|
|
<a name="l02022"></a>02022 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">An_input</span> =
|
| 2016 |
|
|
<a name="l02023"></a>02023 (<span class="vhdlchar">An_input_control</span> == <a class="code" href="ao68000_8v.html#a67d98f6de465730c1bc9792aab02784c">`AN_INPUT_FROM_ADDRESS</a><span class="vhdlchar"></span>) ? <span class="vhdlchar">address</span> :
|
| 2017 |
|
|
<a name="l02024"></a>02024 (<span class="vhdlchar">An_input_control</span> == <a class="code" href="ao68000_8v.html#a90bc8bad52abb88cc05948307f41ffcf">`AN_INPUT_FROM_PREFETCH_IR</a><span class="vhdlchar"></span>) ? <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>] :
|
| 2018 |
|
|
<a name="l02025"></a>02025 <a class="code" href="classregisters.html#a81ed0f1a7f814e74696bea4db63f1e31">result</a>;
|
| 2019 |
13 |
alfik |
<a name="l02026"></a>02026
|
| 2020 |
14 |
alfik |
<a name="l02027"></a>02027 <span class="vhdlkeyword">assign</span> <span class="vhdlchar">Dn_address</span> = (<span class="vhdlchar">Dn_address_control</span> == <a class="code" href="ao68000_8v.html#aad74420658cfe8412a03c3dd6654ceb1">`DN_ADDRESS_FROM_EXTENDED</a><span class="vhdlchar"></span>) ? <a class="code" href="classregisters.html#aa8289dc94534500e03ff980b25804982">prefetch_ir</a>[<span class="vhdllogic">78</span>:<span class="vhdllogic">76</span>] : <a class="code" href="classregisters.html#a69652ae311e16ddcb1bb0dbc90744156">ea_reg</a>;
|
| 2021 |
|
|
<a name="l02028"></a>02028
|
| 2022 |
|
|
<a name="l02029"></a>02029 <span class="vhdlkeyword">endmodule</span>
|
| 2023 |
|
|
<a name="l02030"></a>02030
|
| 2024 |
|
|
<a name="l02031"></a>02031 <span class="keyword">/***********************************************************************************************************************</span>
|
| 2025 |
|
|
<a name="l02032"></a>02032 <span class="keyword"> Memory registers</span>
|
| 2026 |
|
|
<a name="l02033"></a>02033 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 2027 |
|
|
<a name="l02034"></a>02034
|
| 2028 |
|
|
<a name="l02035"></a>02035
|
| 2029 |
|
|
<a name="l02044"></a><a class="code" href="classmemory__registers.html">02044</a> <span class="vhdlkeyword">module</span> <a class="code" href="classmemory__registers.html">memory_registers</a>(
|
| 2030 |
|
|
<a name="l02045"></a><a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">02045</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>,
|
| 2031 |
|
|
<a name="l02046"></a><a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">02046</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a>,
|
| 2032 |
|
|
<a name="l02047"></a>02047
|
| 2033 |
|
|
<a name="l02048"></a>02048 <span class="keyword">// 0000,0001,0010,0011,0100,0101,0110: A0-A6, 0111: USP, 1111: SSP</span>
|
| 2034 |
|
|
<a name="l02049"></a><a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">02049</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a>,
|
| 2035 |
|
|
<a name="l02050"></a><a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">02050</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>,
|
| 2036 |
|
|
<a name="l02051"></a><a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">02051</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>,
|
| 2037 |
|
|
<a name="l02052"></a><a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">02052</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a>,
|
| 2038 |
|
|
<a name="l02053"></a>02053
|
| 2039 |
|
|
<a name="l02054"></a><a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">02054</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a>,
|
| 2040 |
|
|
<a name="l02055"></a>02055
|
| 2041 |
|
|
<a name="l02056"></a><a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">02056</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a>,
|
| 2042 |
|
|
<a name="l02057"></a><a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">02057</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a>,
|
| 2043 |
|
|
<a name="l02058"></a><a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">02058</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a>,
|
| 2044 |
|
|
<a name="l02059"></a>02059 <span class="keyword">// 001: byte, 010: word, 100: long</span>
|
| 2045 |
|
|
<a name="l02060"></a><a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">02060</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>,
|
| 2046 |
|
|
<a name="l02061"></a><a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">02061</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a>,
|
| 2047 |
|
|
<a name="l02062"></a>02062
|
| 2048 |
|
|
<a name="l02063"></a><a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">02063</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a>,
|
| 2049 |
|
|
<a name="l02064"></a><a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">02064</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">87</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a>
|
| 2050 |
|
|
<a name="l02065"></a>02065 );
|
| 2051 |
|
|
<a name="l02066"></a>02066
|
| 2052 |
|
|
<a name="l02067"></a><a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">02067</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a> = (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span>) ? <span class="vhdllogic">1'b0</span> : <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>;
|
| 2053 |
13 |
alfik |
<a name="l02068"></a>02068
|
| 2054 |
14 |
alfik |
<a name="l02069"></a><a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">02069</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>;
|
| 2055 |
|
|
<a name="l02070"></a>02070 <span class="vhdlkeyword">assign</span> <a class="code" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a> = (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span>) ? <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> : <a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>;
|
| 2056 |
|
|
<a name="l02071"></a>02071
|
| 2057 |
|
|
<a name="l02072"></a><a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">02072</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a> = (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b0001</span> :
|
| 2058 |
|
|
<a name="l02073"></a>02073 (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b0011</span> :
|
| 2059 |
|
|
<a name="l02074"></a>02074 (<a class="code" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">4'b1111</span> :
|
| 2060 |
|
|
<a name="l02075"></a>02075 <span class="vhdllogic">4'b0000</span>;
|
| 2061 |
|
|
<a name="l02076"></a>02076
|
| 2062 |
|
|
<a name="l02077"></a><a class="code" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">02077</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 2063 |
|
|
<a name="l02078"></a>02078 <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> <= <span class="vhdllogic">32'd0</span>;
|
| 2064 |
|
|
<a name="l02079"></a>02079 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4'b0111</span> && <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>) <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> <= <a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>;
|
| 2065 |
|
|
<a name="l02080"></a>02080 <span class="vhdlkeyword">end</span>
|
| 2066 |
|
|
<a name="l02081"></a>02081
|
| 2067 |
|
|
<a name="l02082"></a>02082 <span class="keyword">// Register set An implemented as RAM.</span>
|
| 2068 |
|
|
<a name="l02083"></a><a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">02083</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">an_ram_inst</span>(
|
| 2069 |
|
|
<a name="l02084"></a>02084 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
| 2070 |
|
|
<a name="l02085"></a>02085
|
| 2071 |
|
|
<a name="l02086"></a>02086 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>]),
|
| 2072 |
|
|
<a name="l02087"></a>02087 .<span class="vhdlchar">byteena_a</span> (<span class="vhdllogic">4'b1111</span>),
|
| 2073 |
|
|
<a name="l02088"></a>02088 .<span class="vhdlchar">wren_a</span> (<a class="code" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a>),
|
| 2074 |
|
|
<a name="l02089"></a>02089 .<span class="vhdlchar">data_a</span> (<a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>),
|
| 2075 |
|
|
<a name="l02090"></a>02090 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a>)
|
| 2076 |
|
|
<a name="l02091"></a>02091 );
|
| 2077 |
|
|
<a name="l02092"></a>02092 <span class="vhdlkeyword">defparam</span>
|
| 2078 |
|
|
<a name="l02093"></a>02093 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"SINGLE_PORT"</span>,
|
| 2079 |
|
|
<a name="l02094"></a>02094 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">32</span>,
|
| 2080 |
|
|
<a name="l02095"></a>02095 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">3</span>,
|
| 2081 |
|
|
<a name="l02096"></a>02096 <span class="vhdlchar">an_ram_inst</span>.<span class="vhdlchar">width_byteena_a</span> = <span class="vhdllogic">4</span>;
|
| 2082 |
|
|
<a name="l02097"></a>02097
|
| 2083 |
|
|
<a name="l02098"></a>02098 <span class="keyword">// Register set Dn implemented as RAM.</span>
|
| 2084 |
|
|
<a name="l02099"></a><a class="code" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">02099</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">dn_ram_inst</span>(
|
| 2085 |
|
|
<a name="l02100"></a>02100 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
| 2086 |
13 |
alfik |
<a name="l02101"></a>02101
|
| 2087 |
14 |
alfik |
<a name="l02102"></a>02102 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a>),
|
| 2088 |
|
|
<a name="l02103"></a>02103 .<span class="vhdlchar">byteena_a</span> (<a class="code" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a>),
|
| 2089 |
|
|
<a name="l02104"></a>02104 .<span class="vhdlchar">wren_a</span> (<a class="code" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a>),
|
| 2090 |
|
|
<a name="l02105"></a>02105 .<span class="vhdlchar">data_a</span> (<a class="code" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a>),
|
| 2091 |
|
|
<a name="l02106"></a>02106 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a>)
|
| 2092 |
|
|
<a name="l02107"></a>02107 );
|
| 2093 |
|
|
<a name="l02108"></a>02108 <span class="vhdlkeyword">defparam</span>
|
| 2094 |
|
|
<a name="l02109"></a>02109 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"SINGLE_PORT"</span>,
|
| 2095 |
|
|
<a name="l02110"></a>02110 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">32</span>,
|
| 2096 |
|
|
<a name="l02111"></a>02111 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">3</span>,
|
| 2097 |
|
|
<a name="l02112"></a>02112 <span class="vhdlchar">dn_ram_inst</span>.<span class="vhdlchar">width_byteena_a</span> = <span class="vhdllogic">4</span>;
|
| 2098 |
|
|
<a name="l02113"></a>02113
|
| 2099 |
|
|
<a name="l02114"></a>02114 <span class="keyword">// Microcode ROM</span>
|
| 2100 |
|
|
<a name="l02115"></a><a class="code" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">02115</a> <a class="code" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a> <span class="vhdlchar">micro_rom_inst</span>(
|
| 2101 |
|
|
<a name="l02116"></a>02116 .<span class="vhdlchar">clock0</span> (<a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a>),
|
| 2102 |
|
|
<a name="l02117"></a>02117
|
| 2103 |
|
|
<a name="l02118"></a>02118 .<span class="vhdlchar">address_a</span> (<a class="code" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a>),
|
| 2104 |
|
|
<a name="l02119"></a>02119 .<span class="vhdlchar">q_a</span> (<a class="code" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a>)
|
| 2105 |
|
|
<a name="l02120"></a>02120 );
|
| 2106 |
|
|
<a name="l02121"></a>02121 <span class="vhdlkeyword">defparam</span>
|
| 2107 |
|
|
<a name="l02122"></a>02122 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">"ROM"</span>,
|
| 2108 |
|
|
<a name="l02123"></a>02123 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">88</span>,
|
| 2109 |
|
|
<a name="l02124"></a>02124 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">9</span>,
|
| 2110 |
|
|
<a name="l02125"></a>02125 <span class="vhdlchar">micro_rom_inst</span>.<span class="vhdlchar">init_file</span> = <span class="keyword">"ao68000_microcode.mif"</span>;
|
| 2111 |
|
|
<a name="l02126"></a>02126
|
| 2112 |
|
|
<a name="l02127"></a>02127 <span class="vhdlkeyword">endmodule</span>
|
| 2113 |
|
|
<a name="l02128"></a>02128
|
| 2114 |
|
|
<a name="l02129"></a>02129 <span class="keyword">/***********************************************************************************************************************</span>
|
| 2115 |
|
|
<a name="l02130"></a>02130 <span class="keyword"> Instruction decoder</span>
|
| 2116 |
|
|
<a name="l02131"></a>02131 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 2117 |
|
|
<a name="l02132"></a>02132
|
| 2118 |
|
|
<a name="l02133"></a>02133
|
| 2119 |
|
|
<a name="l02143"></a><a class="code" href="classdecoder.html">02143</a> <span class="vhdlkeyword">module</span> <a class="code" href="classdecoder.html">decoder</a>(
|
| 2120 |
|
|
<a name="l02144"></a><a class="code" href="classdecoder.html#a07ea698e43905b149515da25bf07d981">02144</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#a07ea698e43905b149515da25bf07d981">clock</a>,
|
| 2121 |
|
|
<a name="l02145"></a><a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">02145</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">reset_n</a>,
|
| 2122 |
13 |
alfik |
<a name="l02146"></a>02146
|
| 2123 |
14 |
alfik |
<a name="l02147"></a><a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">02147</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">supervisor</a>,
|
| 2124 |
|
|
<a name="l02148"></a><a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">02148</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>,
|
| 2125 |
|
|
<a name="l02149"></a>02149
|
| 2126 |
|
|
<a name="l02150"></a>02150 <span class="keyword">// zero: no trap</span>
|
| 2127 |
|
|
<a name="l02151"></a><a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">02151</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">decoder_trap</a>,
|
| 2128 |
|
|
<a name="l02152"></a><a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">02152</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">decoder_micropc</a>,
|
| 2129 |
|
|
<a name="l02153"></a>02153
|
| 2130 |
|
|
<a name="l02154"></a><a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">02154</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">save_ea</a>,
|
| 2131 |
|
|
<a name="l02155"></a><a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">02155</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">perform_ea_write</a>,
|
| 2132 |
|
|
<a name="l02156"></a><a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">02156</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">perform_ea_read</a>,
|
| 2133 |
|
|
<a name="l02157"></a><a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">02157</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">load_ea</a>,
|
| 2134 |
|
|
<a name="l02158"></a>02158
|
| 2135 |
|
|
<a name="l02159"></a><a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">02159</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a>,
|
| 2136 |
|
|
<a name="l02160"></a><a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">02160</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a>,
|
| 2137 |
|
|
<a name="l02161"></a><a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">02161</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a>
|
| 2138 |
|
|
<a name="l02162"></a>02162 );
|
| 2139 |
|
|
<a name="l02163"></a>02163
|
| 2140 |
|
|
<a name="l02164"></a><a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">02164</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>]
|
| 2141 |
|
|
<a name="l02165"></a>02165 <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a> = <span class="vhdllogic">8'd0</span>,
|
| 2142 |
|
|
<a name="l02166"></a>02166 <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd4</span>,
|
| 2143 |
|
|
<a name="l02167"></a>02167 <a class="code" href="classdecoder.html#a6313ac7ffe9e5484093212a53689d4f0">PRIVILEGE_VIOLATION_TRAP</a> = <span class="vhdllogic">8'd8</span>,
|
| 2144 |
|
|
<a name="l02168"></a>02168 <a class="code" href="classdecoder.html#a40d58c5cecf313424f9df4928b33d9f4">ILLEGAL_1010_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd10</span>,
|
| 2145 |
|
|
<a name="l02169"></a>02169 <a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">ILLEGAL_1111_INSTRUCTION_TRAP</a> = <span class="vhdllogic">8'd11</span>;
|
| 2146 |
|
|
<a name="l02170"></a>02170
|
| 2147 |
|
|
<a name="l02171"></a><a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">02171</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>]
|
| 2148 |
|
|
<a name="l02172"></a>02172 <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> = <span class="vhdllogic">9'd0</span>;
|
| 2149 |
|
|
<a name="l02173"></a>02173
|
| 2150 |
|
|
<a name="l02174"></a>02174 <span class="vhdlkeyword">assign</span> { <a class="code" href="classdecoder.html#a3d51c77a26f72054bae55e07c4a7f50e">decoder_trap</a>, <a class="code" href="classdecoder.html#a17efa6a9faa1bd8ea90966c7127c4aad">decoder_micropc</a> } =
|
| 2151 |
|
|
<a name="l02175"></a>02175 (<a class="code" href="classdecoder.html#abe8ffab56eaa2b729b293fab145b88da">reset_n</a> == <span class="vhdllogic">1'b0</span>) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
| 2152 |
|
|
<a name="l02176"></a>02176
|
| 2153 |
|
|
<a name="l02177"></a>02177 <span class="keyword">// Privilege violation and illegal instruction</span>
|
| 2154 |
|
|
<a name="l02178"></a>02178
|
| 2155 |
|
|
<a name="l02179"></a>02179 <span class="keyword">// ANDI to SR,EORI to SR,ORI to SR,RESET,STOP,RTE,MOVE TO SR,MOVE USP TO USP,MOVE USP TO An privileged instructions</span>
|
| 2156 |
|
|
<a name="l02180"></a>02180 ( ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_0010_01_111_100</span> ||
|
| 2157 |
|
|
<a name="l02181"></a>02181 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_1010_01_111_100</span> ||
|
| 2158 |
|
|
<a name="l02182"></a>02182 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_0000_01_111_100</span> ||
|
| 2159 |
|
|
<a name="l02183"></a>02183 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0000</span> ||
|
| 2160 |
|
|
<a name="l02184"></a>02184 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ||
|
| 2161 |
|
|
<a name="l02185"></a>02185 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> ||
|
| 2162 |
|
|
<a name="l02186"></a>02186 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0110_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">6'b111_111</span>) ||
|
| 2163 |
|
|
<a name="l02187"></a>02187 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_0</span> ||
|
| 2164 |
|
|
<a name="l02188"></a>02188 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_1</span> ) && <a class="code" href="classdecoder.html#ab1195d70746a685dab833ac1e4943013">supervisor</a> == <span class="vhdllogic">1'b0</span> ) ? { <a class="code" href="classdecoder.html#a6313ac7ffe9e5484093212a53689d4f0">PRIVILEGE_VIOLATION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
| 2165 |
|
|
<a name="l02189"></a>02189 <span class="keyword">// ILLEGAL, illegal instruction</span>
|
| 2166 |
|
|
<a name="l02190"></a>02190 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1010_11_111100</span> ) ? { <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
| 2167 |
|
|
<a name="l02191"></a>02191 <span class="keyword">// 1010 illegal instruction</span>
|
| 2168 |
|
|
<a name="l02192"></a>02192 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1010</span> ) ? { <a class="code" href="classdecoder.html#a40d58c5cecf313424f9df4928b33d9f4">ILLEGAL_1010_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
| 2169 |
|
|
<a name="l02193"></a>02193 <span class="keyword">// 1111 illegal instruction</span>
|
| 2170 |
|
|
<a name="l02194"></a>02194 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1111</span> ) ? { <a class="code" href="classdecoder.html#a269c8223e03f340fbe89513326d22891">ILLEGAL_1111_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> } :
|
| 2171 |
|
|
<a name="l02195"></a>02195
|
| 2172 |
|
|
<a name="l02196"></a>02196 <span class="keyword">// instruction decoding</span>
|
| 2173 |
|
|
<a name="l02197"></a>02197
|
| 2174 |
|
|
<a name="l02198"></a>02198 <span class="keyword">// ANDI,EORI,ORI,ADDI,SUBI</span>
|
| 2175 |
|
|
<a name="l02199"></a>02199 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] != <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> &&
|
| 2176 |
|
|
<a name="l02200"></a>02200 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2177 |
|
|
<a name="l02201"></a>02201 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)) &&
|
| 2178 |
|
|
<a name="l02202"></a>02202 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_000_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_000_0_01_111100</span> &&
|
| 2179 |
|
|
<a name="l02203"></a>02203 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_001_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_001_0_01_111100</span> &&
|
| 2180 |
|
|
<a name="l02204"></a>02204 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_101_0_00_111100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">16'b0000_101_0_01_111100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a1508cd79053f2766a7bd8b7932ffdf0c">`MICROPC_ANDI_EORI_ORI_ADDI_SUBI</a><span class="vhdlchar"></span> } :
|
| 2181 |
|
|
<a name="l02205"></a>02205 <span class="keyword">// ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR</span>
|
| 2182 |
|
|
<a name="l02206"></a>02206 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_01_111100</span> ||
|
| 2183 |
|
|
<a name="l02207"></a>02207 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_01_111100</span> ||
|
| 2184 |
|
|
<a name="l02208"></a>02208 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_00_111100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_01_111100</span> ) ?
|
| 2185 |
|
|
<a name="l02209"></a>02209 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af7581a9c9f99af85388e542ad881d71f">`MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR</a><span class="vhdlchar"></span> } :
|
| 2186 |
|
|
<a name="l02210"></a>02210 <span class="keyword">// BTST register</span>
|
| 2187 |
|
|
<a name="l02211"></a>02211 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2188 |
|
|
<a name="l02212"></a>02212 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2189 |
|
|
<a name="l02213"></a>02213 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2190 |
|
|
<a name="l02214"></a>02214 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa2684e7883f516fe90229d1a02585c7c">`MICROPC_BTST_register</a><span class="vhdlchar"></span> } :
|
| 2191 |
|
|
<a name="l02215"></a>02215 <span class="keyword">// MOVEP memory to register</span>
|
| 2192 |
|
|
<a name="l02216"></a>02216 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> && ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> ) ) ?
|
| 2193 |
|
|
<a name="l02217"></a>02217 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a6827fab6e4b333e82a1de52cf6020b7a">`MICROPC_MOVEP_memory_to_register</a><span class="vhdlchar"></span> } :
|
| 2194 |
|
|
<a name="l02218"></a>02218 <span class="keyword">// MOVEP register to memory</span>
|
| 2195 |
|
|
<a name="l02219"></a>02219 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> && ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> ) ) ?
|
| 2196 |
|
|
<a name="l02220"></a>02220 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2516dd6bb3a4f804a752557b483e077b">`MICROPC_MOVEP_register_to_memory</a><span class="vhdlchar"></span> } :
|
| 2197 |
|
|
<a name="l02221"></a>02221 <span class="keyword">// BCHG,BCLR,BSET register</span>
|
| 2198 |
|
|
<a name="l02222"></a>02222 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b100</span> &&
|
| 2199 |
|
|
<a name="l02223"></a>02223 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2200 |
|
|
<a name="l02224"></a>02224 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5aff7e16fcd8e2f83c6a684fb62506b3">`MICROPC_BCHG_BCLR_BSET_register</a><span class="vhdlchar"></span> } :
|
| 2201 |
|
|
<a name="l02225"></a>02225 <span class="keyword">// BTST immediate</span>
|
| 2202 |
|
|
<a name="l02226"></a>02226 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2203 |
|
|
<a name="l02227"></a>02227 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2204 |
|
|
<a name="l02228"></a>02228 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
| 2205 |
|
|
<a name="l02229"></a>02229 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5ec24a82d3f383ac90da0ad8cc7bb0e3">`MICROPC_BTST_immediate</a><span class="vhdlchar"></span> } :
|
| 2206 |
|
|
<a name="l02230"></a>02230 <span class="keyword">// BCHG,BCLR,BSET immediate</span>
|
| 2207 |
|
|
<a name="l02231"></a>02231 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2208 |
|
|
<a name="l02232"></a>02232 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2209 |
|
|
<a name="l02233"></a>02233 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a89a5e8fafa2da702e7c00cb6fe7c2066">`MICROPC_BCHG_BCLR_BSET_immediate</a><span class="vhdlchar"></span> } :
|
| 2210 |
|
|
<a name="l02234"></a>02234 <span class="keyword">// CMPI</span>
|
| 2211 |
|
|
<a name="l02235"></a>02235 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2212 |
|
|
<a name="l02236"></a>02236 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2213 |
|
|
<a name="l02237"></a>02237 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5027ce5e621b327a8116e4ca0af34e90">`MICROPC_CMPI</a><span class="vhdlchar"></span> } :
|
| 2214 |
|
|
<a name="l02238"></a>02238 <span class="keyword">// MOVE</span>
|
| 2215 |
|
|
<a name="l02239"></a>02239 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">14</span>] == <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2216 |
|
|
<a name="l02240"></a>02240 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b000_111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b001_111</span>)) &&
|
| 2217 |
|
|
<a name="l02241"></a>02241 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] != <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
|
| 2218 |
|
|
<a name="l02242"></a>02242 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2219 |
|
|
<a name="l02243"></a>02243 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2220 |
|
|
<a name="l02244"></a>02244 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#afadd69027964ef6d7c9f923ed2714bbe">`MICROPC_MOVE</a><span class="vhdlchar"></span> } :
|
| 2221 |
|
|
<a name="l02245"></a>02245 <span class="keyword">// MOVEA</span>
|
| 2222 |
|
|
<a name="l02246"></a>02246 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">14</span>] == <span class="vhdllogic">2'b00</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b11</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2'b10</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> &&
|
| 2223 |
|
|
<a name="l02247"></a>02247 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2224 |
|
|
<a name="l02248"></a>02248 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2225 |
|
|
<a name="l02249"></a>02249 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a38b3d0769f31c2931ccc92e00af94884">`MICROPC_MOVEA</a><span class="vhdlchar"></span> } :
|
| 2226 |
|
|
<a name="l02250"></a>02250 <span class="keyword">// NEGX,CLR,NEG,NOT,NBCD</span>
|
| 2227 |
|
|
<a name="l02251"></a>02251 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>) &&
|
| 2228 |
|
|
<a name="l02252"></a>02252 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) ||
|
| 2229 |
|
|
<a name="l02253"></a>02253 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span>) ||
|
| 2230 |
|
|
<a name="l02254"></a>02254 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span>)
|
| 2231 |
|
|
<a name="l02255"></a>02255 )
|
| 2232 |
|
|
<a name="l02256"></a>02256 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a6f040be4f69b57ba9603d5eae6085425">`MICROPC_NEGX_CLR_NEG_NOT_NBCD</a><span class="vhdlchar"></span> } :
|
| 2233 |
|
|
<a name="l02257"></a>02257 <span class="keyword">// MOVE FROM SR</span>
|
| 2234 |
|
|
<a name="l02258"></a>02258 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0000_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)
|
| 2235 |
|
|
<a name="l02259"></a>02259 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a9527c313aa58c219b35f23dcfcd52a3a">`MICROPC_MOVE_FROM_SR</a><span class="vhdlchar"></span> } :
|
| 2236 |
|
|
<a name="l02260"></a>02260 <span class="keyword">// CHK</span>
|
| 2237 |
|
|
<a name="l02261"></a>02261 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2238 |
|
|
<a name="l02262"></a>02262 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2239 |
|
|
<a name="l02263"></a>02263 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2240 |
|
|
<a name="l02264"></a>02264 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a09d3064b3da754163f244a861ce4c758">`MICROPC_CHK</a><span class="vhdlchar"></span> } :
|
| 2241 |
|
|
<a name="l02265"></a>02265 <span class="keyword">// LEA</span>
|
| 2242 |
|
|
<a name="l02266"></a>02266 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2243 |
|
|
<a name="l02267"></a>02267 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2244 |
|
|
<a name="l02268"></a>02268 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
| 2245 |
|
|
<a name="l02269"></a>02269 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aced982dae609932df5af323a07349a2b">`MICROPC_LEA</a><span class="vhdlchar"></span> } :
|
| 2246 |
|
|
<a name="l02270"></a>02270 <span class="keyword">// MOVE TO CCR, MOVE TO SR</span>
|
| 2247 |
|
|
<a name="l02271"></a>02271 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0100_11</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_0110_11</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2248 |
|
|
<a name="l02272"></a>02272 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2249 |
|
|
<a name="l02273"></a>02273 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2250 |
|
|
<a name="l02274"></a>02274 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a258ae200cc2cbeccddff03ba18b66a27">`MICROPC_MOVE_TO_CCR_MOVE_TO_SR</a><span class="vhdlchar"></span> } :
|
| 2251 |
|
|
<a name="l02275"></a>02275 <span class="keyword">// SWAP,EXT</span>
|
| 2252 |
|
|
<a name="l02276"></a>02276 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0100</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">9'b1000_01_000</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span>) ) ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a65ca31e571d56e8b7e92ecadd58c94e1">`MICROPC_SWAP_EXT</a><span class="vhdlchar"></span> } :
|
| 2253 |
|
|
<a name="l02277"></a>02277 <span class="keyword">// PEA</span>
|
| 2254 |
|
|
<a name="l02278"></a>02278 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1000_01</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2255 |
|
|
<a name="l02279"></a>02279 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2256 |
|
|
<a name="l02280"></a>02280 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
| 2257 |
|
|
<a name="l02281"></a>02281 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2ce22f23bd95ba0ee7690a059448a357">`MICROPC_PEA</a><span class="vhdlchar"></span> } :
|
| 2258 |
|
|
<a name="l02282"></a>02282 <span class="keyword">// MOVEM register to memory, predecrement</span>
|
| 2259 |
|
|
<a name="l02283"></a>02283 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1000_1</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#affd3d4c8fd7cf2cbd78ecd99397f768b">`MICROPC_MOVEM_register_to_memory_predecrement</a><span class="vhdlchar"></span> } :
|
| 2260 |
|
|
<a name="l02284"></a>02284 <span class="keyword">// MOVEM register to memory, control</span>
|
| 2261 |
|
|
<a name="l02285"></a>02285 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1000_1</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2262 |
|
|
<a name="l02286"></a>02286 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>)
|
| 2263 |
|
|
<a name="l02287"></a>02287 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a775df2459596100b0e801ad20c24322b">`MICROPC_MOVEM_register_to_memory_control</a><span class="vhdlchar"></span> } :
|
| 2264 |
|
|
<a name="l02288"></a>02288 <span class="keyword">// TST</span>
|
| 2265 |
|
|
<a name="l02289"></a>02289 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_1010</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2266 |
|
|
<a name="l02290"></a>02290 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2267 |
|
|
<a name="l02291"></a>02291 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a0c416458c758702471d503b0dbeab5d8">`MICROPC_TST</a><span class="vhdlchar"></span> } :
|
| 2268 |
|
|
<a name="l02292"></a>02292 <span class="keyword">// TAS</span>
|
| 2269 |
|
|
<a name="l02293"></a>02293 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1010_11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2270 |
|
|
<a name="l02294"></a>02294 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2271 |
|
|
<a name="l02295"></a>02295 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a9d9308b3732ecf15f57a22600ac300b8">`MICROPC_TAS</a><span class="vhdlchar"></span> } :
|
| 2272 |
|
|
<a name="l02296"></a>02296 <span class="keyword">// MOVEM memory to register</span>
|
| 2273 |
|
|
<a name="l02297"></a>02297 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">9'b0100_1100_1</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2274 |
|
|
<a name="l02298"></a>02298 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2275 |
|
|
<a name="l02299"></a>02299 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
| 2276 |
|
|
<a name="l02300"></a>02300 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ac2e6ac139e91da76695b3f953c994a0d">`MICROPC_MOVEM_memory_to_register</a><span class="vhdlchar"></span> } :
|
| 2277 |
|
|
<a name="l02301"></a>02301 <span class="keyword">// TRAP</span>
|
| 2278 |
|
|
<a name="l02302"></a>02302 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">12'b0100_1110_0100</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa106c5a18e8252dc2ced5ec2f77650d9">`MICROPC_TRAP</a><span class="vhdlchar"></span> } :
|
| 2279 |
|
|
<a name="l02303"></a>02303 <span class="keyword">// LINK</span>
|
| 2280 |
|
|
<a name="l02304"></a>02304 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0101_0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af1b92ab55a321f316faf654b5d284caf">`MICROPC_LINK</a><span class="vhdlchar"></span> } :
|
| 2281 |
|
|
<a name="l02305"></a>02305 <span class="keyword">// UNLK</span>
|
| 2282 |
|
|
<a name="l02306"></a>02306 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0101_1</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a52c9810463f7dc671e021a7217259c04">`MICROPC_ULNK</a><span class="vhdlchar"></span> } :
|
| 2283 |
|
|
<a name="l02307"></a>02307 <span class="keyword">// MOVE USP to USP</span>
|
| 2284 |
|
|
<a name="l02308"></a>02308 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a999737a0b112cb8f4691dfc97278bc7e">`MICROPC_MOVE_USP_to_USP</a><span class="vhdlchar"></span> } :
|
| 2285 |
|
|
<a name="l02309"></a>02309 <span class="keyword">// MOVE USP to An</span>
|
| 2286 |
|
|
<a name="l02310"></a>02310 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">13'b0100_1110_0110_1</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a506e512a7df02654649a4275b676b5f7">`MICROPC_MOVE_USP_to_An</a><span class="vhdlchar"></span> } :
|
| 2287 |
|
|
<a name="l02311"></a>02311 <span class="keyword">// RESET</span>
|
| 2288 |
|
|
<a name="l02312"></a>02312 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0000</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a7ac5bfe9a8556912db6217142a3bb772">`MICROPC_RESET</a><span class="vhdlchar"></span> } :
|
| 2289 |
|
|
<a name="l02313"></a>02313 <span class="keyword">// NOP</span>
|
| 2290 |
|
|
<a name="l02314"></a>02314 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a836e1069d2a67eabcd01a92fcc2672f0">`MICROPC_NOP</a><span class="vhdlchar"></span> } :
|
| 2291 |
|
|
<a name="l02315"></a>02315 <span class="keyword">// STOP</span>
|
| 2292 |
|
|
<a name="l02316"></a>02316 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa23e89f5c79e7df7ff8ecf19a41ae572">`MICROPC_STOP</a><span class="vhdlchar"></span> } :
|
| 2293 |
|
|
<a name="l02317"></a>02317 <span class="keyword">// RTE,RTR</span>
|
| 2294 |
|
|
<a name="l02318"></a>02318 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0111</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a76b52a43dac42903243a54b46c4bd839">`MICROPC_RTE_RTR</a><span class="vhdlchar"></span> } :
|
| 2295 |
|
|
<a name="l02319"></a>02319 <span class="keyword">// RTS</span>
|
| 2296 |
|
|
<a name="l02320"></a>02320 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0101</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a70b05c3577437ee3a51c6b63859242c5">`MICROPC_RTS</a><span class="vhdlchar"></span> } :
|
| 2297 |
|
|
<a name="l02321"></a>02321 <span class="keyword">// TRAPV</span>
|
| 2298 |
|
|
<a name="l02322"></a>02322 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0110</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5038c753fc668ac678fe18251202305e">`MICROPC_TRAPV</a><span class="vhdlchar"></span> } :
|
| 2299 |
|
|
<a name="l02323"></a>02323 <span class="keyword">// JSR</span>
|
| 2300 |
|
|
<a name="l02324"></a>02324 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1110_10</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2301 |
|
|
<a name="l02325"></a>02325 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2302 |
|
|
<a name="l02326"></a>02326 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
| 2303 |
|
|
<a name="l02327"></a>02327 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a4a79b8f0394c470bd67ba6442fa12395">`MICROPC_JSR</a><span class="vhdlchar"></span> } :
|
| 2304 |
|
|
<a name="l02328"></a>02328 <span class="keyword">// JMP</span>
|
| 2305 |
|
|
<a name="l02329"></a>02329 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">10'b0100_1110_11</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2306 |
|
|
<a name="l02330"></a>02330 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2307 |
|
|
<a name="l02331"></a>02331 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span>))
|
| 2308 |
|
|
<a name="l02332"></a>02332 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a088577482bc02135d9aa7a58c1d0ed05">`MICROPC_JMP</a><span class="vhdlchar"></span> } :
|
| 2309 |
|
|
<a name="l02333"></a>02333 <span class="keyword">// ADDQ,SUBQ not An</span>
|
| 2310 |
|
|
<a name="l02334"></a>02334 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2311 |
|
|
<a name="l02335"></a>02335 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2312 |
|
|
<a name="l02336"></a>02336 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#af6f7102b5f4972ae11cad584ed87de14">`MICROPC_ADDQ_SUBQ_not_An</a><span class="vhdlchar"></span> } :
|
| 2313 |
|
|
<a name="l02337"></a>02337 <span class="keyword">// ADDQ,SUBQ An</span>
|
| 2314 |
|
|
<a name="l02338"></a>02338 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b00</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ae9cec5ce342a7d51efda687c24f35ab1">`MICROPC_ADDQ_SUBQ_An</a><span class="vhdlchar"></span> } :
|
| 2315 |
|
|
<a name="l02339"></a>02339 <span class="keyword">// Scc</span>
|
| 2316 |
|
|
<a name="l02340"></a>02340 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2317 |
|
|
<a name="l02341"></a>02341 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2318 |
|
|
<a name="l02342"></a>02342 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ac09a1b9ae5783634cc9228354105fc94">`MICROPC_Scc</a><span class="vhdlchar"></span> } :
|
| 2319 |
|
|
<a name="l02343"></a>02343 <span class="keyword">// DBcc</span>
|
| 2320 |
|
|
<a name="l02344"></a>02344 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a3d6a33ee86f4d37516a8afb60957b7ee">`MICROPC_DBcc</a><span class="vhdlchar"></span> } :
|
| 2321 |
|
|
<a name="l02345"></a>02345 <span class="keyword">// BSR</span>
|
| 2322 |
|
|
<a name="l02346"></a>02346 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#afefae415ee468c051f367b74183a122b">`MICROPC_BSR</a><span class="vhdlchar"></span> } :
|
| 2323 |
|
|
<a name="l02347"></a>02347 <span class="keyword">// Bcc,BRA</span>
|
| 2324 |
|
|
<a name="l02348"></a>02348 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] != <span class="vhdllogic">4'b0001</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#ae56342916e5e608a0fdd3a01a11688b0">`MICROPC_Bcc_BRA</a><span class="vhdlchar"></span> } :
|
| 2325 |
|
|
<a name="l02349"></a>02349 <span class="keyword">// MOVEQ</span>
|
| 2326 |
|
|
<a name="l02350"></a>02350 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0111</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span> ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a06f670a9b840bc7dda392686b0b53b41">`MICROPC_MOVEQ</a><span class="vhdlchar"></span> } :
|
| 2327 |
|
|
<a name="l02351"></a>02351 <span class="keyword">// CMP</span>
|
| 2328 |
|
|
<a name="l02352"></a>02352 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>) &&
|
| 2329 |
|
|
<a name="l02353"></a>02353 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
|
| 2330 |
|
|
<a name="l02354"></a>02354 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2331 |
|
|
<a name="l02355"></a>02355 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2332 |
|
|
<a name="l02356"></a>02356 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a2d30784cb012710f55727108a9b62cf1">`MICROPC_CMP</a><span class="vhdlchar"></span> } :
|
| 2333 |
|
|
<a name="l02357"></a>02357 <span class="keyword">// CMPA</span>
|
| 2334 |
|
|
<a name="l02358"></a>02358 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2335 |
|
|
<a name="l02359"></a>02359 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2336 |
|
|
<a name="l02360"></a>02360 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2337 |
|
|
<a name="l02361"></a>02361 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a853a2713ed61bd3e53e70297f62b654d">`MICROPC_CMPA</a><span class="vhdlchar"></span> } :
|
| 2338 |
|
|
<a name="l02362"></a>02362 <span class="keyword">// CMPM</span>
|
| 2339 |
|
|
<a name="l02363"></a>02363 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a118f99a150352cf71a51d13156218674">`MICROPC_CMPM</a><span class="vhdlchar"></span> } :
|
| 2340 |
|
|
<a name="l02364"></a>02364 <span class="keyword">// EOR</span>
|
| 2341 |
|
|
<a name="l02365"></a>02365 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2342 |
|
|
<a name="l02366"></a>02366 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2343 |
|
|
<a name="l02367"></a>02367 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#adaa788877b96a4c0cf1c9500aefc505a">`MICROPC_EOR</a><span class="vhdlchar"></span> } :
|
| 2344 |
|
|
<a name="l02368"></a>02368 <span class="keyword">// ADD to mem,SUB to mem,AND to mem,OR to mem</span>
|
| 2345 |
|
|
<a name="l02369"></a>02369 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) &&
|
| 2346 |
|
|
<a name="l02370"></a>02370 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10011</span> ||
|
| 2347 |
|
|
<a name="l02371"></a>02371 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10110</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10111</span> ||
|
| 2348 |
|
|
<a name="l02372"></a>02372 <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11011</span>) &&
|
| 2349 |
|
|
<a name="l02373"></a>02373 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2350 |
|
|
<a name="l02374"></a>02374 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#aa3942210285e132e0151143eca9103b4">`MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem</a><span class="vhdlchar"></span> } :
|
| 2351 |
|
|
<a name="l02375"></a>02375 <span class="keyword">// ADD to Dn,SUB to Dn,AND to Dn,OR to Dn</span>
|
| 2352 |
|
|
<a name="l02376"></a>02376 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) &&
|
| 2353 |
|
|
<a name="l02377"></a>02377 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>) &&
|
| 2354 |
|
|
<a name="l02378"></a>02378 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">12</span>] != <span class="vhdllogic">1'b1</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1'b1</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>) &&
|
| 2355 |
|
|
<a name="l02379"></a>02379 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2356 |
|
|
<a name="l02380"></a>02380 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2357 |
|
|
<a name="l02381"></a>02381 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#acdb63549759af21684d2fd6e3dad8eb7">`MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn</a><span class="vhdlchar"></span> } :
|
| 2358 |
|
|
<a name="l02382"></a>02382 <span class="keyword">// ADDA,SUBA</span>
|
| 2359 |
|
|
<a name="l02383"></a>02383 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b111</span>) &&
|
| 2360 |
|
|
<a name="l02384"></a>02384 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2361 |
|
|
<a name="l02385"></a>02385 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2362 |
|
|
<a name="l02386"></a>02386 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a02c5cdffb720a762c8790dbc86ab1a18">`MICROPC_ADDA_SUBA</a><span class="vhdlchar"></span> } :
|
| 2363 |
|
|
<a name="l02387"></a>02387 <span class="keyword">// ABCD,SBCD,ADDX,SUBX</span>
|
| 2364 |
|
|
<a name="l02388"></a>02388 ( ((<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10000</span>) ||
|
| 2365 |
|
|
<a name="l02389"></a>02389 ((<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b10100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">5'b11000</span>) ) ) ?
|
| 2366 |
|
|
<a name="l02390"></a>02390 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a52a25a790c5779d1d9c5d4b807f6e9e6">`MICROPC_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span> } :
|
| 2367 |
|
|
<a name="l02391"></a>02391 <span class="keyword">// EXG</span>
|
| 2368 |
|
|
<a name="l02392"></a>02392 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b101000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b101001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">6'b110001</span>) ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a5a514be119075b3c3ab64dfa849f3d9c">`MICROPC_EXG</a><span class="vhdlchar"></span> } :
|
| 2369 |
|
|
<a name="l02393"></a>02393 <span class="keyword">// MULS,MULU,DIVS,DIVU</span>
|
| 2370 |
|
|
<a name="l02394"></a>02394 ( (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>) && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2371 |
|
|
<a name="l02395"></a>02395 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> ||
|
| 2372 |
|
|
<a name="l02396"></a>02396 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_010</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_011</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_100</span>))
|
| 2373 |
|
|
<a name="l02397"></a>02397 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#abff7613e058d71dedd233ff63a37a724">`MICROPC_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> } :
|
| 2374 |
|
|
<a name="l02398"></a>02398 <span class="keyword">// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory</span>
|
| 2375 |
|
|
<a name="l02399"></a>02399 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1110</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">11</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> && <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span> &&
|
| 2376 |
|
|
<a name="l02400"></a>02400 (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b111</span> || (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_000</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b111_001</span>))
|
| 2377 |
|
|
<a name="l02401"></a>02401 ) ? { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a28f22a27673dd123f2ae53ac00c27c47">`MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory</a><span class="vhdlchar"></span> } :
|
| 2378 |
|
|
<a name="l02402"></a>02402 <span class="keyword">// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register</span>
|
| 2379 |
|
|
<a name="l02403"></a>02403 ( <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1110</span> && (<a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b00</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span> || <a class="code" href="classdecoder.html#aca42387025b7a44908a9c95b09ffd639">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ) ?
|
| 2380 |
|
|
<a name="l02404"></a>02404 { <a class="code" href="classdecoder.html#a0bab3a76a4f15fcb25284f461403e8ac">NO_TRAP</a>, <a class="code" href="ao68000_8v.html#a8a505b33f1c42b903dcb264862dda090">`MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register</a><span class="vhdlchar"></span> } :
|
| 2381 |
|
|
<a name="l02405"></a>02405
|
| 2382 |
|
|
<a name="l02406"></a>02406 <span class="keyword">// else</span>
|
| 2383 |
|
|
<a name="l02407"></a>02407
|
| 2384 |
|
|
<a name="l02408"></a>02408 { <a class="code" href="classdecoder.html#ae700aab6efd1c75556aeb4237f1d8c33">ILLEGAL_INSTRUCTION_TRAP</a>, <a class="code" href="classdecoder.html#aa6cefc0d2e58f3efccca7b784c2c9551">UNUSED_MICROPC</a> }
|
| 2385 |
|
|
<a name="l02409"></a>02409 ;
|
| 2386 |
|
|
<a name="l02410"></a>02410
|
| 2387 |
|
|
<a name="l02411"></a>02411 <span class="keyword">// load ea</span>
|
| 2388 |
|
|
<a name="l02412"></a>02412 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a37c251ae6bb47dd4f8a844cfc8f0757b">load_ea</a> =
|
| 2389 |
|
|
<a name="l02413"></a>02413 (
|
| 2390 |
|
|
<a name="l02414"></a>02414 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> || (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span>))) ||
|
| 2391 |
|
|
<a name="l02415"></a>02415 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> && <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span>) ||
|
| 2392 |
|
|
<a name="l02416"></a>02416 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span>)) ||
|
| 2393 |
|
|
<a name="l02417"></a>02417 (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span> && (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> || (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span>)))
|
| 2394 |
|
|
<a name="l02418"></a>02418 ) ? <span class="vhdllogic">9'd0</span> <span class="keyword">// no ea needed</span>
|
| 2395 |
|
|
<a name="l02419"></a>02419 :
|
| 2396 |
|
|
<a name="l02420"></a>02420 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b010</span> && (
|
| 2397 |
|
|
<a name="l02421"></a>02421 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
| 2398 |
|
|
<a name="l02422"></a>02422 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
| 2399 |
|
|
<a name="l02423"></a>02423 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2400 |
|
|
<a name="l02424"></a>02424 )) ? <a class="code" href="ao68000_8v.html#a52c9fefea5280f08cf24bac6373252ac">`MICROPC_LOAD_EA_An</a><span class="vhdlchar"></span> <span class="keyword">// (An)</span>
|
| 2401 |
|
|
<a name="l02425"></a>02425 :
|
| 2402 |
|
|
<a name="l02426"></a>02426 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b011</span> && (
|
| 2403 |
|
|
<a name="l02427"></a>02427 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
| 2404 |
|
|
<a name="l02428"></a>02428 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2405 |
|
|
<a name="l02429"></a>02429 )) ? <a class="code" href="ao68000_8v.html#aafdd46a7740d48b02e781d3136f7ce1d">`MICROPC_LOAD_EA_An_plus</a><span class="vhdlchar"></span> <span class="keyword">// (An)+</span>
|
| 2406 |
|
|
<a name="l02430"></a>02430 :
|
| 2407 |
|
|
<a name="l02431"></a>02431 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b100</span> && (
|
| 2408 |
|
|
<a name="l02432"></a>02432 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> ||
|
| 2409 |
|
|
<a name="l02433"></a>02433 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2410 |
|
|
<a name="l02434"></a>02434 )) ? <a class="code" href="ao68000_8v.html#a9b094e5044be3be8167a5b80bd274433">`MICROPC_LOAD_EA_minus_An</a><span class="vhdlchar"></span> <span class="keyword">// -(An)</span>
|
| 2411 |
|
|
<a name="l02435"></a>02435 :
|
| 2412 |
|
|
<a name="l02436"></a>02436 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b101</span> && (
|
| 2413 |
|
|
<a name="l02437"></a>02437 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
| 2414 |
|
|
<a name="l02438"></a>02438 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2415 |
|
|
<a name="l02439"></a>02439 )) ? <a class="code" href="ao68000_8v.html#a6e06b607b9a1a157e3753943d2b015e1">`MICROPC_LOAD_EA_d16_An</a><span class="vhdlchar"></span> <span class="keyword">// (d16, An)</span>
|
| 2416 |
|
|
<a name="l02440"></a>02440 :
|
| 2417 |
|
|
<a name="l02441"></a>02441 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b110</span> && (
|
| 2418 |
|
|
<a name="l02442"></a>02442 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
| 2419 |
|
|
<a name="l02443"></a>02443 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2420 |
|
|
<a name="l02444"></a>02444 )) ? <a class="code" href="ao68000_8v.html#aa80bb2f21742a46f59c3b8401c9209a3">`MICROPC_LOAD_EA_d8_An_Xn</a><span class="vhdlchar"></span> <span class="keyword">// (d8, An, Xn)</span>
|
| 2421 |
|
|
<a name="l02445"></a>02445 :
|
| 2422 |
|
|
<a name="l02446"></a>02446 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b000</span> && (
|
| 2423 |
|
|
<a name="l02447"></a>02447 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
| 2424 |
|
|
<a name="l02448"></a>02448 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2425 |
|
|
<a name="l02449"></a>02449 )) ? <a class="code" href="ao68000_8v.html#ade20a2ce9d926ed45a0c6e2d4c2bffad">`MICROPC_LOAD_EA_xxx_W</a><span class="vhdlchar"></span> <span class="keyword">// (xxx).W</span>
|
| 2426 |
|
|
<a name="l02450"></a>02450 :
|
| 2427 |
|
|
<a name="l02451"></a>02451 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b001</span> && (
|
| 2428 |
|
|
<a name="l02452"></a>02452 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> ||
|
| 2429 |
|
|
<a name="l02453"></a>02453 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2430 |
|
|
<a name="l02454"></a>02454 )) ? <a class="code" href="ao68000_8v.html#ac3601da82892ec91bbc958628eb6ed03">`MICROPC_LOAD_EA_xxx_L</a><span class="vhdlchar"></span> <span class="keyword">// (xxx).L</span>
|
| 2431 |
|
|
<a name="l02455"></a>02455 :
|
| 2432 |
|
|
<a name="l02456"></a>02456 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b010</span> && (
|
| 2433 |
|
|
<a name="l02457"></a>02457 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2434 |
|
|
<a name="l02458"></a>02458 )) ? <a class="code" href="ao68000_8v.html#a7cb86509757fa3419fbc8980724bd315">`MICROPC_LOAD_EA_d16_PC</a><span class="vhdlchar"></span> <span class="keyword">// (d16, PC)</span>
|
| 2435 |
|
|
<a name="l02459"></a>02459 :
|
| 2436 |
|
|
<a name="l02460"></a>02460 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b011</span> && (
|
| 2437 |
|
|
<a name="l02461"></a>02461 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2438 |
|
|
<a name="l02462"></a>02462 )) ? <a class="code" href="ao68000_8v.html#a785fdbd62d5c0da122ada9db07753b74">`MICROPC_LOAD_EA_d8_PC_Xn</a><span class="vhdlchar"></span> <span class="keyword">// (d8, PC, Xn)</span>
|
| 2439 |
13 |
alfik |
<a name="l02463"></a>02463 :
|
| 2440 |
14 |
alfik |
<a name="l02464"></a>02464 <a class="code" href="ao68000_8v.html#a92f21025346f2b9baad5ee3ea27c8833">`MICROPC_LOAD_EA_illegal_command</a><span class="vhdlchar"></span> <span class="keyword">// illegal command</span>
|
| 2441 |
|
|
<a name="l02465"></a>02465 ;
|
| 2442 |
|
|
<a name="l02466"></a>02466
|
| 2443 |
|
|
<a name="l02467"></a>02467 <span class="keyword">// perform ea read</span>
|
| 2444 |
|
|
<a name="l02468"></a>02468 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a0081e82b20c0976ecb13d48dcc0f7554">perform_ea_read</a> =
|
| 2445 |
|
|
<a name="l02469"></a>02469 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> ||
|
| 2446 |
|
|
<a name="l02470"></a>02470 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
| 2447 |
|
|
<a name="l02471"></a>02471 <a class="code" href="ao68000_8v.html#ae21eb6fc6455af78326135e407ee17eb">`MICROPC_PERFORM_EA_READ_Dn</a><span class="vhdlchar"></span> :
|
| 2448 |
|
|
<a name="l02472"></a>02472 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) ) ? <a class="code" href="ao68000_8v.html#a8d6dcbc97994c642a8da0be0fecc257a">`MICROPC_PERFORM_EA_READ_An</a><span class="vhdlchar"></span> :
|
| 2449 |
|
|
<a name="l02473"></a>02473 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b111</span> && <a class="code" href="classdecoder.html#ab7e5c6aab518d6f4ffb374d0d70774ed">ea_reg</a> == <span class="vhdllogic">3'b100</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
| 2450 |
|
|
<a name="l02474"></a>02474 <a class="code" href="ao68000_8v.html#ac2394d0cf1bffca610b4c8fb77881207">`MICROPC_PERFORM_EA_READ_imm</a><span class="vhdlchar"></span> :
|
| 2451 |
|
|
<a name="l02475"></a>02475 <a class="code" href="ao68000_8v.html#a2c70544d287306914c57f360847a1abd">`MICROPC_PERFORM_EA_READ_memory</a><span class="vhdlchar"></span>
|
| 2452 |
|
|
<a name="l02476"></a>02476 ;
|
| 2453 |
|
|
<a name="l02477"></a>02477
|
| 2454 |
|
|
<a name="l02478"></a>02478 <span class="keyword">// perform ea write</span>
|
| 2455 |
|
|
<a name="l02479"></a>02479 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a0a10ac646012973ca8a578403894590e">perform_ea_write</a> =
|
| 2456 |
|
|
<a name="l02480"></a>02480 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b000</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span> ||
|
| 2457 |
|
|
<a name="l02481"></a>02481 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>) ) ?
|
| 2458 |
|
|
<a name="l02482"></a>02482 <a class="code" href="ao68000_8v.html#acb05778c30ee2acc522c18f823a678ff">`MICROPC_PERFORM_EA_WRITE_Dn</a><span class="vhdlchar"></span> :
|
| 2459 |
|
|
<a name="l02483"></a>02483 ( <a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b001</span> && (<a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>) ) ? <a class="code" href="ao68000_8v.html#a20c5aa2df0d23f8bbdaccfca2bfed9f8">`MICROPC_PERFORM_EA_WRITE_An</a><span class="vhdlchar"></span> :
|
| 2460 |
|
|
<a name="l02484"></a>02484 <a class="code" href="ao68000_8v.html#ab8383cdb4a1df6d5f3296bb4244c7bab">`MICROPC_PERFORM_EA_WRITE_memory</a><span class="vhdlchar"></span>
|
| 2461 |
|
|
<a name="l02485"></a>02485 ;
|
| 2462 |
|
|
<a name="l02486"></a>02486
|
| 2463 |
|
|
<a name="l02487"></a>02487 <span class="keyword">// save ea</span>
|
| 2464 |
|
|
<a name="l02488"></a>02488 <span class="vhdlkeyword">assign</span> <a class="code" href="classdecoder.html#a8f1fa508fbad7ecd8f15a47ac97be0dc">save_ea</a> =
|
| 2465 |
|
|
<a name="l02489"></a>02489 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b011</span> && (
|
| 2466 |
|
|
<a name="l02490"></a>02490 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> ||
|
| 2467 |
|
|
<a name="l02491"></a>02491 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2468 |
|
|
<a name="l02492"></a>02492 )) ? <a class="code" href="ao68000_8v.html#a02dc58bcc0412d6c93647a1304f20443">`MICROPC_SAVE_EA_An_plus</a><span class="vhdlchar"></span> <span class="keyword">// (An)+</span>
|
| 2469 |
|
|
<a name="l02493"></a>02493 :
|
| 2470 |
|
|
<a name="l02494"></a>02494 (<a class="code" href="classdecoder.html#afd47a5f105fa04f0f04bb11e2cb07929">ea_mod</a> == <span class="vhdllogic">3'b100</span> && (
|
| 2471 |
|
|
<a name="l02495"></a>02495 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span> ||
|
| 2472 |
|
|
<a name="l02496"></a>02496 <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span> || <a class="code" href="classdecoder.html#aee711c3bd3db98552b24b1897f7a61a3">ea_type</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>
|
| 2473 |
|
|
<a name="l02497"></a>02497 )) ? <a class="code" href="ao68000_8v.html#ae4c00f630c944a41db777f7b51ee052d">`MICROPC_SAVE_EA_minus_An</a><span class="vhdlchar"></span> <span class="keyword">// -(An)</span>
|
| 2474 |
|
|
<a name="l02498"></a>02498 :
|
| 2475 |
|
|
<a name="l02499"></a>02499 <span class="vhdllogic">9'd0</span> <span class="keyword">// no ea needed</span>
|
| 2476 |
|
|
<a name="l02500"></a>02500 ;
|
| 2477 |
|
|
<a name="l02501"></a>02501
|
| 2478 |
|
|
<a name="l02502"></a>02502 <span class="vhdlkeyword">endmodule</span>
|
| 2479 |
|
|
<a name="l02503"></a>02503
|
| 2480 |
|
|
<a name="l02504"></a>02504 <span class="keyword">/***********************************************************************************************************************</span>
|
| 2481 |
|
|
<a name="l02505"></a>02505 <span class="keyword"> Condition</span>
|
| 2482 |
|
|
<a name="l02506"></a>02506 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 2483 |
|
|
<a name="l02507"></a>02507
|
| 2484 |
|
|
<a name="l02508"></a>02508
|
| 2485 |
|
|
<a name="l02514"></a><a class="code" href="classcondition.html">02514</a> <span class="vhdlkeyword">module</span> <a class="code" href="classcondition.html">condition</a>(
|
| 2486 |
|
|
<a name="l02515"></a><a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">02515</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a>,
|
| 2487 |
|
|
<a name="l02516"></a><a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">02516</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>,
|
| 2488 |
|
|
<a name="l02517"></a><a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">02517</a> <span class="vhdlkeyword">output</span> <a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">condition</a>
|
| 2489 |
|
|
<a name="l02518"></a>02518 );
|
| 2490 |
13 |
alfik |
<a name="l02519"></a>02519
|
| 2491 |
14 |
alfik |
<a name="l02520"></a><a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">02520</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a>,<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>,<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>,<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a>;
|
| 2492 |
|
|
<a name="l02521"></a>02521 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">0</span>];
|
| 2493 |
|
|
<a name="l02522"></a>02522 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">1</span>];
|
| 2494 |
|
|
<a name="l02523"></a>02523 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">2</span>];
|
| 2495 |
|
|
<a name="l02524"></a>02524 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> = <a class="code" href="classcondition.html#abac84a257e657e334871ef190cce9616">ccr</a>[<span class="vhdllogic">3</span>];
|
| 2496 |
|
|
<a name="l02525"></a>02525
|
| 2497 |
|
|
<a name="l02526"></a>02526 <span class="vhdlkeyword">assign</span> <a class="code" href="classcondition.html#acb19756f5d198b371846bce84e08d569">condition</a> = (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0000</span>) ? <span class="vhdllogic">1'b1</span> : <span class="keyword">// true</span>
|
| 2498 |
|
|
<a name="l02527"></a>02527 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0001</span>) ? <span class="vhdllogic">1'b0</span> : <span class="keyword">// false</span>
|
| 2499 |
|
|
<a name="l02528"></a>02528 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0010</span>) ? ~<a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// high</span>
|
| 2500 |
|
|
<a name="l02529"></a>02529 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0011</span>) ? <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> | <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// low or same</span>
|
| 2501 |
|
|
<a name="l02530"></a>02530 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0100</span>) ? ~<a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> : <span class="keyword">// carry clear</span>
|
| 2502 |
|
|
<a name="l02531"></a>02531 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0101</span>) ? <a class="code" href="classcondition.html#a3f5fcf283ca56b2cfe4269cff52ee925">C</a> : <span class="keyword">// carry set</span>
|
| 2503 |
|
|
<a name="l02532"></a>02532 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0110</span>) ? ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// not equal</span>
|
| 2504 |
|
|
<a name="l02533"></a>02533 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b0111</span>) ? <a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a> : <span class="keyword">// equal</span>
|
| 2505 |
|
|
<a name="l02534"></a>02534 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1000</span>) ? ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> : <span class="keyword">// overflow clear</span>
|
| 2506 |
|
|
<a name="l02535"></a>02535 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1001</span>) ? <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> : <span class="keyword">// overflow set</span>
|
| 2507 |
|
|
<a name="l02536"></a>02536 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1010</span>) ? ~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> : <span class="keyword">// plus</span>
|
| 2508 |
|
|
<a name="l02537"></a>02537 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1011</span>) ? <a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> : <span class="keyword">// minus</span>
|
| 2509 |
|
|
<a name="l02538"></a>02538 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1100</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// greater or equal</span>
|
| 2510 |
|
|
<a name="l02539"></a>02539 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1101</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// less than</span>
|
| 2511 |
|
|
<a name="l02540"></a>02540 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1110</span>) ? (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a> & ~<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) : <span class="keyword">// greater than</span>
|
| 2512 |
|
|
<a name="l02541"></a>02541 (<a class="code" href="classcondition.html#ad14bf5d3721fe9b8fe1f71fd2f5bd8a4">cond</a> == <span class="vhdllogic">4'b1111</span>) ? (<a class="code" href="classcondition.html#a88c2e82409be05b0e4072b5fd9fc6048">Z</a>) | (<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & ~<a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) | (~<a class="code" href="classcondition.html#a741ec53b25de93d917a650089cd95870">N</a> & <a class="code" href="classcondition.html#a4478c90a4669d8bd947561aaddfe3bfb">V</a>) : <span class="keyword">// less or equal</span>
|
| 2513 |
|
|
<a name="l02542"></a>02542 <span class="vhdllogic">1'b0</span>;
|
| 2514 |
|
|
<a name="l02543"></a>02543 <span class="vhdlkeyword">endmodule</span>
|
| 2515 |
|
|
<a name="l02544"></a>02544
|
| 2516 |
|
|
<a name="l02545"></a>02545 <span class="keyword">/***********************************************************************************************************************</span>
|
| 2517 |
|
|
<a name="l02546"></a>02546 <span class="keyword"> ALU</span>
|
| 2518 |
|
|
<a name="l02547"></a>02547 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 2519 |
|
|
<a name="l02548"></a>02548
|
| 2520 |
|
|
<a name="l02549"></a>02549
|
| 2521 |
|
|
<a name="l02558"></a><a class="code" href="classalu.html">02558</a> <span class="vhdlkeyword">module</span> <a class="code" href="classalu.html">alu</a>(
|
| 2522 |
|
|
<a name="l02559"></a><a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">02559</a> <span class="vhdlkeyword">input</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a>,
|
| 2523 |
|
|
<a name="l02560"></a><a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">02560</a> <span class="vhdlkeyword">input</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>,
|
| 2524 |
|
|
<a name="l02561"></a>02561
|
| 2525 |
|
|
<a name="l02562"></a>02562 <span class="keyword">// only zero bit</span>
|
| 2526 |
|
|
<a name="l02563"></a><a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">02563</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">address</a>,
|
| 2527 |
|
|
<a name="l02564"></a>02564 <span class="keyword">// only ir[11:9] and ir[6]</span>
|
| 2528 |
|
|
<a name="l02565"></a><a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">02565</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>,
|
| 2529 |
|
|
<a name="l02566"></a>02566 <span class="keyword">// byte 2'b00, word 2'b01, long 2'b10</span>
|
| 2530 |
|
|
<a name="l02567"></a><a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">02567</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>,
|
| 2531 |
|
|
<a name="l02568"></a>02568
|
| 2532 |
|
|
<a name="l02569"></a><a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">02569</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>,
|
| 2533 |
|
|
<a name="l02570"></a><a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">02570</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>,
|
| 2534 |
|
|
<a name="l02571"></a>02571
|
| 2535 |
|
|
<a name="l02572"></a><a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">02572</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>,
|
| 2536 |
|
|
<a name="l02573"></a><a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">02573</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>,
|
| 2537 |
|
|
<a name="l02574"></a>02574
|
| 2538 |
|
|
<a name="l02575"></a><a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">02575</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>,
|
| 2539 |
|
|
<a name="l02576"></a><a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">02576</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>,
|
| 2540 |
|
|
<a name="l02577"></a>02577
|
| 2541 |
|
|
<a name="l02578"></a><a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">02578</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a>,
|
| 2542 |
|
|
<a name="l02579"></a><a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">02579</a> <span class="vhdlkeyword">output</span> <a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a>
|
| 2543 |
|
|
<a name="l02580"></a>02580 );
|
| 2544 |
13 |
alfik |
<a name="l02581"></a>02581
|
| 2545 |
14 |
alfik |
<a name="l02582"></a>02582 <span class="keyword">//****************************************************** Altera-specific multiplication and division modules START</span>
|
| 2546 |
|
|
<a name="l02583"></a>02583 <span class="keyword">/* Multiplication and division modules.</span>
|
| 2547 |
|
|
<a name="l02584"></a>02584 <span class="keyword"> </span>
|
| 2548 |
|
|
<a name="l02585"></a>02585 <span class="keyword"> Currently this module contains:</span>
|
| 2549 |
|
|
<a name="l02586"></a>02586 <span class="keyword"> - <em>lpm_mult</em> instantiation from Altera Megafunction/LPM library,</span>
|
| 2550 |
|
|
<a name="l02587"></a>02587 <span class="keyword"> - a sequential state machine for division written by Frederic Requin</span>
|
| 2551 |
|
|
<a name="l02588"></a>02588 <span class="keyword"> */</span>
|
| 2552 |
|
|
<a name="l02589"></a>02589
|
| 2553 |
|
|
<a name="l02590"></a><a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">02590</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a> = <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>];
|
| 2554 |
|
|
<a name="l02591"></a>02591
|
| 2555 |
|
|
<a name="l02592"></a>02592 <span class="keyword">// 18-2 - division calculation, 1 - waiting for result read, 0 - idle</span>
|
| 2556 |
|
|
<a name="l02593"></a><a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">02593</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a>;
|
| 2557 |
|
|
<a name="l02594"></a><a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">02594</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">16</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>;
|
| 2558 |
|
|
<a name="l02595"></a><a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">02595</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>, <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>;
|
| 2559 |
|
|
<a name="l02596"></a>02596
|
| 2560 |
|
|
<a name="l02597"></a>02597 <span class="keyword">// Compute the difference with borrow</span>
|
| 2561 |
|
|
<a name="l02598"></a><a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">02598</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">32</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a> = (<a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> - <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>);
|
| 2562 |
|
|
<a name="l02599"></a>02599
|
| 2563 |
|
|
<a name="l02600"></a>02600 <span class="keyword">// Overflow flag: when (quotient >= 65536) or (signed division and (quotient >= 32768 or quotient < -32768))</span>
|
| 2564 |
|
|
<a name="l02601"></a><a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">02601</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> =
|
| 2565 |
|
|
<a name="l02602"></a>02602 (<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">16</span>] == <span class="vhdllogic">1'b1</span> ||
|
| 2566 |
|
|
<a name="l02603"></a>02603 (<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a> == <span class="vhdllogic">1'b1</span> && (
|
| 2567 |
|
|
<a name="l02604"></a>02604 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>) ||
|
| 2568 |
|
|
<a name="l02605"></a>02605 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">16'd32768</span>) )));
|
| 2569 |
|
|
<a name="l02606"></a>02606
|
| 2570 |
|
|
<a name="l02607"></a><a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">02607</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> =
|
| 2571 |
|
|
<a name="l02608"></a>02608 <span class="keyword">// positive quotient</span>
|
| 2572 |
|
|
<a name="l02609"></a>02609 (((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>]) & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] :
|
| 2573 |
|
|
<a name="l02610"></a>02610 <span class="keyword">// negative quotient</span>
|
| 2574 |
|
|
<a name="l02611"></a>02611 -<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 2575 |
|
|
<a name="l02612"></a>02612
|
| 2576 |
|
|
<a name="l02613"></a><a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">02613</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a> =
|
| 2577 |
|
|
<a name="l02614"></a>02614 <span class="keyword">// positive remainder</span>
|
| 2578 |
|
|
<a name="l02615"></a>02615 ((<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] :
|
| 2579 |
|
|
<a name="l02616"></a>02616 <span class="keyword">// negative remainder</span>
|
| 2580 |
|
|
<a name="l02617"></a>02617 -<a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 2581 |
|
|
<a name="l02618"></a>02618
|
| 2582 |
|
|
<a name="l02619"></a><a class="code" href="classalu.html#a833db0d5eda614d712b846b259c0f4d3">02619</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 2583 |
|
|
<a name="l02620"></a>02620 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 2584 |
|
|
<a name="l02621"></a>02621 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd0</span>;
|
| 2585 |
|
|
<a name="l02622"></a>02622 <span class="vhdlkeyword">end</span>
|
| 2586 |
|
|
<a name="l02623"></a>02623 <span class="keyword">// Cycle #0 : load the registers</span>
|
| 2587 |
|
|
<a name="l02624"></a>02624 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 2588 |
|
|
<a name="l02625"></a>02625 <span class="keyword">// 17 cycles to finish + wait state</span>
|
| 2589 |
|
|
<a name="l02626"></a>02626 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd18</span>;
|
| 2590 |
|
|
<a name="l02627"></a>02627 <span class="keyword">// Clear the quotient</span>
|
| 2591 |
|
|
<a name="l02628"></a>02628 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= <span class="vhdllogic">17'd0</span>;
|
| 2592 |
|
|
<a name="l02629"></a>02629
|
| 2593 |
|
|
<a name="l02630"></a>02630 <span class="keyword">// Unsigned divide or positive numerator</span>
|
| 2594 |
|
|
<a name="l02631"></a>02631 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>])) <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 2595 |
|
|
<a name="l02632"></a>02632 <span class="keyword">// Negative numerator</span>
|
| 2596 |
|
|
<a name="l02633"></a>02633 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= -<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 2597 |
|
|
<a name="l02634"></a>02634
|
| 2598 |
|
|
<a name="l02635"></a>02635 <span class="keyword">// Unsigned divide or positive denominator</span>
|
| 2599 |
|
|
<a name="l02636"></a>02636 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>])) <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
| 2600 |
|
|
<a name="l02637"></a>02637 <span class="keyword">// Negative denominator</span>
|
| 2601 |
|
|
<a name="l02638"></a>02638 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {-<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
| 2602 |
|
|
<a name="l02639"></a>02639 <span class="vhdlkeyword">end</span>
|
| 2603 |
|
|
<a name="l02640"></a>02640 <span class="keyword">// Cycles #1-17 : division calculation</span>
|
| 2604 |
|
|
<a name="l02641"></a>02641 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> > <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
| 2605 |
|
|
<a name="l02642"></a>02642 <span class="keyword">// Check difference's sign</span>
|
| 2606 |
|
|
<a name="l02643"></a>02643 <span class="vhdlkeyword">if</span> (!<a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">32</span>]) <span class="vhdlkeyword">begin</span>
|
| 2607 |
|
|
<a name="l02644"></a>02644 <span class="keyword">// Difference is positive : shift a one</span>
|
| 2608 |
|
|
<a name="l02645"></a>02645 <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 2609 |
|
|
<a name="l02646"></a>02646 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b1</span>};
|
| 2610 |
|
|
<a name="l02647"></a>02647 <span class="vhdlkeyword">end</span>
|
| 2611 |
|
|
<a name="l02648"></a>02648 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 2612 |
|
|
<a name="l02649"></a>02649 <span class="keyword">// Difference is negative : shift a zero</span>
|
| 2613 |
|
|
<a name="l02650"></a>02650 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
| 2614 |
|
|
<a name="l02651"></a>02651 <span class="vhdlkeyword">end</span>
|
| 2615 |
|
|
<a name="l02652"></a>02652 <span class="keyword">// Shift right divider</span>
|
| 2616 |
|
|
<a name="l02653"></a>02653 <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
| 2617 |
|
|
<a name="l02654"></a>02654 <span class="keyword">// Count one bit</span>
|
| 2618 |
|
|
<a name="l02655"></a>02655 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
| 2619 |
|
|
<a name="l02656"></a>02656 <span class="vhdlkeyword">end</span>
|
| 2620 |
|
|
<a name="l02657"></a>02657 <span class="keyword">// result read</span>
|
| 2621 |
|
|
<a name="l02658"></a>02658 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
| 2622 |
|
|
<a name="l02659"></a>02659 <span class="keyword">// goto idle</span>
|
| 2623 |
|
|
<a name="l02660"></a>02660 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
| 2624 |
|
|
<a name="l02661"></a>02661 <span class="vhdlkeyword">end</span>
|
| 2625 |
|
|
<a name="l02662"></a>02662 <span class="vhdlkeyword">end</span>
|
| 2626 |
|
|
<a name="l02663"></a>02663
|
| 2627 |
|
|
<a name="l02664"></a>02664 <span class="keyword">// MULS/MULU: 16-bit operand1[15:0] signed/unsigned * operand2[15:0] signed/unsigned = 32-bit result signed/unsigned</span>
|
| 2628 |
|
|
<a name="l02665"></a>02665 <span class="keyword">// Optimization by Frederic Requin</span>
|
| 2629 |
|
|
<a name="l02666"></a><a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">02666</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">33</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>;
|
| 2630 |
|
|
<a name="l02667"></a>02667
|
| 2631 |
|
|
<a name="l02668"></a><a class="code" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">02668</a> <a class="code" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">lpm_mult</a> <span class="vhdlchar">muls</span>(
|
| 2632 |
|
|
<a name="l02669"></a>02669 .<a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> (<a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a>),
|
| 2633 |
|
|
<a name="l02670"></a>02670 .<span class="vhdlchar">dataa</span> ({<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>]}),
|
| 2634 |
|
|
<a name="l02671"></a>02671 .<span class="vhdlchar">datab</span> ({<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>] & <a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>]}),
|
| 2635 |
|
|
<a name="l02672"></a>02672 .<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>)
|
| 2636 |
|
|
<a name="l02673"></a>02673 );
|
| 2637 |
|
|
<a name="l02674"></a>02674 <span class="vhdlkeyword">defparam</span>
|
| 2638 |
|
|
<a name="l02675"></a>02675 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widtha</span> = <span class="vhdllogic">17</span>,
|
| 2639 |
|
|
<a name="l02676"></a>02676 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widthb</span> = <span class="vhdllogic">17</span>,
|
| 2640 |
|
|
<a name="l02677"></a>02677 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_widthp</span> = <span class="vhdllogic">34</span>,
|
| 2641 |
|
|
<a name="l02678"></a>02678 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_representation</span> = <span class="keyword">"SIGNED"</span>,
|
| 2642 |
|
|
<a name="l02679"></a>02679 <span class="vhdlchar">muls</span>.<span class="vhdlchar">lpm_pipeline</span> = <span class="vhdllogic">1</span>;
|
| 2643 |
|
|
<a name="l02680"></a>02680
|
| 2644 |
|
|
<a name="l02681"></a>02681 <span class="keyword">// multiplication ready in one cycle, division ready when div_count in waiting or idle state</span>
|
| 2645 |
|
|
<a name="l02682"></a>02682 <span class="vhdlkeyword">assign</span> <a class="code" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a> = (<a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd1</span> || <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>);
|
| 2646 |
|
|
<a name="l02683"></a>02683
|
| 2647 |
|
|
<a name="l02684"></a>02684 <span class="keyword">//****************************************************** Altera-specific multiplication and division modules END</span>
|
| 2648 |
|
|
<a name="l02685"></a>02685
|
| 2649 |
|
|
<a name="l02686"></a>02686 <span class="keyword">// ALU internal defines</span>
|
| 2650 |
|
|
<a name="l02687"></a><a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">02687</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? operand2[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? operand2[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>])
|
| 2651 |
|
|
<a name="l02688"></a>02688
|
| 2652 |
|
|
<a name="l02689"></a><a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">02689</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">Dm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? operand1[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? operand1[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>])
|
| 2653 |
|
|
<a name="l02690"></a>02690
|
| 2654 |
|
|
<a name="l02691"></a><a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">02691</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">Rm</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? result[<span class="vhdllogic">7</span>] : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? result[<span class="vhdllogic">15</span>] : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>])
|
| 2655 |
|
|
<a name="l02692"></a>02692
|
| 2656 |
|
|
<a name="l02693"></a><a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">02693</a> <span class="preprocessor">`define</span> <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a> ((<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>) : (<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) : (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>))
|
| 2657 |
|
|
<a name="l02694"></a>02694
|
| 2658 |
|
|
<a name="l02695"></a>02695 <span class="keyword">// ALU operations</span>
|
| 2659 |
13 |
alfik |
<a name="l02696"></a>02696
|
| 2660 |
14 |
alfik |
<a name="l02697"></a><a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">02697</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a>;
|
| 2661 |
|
|
<a name="l02698"></a><a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">02698</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a>;
|
| 2662 |
|
|
<a name="l02699"></a>02699
|
| 2663 |
|
|
<a name="l02700"></a><a class="code" href="classalu.html#a04b10dc82e8a06c3856bfd16a7e18d06">02700</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 2664 |
|
|
<a name="l02701"></a>02701 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 2665 |
|
|
<a name="l02702"></a>02702 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b1</span>, <span class="vhdllogic">2'b0</span>, <span class="vhdllogic">3'b111</span>, <span class="vhdllogic">8'b0</span> };
|
| 2666 |
|
|
<a name="l02703"></a>02703 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <span class="vhdllogic">32'd0</span>;
|
| 2667 |
|
|
<a name="l02704"></a>02704 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 2668 |
|
|
<a name="l02705"></a>02705 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <span class="vhdllogic">3'b0</span>;
|
| 2669 |
|
|
<a name="l02706"></a>02706 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
| 2670 |
|
|
<a name="l02707"></a>02707 <span class="vhdlkeyword">end</span>
|
| 2671 |
|
|
<a name="l02708"></a>02708 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 2672 |
|
|
<a name="l02709"></a>02709 <span class="vhdlkeyword">case</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>)
|
| 2673 |
|
|
<a name="l02710"></a>02710 <a class="code" href="ao68000_8v.html#a687e6310453b4cedb64aa6e66b058c18">`ALU_SR_SET_INTERRUPT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2674 |
|
|
<a name="l02711"></a>02711 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
| 2675 |
|
|
<a name="l02712"></a>02712 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b1</span>;
|
| 2676 |
|
|
<a name="l02713"></a>02713 <span class="vhdlkeyword">end</span>
|
| 2677 |
|
|
<a name="l02714"></a>02714
|
| 2678 |
|
|
<a name="l02715"></a>02715 <a class="code" href="ao68000_8v.html#ac9fc44b8d3bbcd6c742f1ba074fc668d">`ALU_SR_SET_TRAP</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2679 |
|
|
<a name="l02716"></a>02716 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 2680 |
|
|
<a name="l02717"></a>02717 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">11</span>], <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 2681 |
|
|
<a name="l02718"></a>02718 <span class="vhdlkeyword">end</span>
|
| 2682 |
|
|
<a name="l02719"></a>02719 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 2683 |
|
|
<a name="l02720"></a>02720 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">0</span>] };
|
| 2684 |
|
|
<a name="l02721"></a>02721 <span class="vhdlkeyword">end</span>
|
| 2685 |
|
|
<a name="l02722"></a>02722 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
| 2686 |
|
|
<a name="l02723"></a>02723 <span class="vhdlkeyword">end</span>
|
| 2687 |
|
|
<a name="l02724"></a>02724
|
| 2688 |
|
|
<a name="l02725"></a>02725 <a class="code" href="ao68000_8v.html#a59147ff996e0ba496f1f06d7a06decae">`ALU_MOVEP_M2R_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2689 |
|
|
<a name="l02726"></a>02726 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2690 |
|
|
<a name="l02727"></a>02727 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2691 |
|
|
<a name="l02728"></a>02728 <span class="keyword">//CCR: no change</span>
|
| 2692 |
|
|
<a name="l02729"></a>02729 <span class="vhdlkeyword">end</span>
|
| 2693 |
|
|
<a name="l02730"></a>02730 <a class="code" href="ao68000_8v.html#a3b1155f3496b0fc984e5418e09586bf5">`ALU_MOVEP_M2R_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2694 |
|
|
<a name="l02731"></a>02731 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2695 |
|
|
<a name="l02732"></a>02732 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2696 |
|
|
<a name="l02733"></a>02733 <span class="keyword">//CCR: no change</span>
|
| 2697 |
|
|
<a name="l02734"></a>02734 <span class="vhdlkeyword">end</span>
|
| 2698 |
|
|
<a name="l02735"></a>02735 <a class="code" href="ao68000_8v.html#a5458c8548afc8f7517bdc582c9946b2f">`ALU_MOVEP_M2R_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2699 |
|
|
<a name="l02736"></a>02736 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2700 |
|
|
<a name="l02737"></a>02737 <span class="keyword">//CCR: no change</span>
|
| 2701 |
|
|
<a name="l02738"></a>02738 <span class="vhdlkeyword">end</span>
|
| 2702 |
|
|
<a name="l02739"></a>02739 <a class="code" href="ao68000_8v.html#a8ec0074ca9c5cfec15aa93b92353e09b">`ALU_MOVEP_M2R_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2703 |
|
|
<a name="l02740"></a>02740 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2704 |
|
|
<a name="l02741"></a>02741 <span class="keyword">//CCR: no change</span>
|
| 2705 |
|
|
<a name="l02742"></a>02742 <span class="vhdlkeyword">end</span>
|
| 2706 |
|
|
<a name="l02743"></a>02743
|
| 2707 |
12 |
alfik |
<a name="l02744"></a>02744
|
| 2708 |
14 |
alfik |
<a name="l02745"></a>02745 <a class="code" href="ao68000_8v.html#aab7548aba43c6c12259a2a154ce2982b">`ALU_MOVEP_R2M_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2709 |
|
|
<a name="l02746"></a>02746 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>];
|
| 2710 |
|
|
<a name="l02747"></a>02747 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
| 2711 |
|
|
<a name="l02748"></a>02748 <span class="keyword">// CCR: no change</span>
|
| 2712 |
|
|
<a name="l02749"></a>02749 <span class="vhdlkeyword">end</span>
|
| 2713 |
|
|
<a name="l02750"></a>02750 <a class="code" href="ao68000_8v.html#a9918f4663f481092da549f3cb008721d">`ALU_MOVEP_R2M_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2714 |
|
|
<a name="l02751"></a>02751 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>];
|
| 2715 |
|
|
<a name="l02752"></a>02752 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2716 |
|
|
<a name="l02753"></a>02753 <span class="keyword">// CCR: no change</span>
|
| 2717 |
|
|
<a name="l02754"></a>02754 <span class="vhdlkeyword">end</span>
|
| 2718 |
|
|
<a name="l02755"></a>02755 <a class="code" href="ao68000_8v.html#aee5fc91f58c97ffa4d252e127c9e4226">`ALU_MOVEP_R2M_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2719 |
|
|
<a name="l02756"></a>02756 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
| 2720 |
|
|
<a name="l02757"></a>02757 <span class="keyword">// CCR: no change</span>
|
| 2721 |
|
|
<a name="l02758"></a>02758 <span class="vhdlkeyword">end</span>
|
| 2722 |
|
|
<a name="l02759"></a>02759 <a class="code" href="ao68000_8v.html#a0bc85184fda7b9fcbf00afa29be91d42">`ALU_MOVEP_R2M_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2723 |
|
|
<a name="l02760"></a>02760 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2724 |
|
|
<a name="l02761"></a>02761 <span class="keyword">// CCR: no change</span>
|
| 2725 |
|
|
<a name="l02762"></a>02762 <span class="vhdlkeyword">end</span>
|
| 2726 |
|
|
<a name="l02763"></a>02763
|
| 2727 |
|
|
<a name="l02764"></a>02764
|
| 2728 |
|
|
<a name="l02765"></a>02765
|
| 2729 |
|
|
<a name="l02766"></a>02766 <a class="code" href="ao68000_8v.html#a6a119b7268e4e0a78e0307ba0c693ccb">`ALU_SIGN_EXTEND</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2730 |
|
|
<a name="l02767"></a>02767 <span class="keyword">// move operand1 with sign-extension to result</span>
|
| 2731 |
|
|
<a name="l02768"></a>02768 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 2732 |
|
|
<a name="l02769"></a>02769 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 2733 |
|
|
<a name="l02770"></a>02770 <span class="vhdlkeyword">end</span>
|
| 2734 |
|
|
<a name="l02771"></a>02771 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 2735 |
|
|
<a name="l02772"></a>02772 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 2736 |
|
|
<a name="l02773"></a>02773 <span class="vhdlkeyword">end</span>
|
| 2737 |
|
|
<a name="l02774"></a>02774 <span class="keyword">// CCR: no change</span>
|
| 2738 |
|
|
<a name="l02775"></a>02775 <span class="vhdlkeyword">end</span>
|
| 2739 |
|
|
<a name="l02776"></a>02776
|
| 2740 |
|
|
<a name="l02777"></a>02777 <a class="code" href="ao68000_8v.html#ae497ab0b3e0550245c333bdb426d4236">`ALU_ARITHMETIC_LOGIC</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2741 |
|
|
<a name="l02778"></a>02778
|
| 2742 |
|
|
<a name="l02779"></a>02779 <span class="keyword">// OR,OR to mem,OR to Dn</span>
|
| 2743 |
|
|
<a name="l02780"></a>02780 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ||
|
| 2744 |
|
|
<a name="l02781"></a>02781 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>)
|
| 2745 |
|
|
<a name="l02782"></a>02782 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] | <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 2746 |
|
|
<a name="l02783"></a>02783 <span class="keyword">// AND,AND to mem,AND to Dn</span>
|
| 2747 |
|
|
<a name="l02784"></a>02784 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b001</span>) ||
|
| 2748 |
|
|
<a name="l02785"></a>02785 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span>)
|
| 2749 |
|
|
<a name="l02786"></a>02786 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 2750 |
|
|
<a name="l02787"></a>02787 <span class="keyword">// EORI,EOR</span>
|
| 2751 |
|
|
<a name="l02788"></a>02788 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b101</span>) ||
|
| 2752 |
|
|
<a name="l02789"></a>02789 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>)
|
| 2753 |
|
|
<a name="l02790"></a>02790 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 2754 |
|
|
<a name="l02791"></a>02791 <span class="keyword">// ADD,ADD to mem,ADD to Dn,ADDQ</span>
|
| 2755 |
|
|
<a name="l02792"></a>02792 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
| 2756 |
|
|
<a name="l02793"></a>02793 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
| 2757 |
|
|
<a name="l02794"></a>02794 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
| 2758 |
|
|
<a name="l02795"></a>02795 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 2759 |
|
|
<a name="l02796"></a>02796 <span class="keyword">// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ</span>
|
| 2760 |
|
|
<a name="l02797"></a>02797 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
| 2761 |
|
|
<a name="l02798"></a>02798 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
| 2762 |
|
|
<a name="l02799"></a>02799 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
| 2763 |
|
|
<a name="l02800"></a>02800 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
| 2764 |
|
|
<a name="l02801"></a>02801 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>)) ||
|
| 2765 |
|
|
<a name="l02802"></a>02802 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
| 2766 |
|
|
<a name="l02803"></a>02803 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 2767 |
|
|
<a name="l02804"></a>02804
|
| 2768 |
|
|
<a name="l02805"></a>02805 <span class="keyword">// Z</span>
|
| 2769 |
|
|
<a name="l02806"></a>02806 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 2770 |
|
|
<a name="l02807"></a>02807 <span class="keyword">// N</span>
|
| 2771 |
|
|
<a name="l02808"></a>02808 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 2772 |
|
|
<a name="l02809"></a>02809
|
| 2773 |
|
|
<a name="l02810"></a>02810 <span class="keyword">// CMPI,CMPM,CMP</span>
|
| 2774 |
|
|
<a name="l02811"></a>02811 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
| 2775 |
|
|
<a name="l02812"></a>02812 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
| 2776 |
|
|
<a name="l02813"></a>02813 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>))
|
| 2777 |
|
|
<a name="l02814"></a>02814 ) <span class="vhdlkeyword">begin</span>
|
| 2778 |
|
|
<a name="l02815"></a>02815 <span class="keyword">// C,V</span>
|
| 2779 |
|
|
<a name="l02816"></a>02816 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2780 |
|
|
<a name="l02817"></a>02817 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2781 |
|
|
<a name="l02818"></a>02818 <span class="keyword">// X not affected</span>
|
| 2782 |
|
|
<a name="l02819"></a>02819 <span class="vhdlkeyword">end</span>
|
| 2783 |
|
|
<a name="l02820"></a>02820 <span class="keyword">// ADDI,ADD to mem,ADD to Dn,ADDQ</span>
|
| 2784 |
|
|
<a name="l02821"></a>02821 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
| 2785 |
|
|
<a name="l02822"></a>02822 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
| 2786 |
|
|
<a name="l02823"></a>02823 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
| 2787 |
|
|
<a name="l02824"></a>02824 ) <span class="vhdlkeyword">begin</span>
|
| 2788 |
|
|
<a name="l02825"></a>02825 <span class="keyword">// C,X,V</span>
|
| 2789 |
|
|
<a name="l02826"></a>02826 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2790 |
|
|
<a name="l02827"></a>02827 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 2791 |
|
|
<a name="l02828"></a>02828 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2792 |
|
|
<a name="l02829"></a>02829 <span class="vhdlkeyword">end</span>
|
| 2793 |
|
|
<a name="l02830"></a>02830 <span class="keyword">// SUBI,SUB to mem,SUB to Dn,SUBQ</span>
|
| 2794 |
|
|
<a name="l02831"></a>02831 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
| 2795 |
|
|
<a name="l02832"></a>02832 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
| 2796 |
|
|
<a name="l02833"></a>02833 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
| 2797 |
|
|
<a name="l02834"></a>02834 ) <span class="vhdlkeyword">begin</span>
|
| 2798 |
|
|
<a name="l02835"></a>02835 <span class="keyword">// C,X,V</span>
|
| 2799 |
|
|
<a name="l02836"></a>02836 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2800 |
|
|
<a name="l02837"></a>02837 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 2801 |
|
|
<a name="l02838"></a>02838 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2802 |
|
|
<a name="l02839"></a>02839 <span class="vhdlkeyword">end</span>
|
| 2803 |
|
|
<a name="l02840"></a>02840 <span class="keyword">// ANDI,EORI,ORI,EOR,OR to mem,AND to mem,OR to Dn,AND to Dn</span>
|
| 2804 |
|
|
<a name="l02841"></a>02841 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 2805 |
|
|
<a name="l02842"></a>02842 <span class="keyword">// C,V</span>
|
| 2806 |
|
|
<a name="l02843"></a>02843 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 2807 |
|
|
<a name="l02844"></a>02844 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 2808 |
|
|
<a name="l02845"></a>02845 <span class="keyword">// X not affected</span>
|
| 2809 |
|
|
<a name="l02846"></a>02846 <span class="vhdlkeyword">end</span>
|
| 2810 |
|
|
<a name="l02847"></a>02847 <span class="vhdlkeyword">end</span>
|
| 2811 |
|
|
<a name="l02848"></a>02848
|
| 2812 |
|
|
<a name="l02849"></a>02849 <a class="code" href="ao68000_8v.html#a3e54001e73374bd4f7cfda3de55bd944">`ALU_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 259 LE</span>
|
| 2813 |
|
|
<a name="l02850"></a>02850 <span class="keyword">// ABCD</span>
|
| 2814 |
|
|
<a name="l02851"></a>02851 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b100</span> ) <span class="vhdlkeyword">begin</span>
|
| 2815 |
|
|
<a name="l02852"></a>02852 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">4'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 2816 |
|
|
<a name="l02853"></a>02853 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
| 2817 |
|
|
<a name="l02854"></a>02854
|
| 2818 |
|
|
<a name="l02855"></a>02855 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 2819 |
|
|
<a name="l02856"></a>02856
|
| 2820 |
|
|
<a name="l02857"></a>02857 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
| 2821 |
|
|
<a name="l02858"></a>02858 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h1F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd2</span>) :
|
| 2822 |
|
|
<a name="l02859"></a>02859 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h0F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd1</span>) :
|
| 2823 |
|
|
<a name="l02860"></a>02860 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 2824 |
|
|
<a name="l02861"></a>02861 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 2825 |
|
|
<a name="l02862"></a>02862
|
| 2826 |
|
|
<a name="l02863"></a>02863 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
| 2827 |
|
|
<a name="l02864"></a>02864 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
| 2828 |
|
|
<a name="l02865"></a>02865
|
| 2829 |
|
|
<a name="l02866"></a>02866 <span class="keyword">// C</span>
|
| 2830 |
|
|
<a name="l02867"></a>02867 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 2831 |
|
|
<a name="l02868"></a>02868 <span class="keyword">// X = C</span>
|
| 2832 |
|
|
<a name="l02869"></a>02869 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 2833 |
|
|
<a name="l02870"></a>02870
|
| 2834 |
|
|
<a name="l02871"></a>02871 <span class="keyword">// V</span>
|
| 2835 |
|
|
<a name="l02872"></a>02872 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 2836 |
|
|
<a name="l02873"></a>02873 <span class="vhdlkeyword">end</span>
|
| 2837 |
|
|
<a name="l02874"></a>02874 <span class="keyword">// SBCD</span>
|
| 2838 |
|
|
<a name="l02875"></a>02875 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 2839 |
|
|
<a name="l02876"></a>02876
|
| 2840 |
|
|
<a name="l02877"></a>02877 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">5'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 2841 |
|
|
<a name="l02878"></a>02878 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
| 2842 |
|
|
<a name="l02879"></a>02879
|
| 2843 |
|
|
<a name="l02880"></a>02880 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 2844 |
|
|
<a name="l02881"></a>02881
|
| 2845 |
|
|
<a name="l02882"></a>02882 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
| 2846 |
|
|
<a name="l02883"></a>02883 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd16</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd2</span>) :
|
| 2847 |
|
|
<a name="l02884"></a>02884 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd1</span>) :
|
| 2848 |
|
|
<a name="l02885"></a>02885 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 2849 |
|
|
<a name="l02886"></a>02886 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 2850 |
|
|
<a name="l02887"></a>02887
|
| 2851 |
|
|
<a name="l02888"></a>02888 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
| 2852 |
|
|
<a name="l02889"></a>02889 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
| 2853 |
|
|
<a name="l02890"></a>02890
|
| 2854 |
|
|
<a name="l02891"></a>02891 <span class="keyword">// C</span>
|
| 2855 |
|
|
<a name="l02892"></a>02892 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 2856 |
|
|
<a name="l02893"></a>02893 <span class="keyword">// X = C</span>
|
| 2857 |
|
|
<a name="l02894"></a>02894 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 2858 |
|
|
<a name="l02895"></a>02895
|
| 2859 |
|
|
<a name="l02896"></a>02896 <span class="keyword">// V</span>
|
| 2860 |
|
|
<a name="l02897"></a>02897 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 2861 |
|
|
<a name="l02898"></a>02898 <span class="vhdlkeyword">end</span>
|
| 2862 |
|
|
<a name="l02899"></a>02899 <span class="keyword">// ADDX</span>
|
| 2863 |
|
|
<a name="l02900"></a>02900 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
| 2864 |
|
|
<a name="l02901"></a>02901 <span class="keyword">// SUBX</span>
|
| 2865 |
|
|
<a name="l02902"></a>02902 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
| 2866 |
|
|
<a name="l02903"></a>02903
|
| 2867 |
|
|
<a name="l02904"></a>02904 <span class="keyword">// Z</span>
|
| 2868 |
|
|
<a name="l02905"></a>02905 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 2869 |
|
|
<a name="l02906"></a>02906 <span class="keyword">// N</span>
|
| 2870 |
|
|
<a name="l02907"></a>02907 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 2871 |
|
|
<a name="l02908"></a>02908
|
| 2872 |
|
|
<a name="l02909"></a>02909 <span class="keyword">// ADDX</span>
|
| 2873 |
|
|
<a name="l02910"></a>02910 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <span class="vhdlkeyword">begin</span>
|
| 2874 |
|
|
<a name="l02911"></a>02911 <span class="keyword">// C,X,V</span>
|
| 2875 |
|
|
<a name="l02912"></a>02912 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2876 |
|
|
<a name="l02913"></a>02913 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 2877 |
|
|
<a name="l02914"></a>02914 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2878 |
|
|
<a name="l02915"></a>02915 <span class="vhdlkeyword">end</span>
|
| 2879 |
|
|
<a name="l02916"></a>02916 <span class="keyword">// SUBX</span>
|
| 2880 |
|
|
<a name="l02917"></a>02917 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <span class="vhdlkeyword">begin</span>
|
| 2881 |
|
|
<a name="l02918"></a>02918 <span class="keyword">// C,X,V</span>
|
| 2882 |
|
|
<a name="l02919"></a>02919 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2883 |
|
|
<a name="l02920"></a>02920 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 2884 |
|
|
<a name="l02921"></a>02921 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 2885 |
|
|
<a name="l02922"></a>02922 <span class="vhdlkeyword">end</span>
|
| 2886 |
|
|
<a name="l02923"></a>02923 <span class="vhdlkeyword">end</span>
|
| 2887 |
|
|
<a name="l02924"></a>02924
|
| 2888 |
|
|
<a name="l02925"></a>02925 <a class="code" href="ao68000_8v.html#ac444f659b2726fd335e839dfadabbfe3">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2889 |
|
|
<a name="l02926"></a>02926
|
| 2890 |
|
|
<a name="l02927"></a>02927 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 2891 |
|
|
<a name="l02928"></a>02928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 2892 |
|
|
<a name="l02929"></a>02929 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 2893 |
|
|
<a name="l02930"></a>02930
|
| 2894 |
|
|
<a name="l02931"></a>02931 <span class="keyword">// X for ASL</span>
|
| 2895 |
|
|
<a name="l02932"></a>02932 <span class="keyword">//if(operand2[5:0] > 6'b0 && ir[8] == 1'b1 && ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) ) begin</span>
|
| 2896 |
|
|
<a name="l02933"></a>02933 <span class="keyword">// X set to Dm</span>
|
| 2897 |
|
|
<a name="l02934"></a>02934 <span class="keyword">// sr[4] <= `Dm;</span>
|
| 2898 |
|
|
<a name="l02935"></a>02935 <span class="keyword">//end</span>
|
| 2899 |
|
|
<a name="l02936"></a>02936 <span class="keyword">// else X not affected</span>
|
| 2900 |
|
|
<a name="l02937"></a>02937
|
| 2901 |
|
|
<a name="l02938"></a>02938 <span class="keyword">// V cleared</span>
|
| 2902 |
|
|
<a name="l02939"></a>02939 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 2903 |
|
|
<a name="l02940"></a>02940 <span class="keyword">// C for ROXL,ROXR: set to X</span>
|
| 2904 |
|
|
<a name="l02941"></a>02941 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>) ) <span class="vhdlkeyword">begin</span>
|
| 2905 |
|
|
<a name="l02942"></a>02942 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
| 2906 |
|
|
<a name="l02943"></a>02943 <span class="vhdlkeyword">end</span>
|
| 2907 |
|
|
<a name="l02944"></a>02944 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 2908 |
|
|
<a name="l02945"></a>02945 <span class="keyword">// C cleared</span>
|
| 2909 |
|
|
<a name="l02946"></a>02946 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 2910 |
|
|
<a name="l02947"></a>02947 <span class="vhdlkeyword">end</span>
|
| 2911 |
|
|
<a name="l02948"></a>02948
|
| 2912 |
|
|
<a name="l02949"></a>02949 <span class="keyword">// N set</span>
|
| 2913 |
|
|
<a name="l02950"></a>02950 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 2914 |
|
|
<a name="l02951"></a>02951 <span class="keyword">// Z set</span>
|
| 2915 |
|
|
<a name="l02952"></a>02952 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 2916 |
|
|
<a name="l02953"></a>02953 <span class="vhdlkeyword">end</span>
|
| 2917 |
|
|
<a name="l02954"></a>02954
|
| 2918 |
|
|
<a name="l02955"></a>02955 <a class="code" href="ao68000_8v.html#ac946f278d039868214c441c11fcf2587">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 2919 |
|
|
<a name="l02956"></a>02956
|
| 2920 |
|
|
<a name="l02957"></a>02957 <span class="keyword">// ASL</span>
|
| 2921 |
|
|
<a name="l02958"></a>02958 <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 2922 |
|
|
<a name="l02959"></a>02959 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
| 2923 |
|
|
<a name="l02960"></a>02960
|
| 2924 |
|
|
<a name="l02961"></a>02961 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b0</span>)? (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> != <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) : <span class="vhdllogic">1'b1</span>; <span class="keyword">// V</span>
|
| 2925 |
|
|
<a name="l02962"></a>02962 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 2926 |
|
|
<a name="l02963"></a>02963 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
| 2927 |
|
|
<a name="l02964"></a>02964 <span class="vhdlkeyword">end</span>
|
| 2928 |
|
|
<a name="l02965"></a>02965 <span class="keyword">// LSL</span>
|
| 2929 |
|
|
<a name="l02966"></a>02966 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 2930 |
|
|
<a name="l02967"></a>02967 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
| 2931 |
|
|
<a name="l02968"></a>02968
|
| 2932 |
|
|
<a name="l02969"></a>02969 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 2933 |
|
|
<a name="l02970"></a>02970 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 2934 |
|
|
<a name="l02971"></a>02971 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
| 2935 |
|
|
<a name="l02972"></a>02972 <span class="vhdlkeyword">end</span>
|
| 2936 |
|
|
<a name="l02973"></a>02973 <span class="keyword">// ROL</span>
|
| 2937 |
|
|
<a name="l02974"></a>02974 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 2938 |
|
|
<a name="l02975"></a>02975 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>};
|
| 2939 |
|
|
<a name="l02976"></a>02976
|
| 2940 |
|
|
<a name="l02977"></a>02977 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 2941 |
|
|
<a name="l02978"></a>02978 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 2942 |
|
|
<a name="l02979"></a>02979 <span class="keyword">// X not affected</span>
|
| 2943 |
13 |
alfik |
<a name="l02980"></a>02980 <span class="vhdlkeyword">end</span>
|
| 2944 |
14 |
alfik |
<a name="l02981"></a>02981 <span class="keyword">// ROXL</span>
|
| 2945 |
|
|
<a name="l02982"></a>02982 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 2946 |
|
|
<a name="l02983"></a>02983 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 2947 |
|
|
<a name="l02984"></a>02984
|
| 2948 |
|
|
<a name="l02985"></a>02985 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 2949 |
|
|
<a name="l02986"></a>02986 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 2950 |
|
|
<a name="l02987"></a>02987 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
| 2951 |
|
|
<a name="l02988"></a>02988 <span class="vhdlkeyword">end</span>
|
| 2952 |
|
|
<a name="l02989"></a>02989 <span class="keyword">// ASR</span>
|
| 2953 |
|
|
<a name="l02990"></a>02990 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 2954 |
|
|
<a name="l02991"></a>02991 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
| 2955 |
|
|
<a name="l02992"></a>02992 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
| 2956 |
|
|
<a name="l02993"></a>02993 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
| 2957 |
|
|
<a name="l02994"></a>02994
|
| 2958 |
|
|
<a name="l02995"></a>02995 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 2959 |
|
|
<a name="l02996"></a>02996 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 2960 |
|
|
<a name="l02997"></a>02997 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
| 2961 |
|
|
<a name="l02998"></a>02998 <span class="vhdlkeyword">end</span>
|
| 2962 |
|
|
<a name="l02999"></a>02999 <span class="keyword">// LSR</span>
|
| 2963 |
|
|
<a name="l03000"></a>03000 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 2964 |
|
|
<a name="l03001"></a>03001 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
| 2965 |
|
|
<a name="l03002"></a>03002 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
| 2966 |
|
|
<a name="l03003"></a>03003 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
| 2967 |
|
|
<a name="l03004"></a>03004
|
| 2968 |
|
|
<a name="l03005"></a>03005 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 2969 |
|
|
<a name="l03006"></a>03006 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 2970 |
|
|
<a name="l03007"></a>03007 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
| 2971 |
|
|
<a name="l03008"></a>03008 <span class="vhdlkeyword">end</span>
|
| 2972 |
|
|
<a name="l03009"></a>03009 <span class="keyword">// ROR</span>
|
| 2973 |
|
|
<a name="l03010"></a>03010 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 2974 |
|
|
<a name="l03011"></a>03011 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
| 2975 |
|
|
<a name="l03012"></a>03012 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
| 2976 |
|
|
<a name="l03013"></a>03013 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
| 2977 |
|
|
<a name="l03014"></a>03014
|
| 2978 |
|
|
<a name="l03015"></a>03015 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 2979 |
|
|
<a name="l03016"></a>03016 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 2980 |
|
|
<a name="l03017"></a>03017 <span class="keyword">// X not affected</span>
|
| 2981 |
|
|
<a name="l03018"></a>03018 <span class="vhdlkeyword">end</span>
|
| 2982 |
|
|
<a name="l03019"></a>03019 <span class="keyword">// ROXR</span>
|
| 2983 |
|
|
<a name="l03020"></a>03020 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 2984 |
|
|
<a name="l03021"></a>03021 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>]};
|
| 2985 |
|
|
<a name="l03022"></a>03022 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>]};
|
| 2986 |
|
|
<a name="l03023"></a>03023 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
| 2987 |
|
|
<a name="l03024"></a>03024
|
| 2988 |
|
|
<a name="l03025"></a>03025 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 2989 |
|
|
<a name="l03026"></a>03026 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 2990 |
|
|
<a name="l03027"></a>03027 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
| 2991 |
|
|
<a name="l03028"></a>03028 <span class="vhdlkeyword">end</span>
|
| 2992 |
|
|
<a name="l03029"></a>03029
|
| 2993 |
|
|
<a name="l03030"></a>03030 <span class="keyword">// N set</span>
|
| 2994 |
|
|
<a name="l03031"></a>03031 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 2995 |
|
|
<a name="l03032"></a>03032 <span class="keyword">// Z set</span>
|
| 2996 |
|
|
<a name="l03033"></a>03033 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 2997 |
|
|
<a name="l03034"></a>03034 <span class="vhdlkeyword">end</span>
|
| 2998 |
|
|
<a name="l03035"></a>03035
|
| 2999 |
|
|
<a name="l03036"></a>03036 <a class="code" href="ao68000_8v.html#a268aa82704bd8f1c1548dfc69a12a951">`ALU_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3000 |
|
|
<a name="l03037"></a>03037 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 3001 |
|
|
<a name="l03038"></a>03038
|
| 3002 |
|
|
<a name="l03039"></a>03039 <span class="keyword">// X not affected</span>
|
| 3003 |
|
|
<a name="l03040"></a>03040 <span class="keyword">// C cleared</span>
|
| 3004 |
|
|
<a name="l03041"></a>03041 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3005 |
|
|
<a name="l03042"></a>03042 <span class="keyword">// V cleared</span>
|
| 3006 |
|
|
<a name="l03043"></a>03043 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3007 |
13 |
alfik |
<a name="l03044"></a>03044
|
| 3008 |
14 |
alfik |
<a name="l03045"></a>03045 <span class="keyword">// N set</span>
|
| 3009 |
|
|
<a name="l03046"></a>03046 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3010 |
|
|
<a name="l03047"></a>03047 <span class="keyword">// Z set</span>
|
| 3011 |
|
|
<a name="l03048"></a>03048 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 3012 |
|
|
<a name="l03049"></a>03049 <span class="vhdlkeyword">end</span>
|
| 3013 |
|
|
<a name="l03050"></a>03050
|
| 3014 |
|
|
<a name="l03051"></a>03051 <a class="code" href="ao68000_8v.html#a30a87601d2ca38286bb0d486d59f6a07">`ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3015 |
|
|
<a name="l03052"></a>03052 <span class="keyword">// ADDA: 1101</span>
|
| 3016 |
|
|
<a name="l03053"></a>03053 <span class="keyword">// CMPA: 1011</span>
|
| 3017 |
|
|
<a name="l03054"></a>03054 <span class="keyword">// SUBA: 1001</span>
|
| 3018 |
|
|
<a name="l03055"></a>03055 <span class="keyword">// ADDQ,SUBQ: 0101 xxx0,1</span>
|
| 3019 |
|
|
<a name="l03056"></a>03056 <span class="keyword">// operation requires that operand2 was sign extended</span>
|
| 3020 |
|
|
<a name="l03057"></a>03057
|
| 3021 |
|
|
<a name="l03058"></a>03058 <span class="keyword">// ADDA,ADDQ</span>
|
| 3022 |
|
|
<a name="l03059"></a>03059 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) )
|
| 3023 |
|
|
<a name="l03060"></a>03060 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 3024 |
|
|
<a name="l03061"></a>03061 <span class="keyword">// SUBA,CMPA,SUBQ</span>
|
| 3025 |
|
|
<a name="l03062"></a>03062 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) )
|
| 3026 |
|
|
<a name="l03063"></a>03063 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 3027 |
|
|
<a name="l03064"></a>03064
|
| 3028 |
|
|
<a name="l03065"></a>03065 <span class="keyword">// for CMPA</span>
|
| 3029 |
|
|
<a name="l03066"></a>03066 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> ) <span class="vhdlkeyword">begin</span>
|
| 3030 |
|
|
<a name="l03067"></a>03067 <span class="keyword">// Z</span>
|
| 3031 |
|
|
<a name="l03068"></a>03068 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 3032 |
|
|
<a name="l03069"></a>03069 <span class="keyword">// N</span>
|
| 3033 |
|
|
<a name="l03070"></a>03070 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3034 |
|
|
<a name="l03071"></a>03071
|
| 3035 |
|
|
<a name="l03072"></a>03072 <span class="keyword">// C,V</span>
|
| 3036 |
|
|
<a name="l03073"></a>03073 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 3037 |
|
|
<a name="l03074"></a>03074 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 3038 |
|
|
<a name="l03075"></a>03075 <span class="keyword">// X not affected</span>
|
| 3039 |
|
|
<a name="l03076"></a>03076 <span class="vhdlkeyword">end</span>
|
| 3040 |
|
|
<a name="l03077"></a>03077 <span class="keyword">// for ADDA,SUBA,ADDQ,SUBQ: ccr not affected</span>
|
| 3041 |
|
|
<a name="l03078"></a>03078 <span class="vhdlkeyword">end</span>
|
| 3042 |
|
|
<a name="l03079"></a>03079
|
| 3043 |
|
|
<a name="l03080"></a>03080 <a class="code" href="ao68000_8v.html#af0a4db089a5eb288abf9453ca2d79c26">`ALU_CHK</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3044 |
|
|
<a name="l03081"></a>03081 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 3045 |
|
|
<a name="l03082"></a>03082
|
| 3046 |
|
|
<a name="l03083"></a>03083 <span class="keyword">// undocumented behavior: Z flag, see 68knotes.txt</span>
|
| 3047 |
|
|
<a name="l03084"></a>03084 <span class="keyword">//sr[2] <= (operand1[15:0] == 16'b0) ? 1'b1 : 1'b0;</span>
|
| 3048 |
|
|
<a name="l03085"></a>03085 <span class="keyword">// undocumented behavior: C,V flags, see 68knotes.txt</span>
|
| 3049 |
|
|
<a name="l03086"></a>03086 <span class="keyword">//sr[0] <= 1'b0;</span>
|
| 3050 |
|
|
<a name="l03087"></a>03087 <span class="keyword">//sr[1] <= 1'b0;</span>
|
| 3051 |
|
|
<a name="l03088"></a>03088
|
| 3052 |
|
|
<a name="l03089"></a>03089 <span class="keyword">// C,X,V</span>
|
| 3053 |
|
|
<a name="l03090"></a>03090 <span class="keyword">// sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);</span>
|
| 3054 |
|
|
<a name="l03091"></a>03091 <span class="keyword">// sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];</span>
|
| 3055 |
|
|
<a name="l03092"></a>03092 <span class="keyword">// sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);</span>
|
| 3056 |
|
|
<a name="l03093"></a>03093 <span class="keyword">// +: 0-1, 0-0=0, 1-1=0</span>
|
| 3057 |
|
|
<a name="l03094"></a>03094 <span class="keyword">// -: 0-0=1, 1-0, 1-1=1</span>
|
| 3058 |
|
|
<a name="l03095"></a>03095 <span class="keyword">// operand1 - operand2 > 0</span>
|
| 3059 |
|
|
<a name="l03096"></a>03096 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] && ((~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>)) == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
| 3060 |
|
|
<a name="l03097"></a>03097 <span class="keyword">// clear N</span>
|
| 3061 |
|
|
<a name="l03098"></a>03098 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3062 |
|
|
<a name="l03099"></a>03099 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 3063 |
|
|
<a name="l03100"></a>03100 <span class="vhdlkeyword">end</span>
|
| 3064 |
|
|
<a name="l03101"></a>03101 <span class="keyword">// operand1 < 0</span>
|
| 3065 |
|
|
<a name="l03102"></a>03102 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
| 3066 |
|
|
<a name="l03103"></a>03103 <span class="keyword">// set N</span>
|
| 3067 |
|
|
<a name="l03104"></a>03104 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 3068 |
|
|
<a name="l03105"></a>03105 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 3069 |
|
|
<a name="l03106"></a>03106 <span class="vhdlkeyword">end</span>
|
| 3070 |
|
|
<a name="l03107"></a>03107 <span class="keyword">// no trap</span>
|
| 3071 |
|
|
<a name="l03108"></a>03108 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 3072 |
|
|
<a name="l03109"></a>03109 <span class="keyword">// N undefined: not affected</span>
|
| 3073 |
|
|
<a name="l03110"></a>03110 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 3074 |
|
|
<a name="l03111"></a>03111 <span class="vhdlkeyword">end</span>
|
| 3075 |
|
|
<a name="l03112"></a>03112
|
| 3076 |
|
|
<a name="l03113"></a>03113 <span class="keyword">// X not affected</span>
|
| 3077 |
|
|
<a name="l03114"></a>03114 <span class="vhdlkeyword">end</span>
|
| 3078 |
|
|
<a name="l03115"></a>03115
|
| 3079 |
|
|
<a name="l03116"></a>03116 <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3080 |
|
|
<a name="l03117"></a>03117
|
| 3081 |
|
|
<a name="l03118"></a>03118 <span class="keyword">// division by 0</span>
|
| 3082 |
|
|
<a name="l03119"></a>03119 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 3083 |
|
|
<a name="l03120"></a>03120 <span class="keyword">// X not affected</span>
|
| 3084 |
|
|
<a name="l03121"></a>03121 <span class="keyword">// C cleared</span>
|
| 3085 |
|
|
<a name="l03122"></a>03122 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3086 |
|
|
<a name="l03123"></a>03123 <span class="keyword">// V,Z,N undefined: cleared</span>
|
| 3087 |
|
|
<a name="l03124"></a>03124 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3088 |
|
|
<a name="l03125"></a>03125 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3089 |
|
|
<a name="l03126"></a>03126 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3090 |
|
|
<a name="l03127"></a>03127
|
| 3091 |
|
|
<a name="l03128"></a>03128 <span class="keyword">// set trap</span>
|
| 3092 |
|
|
<a name="l03129"></a>03129 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 3093 |
|
|
<a name="l03130"></a>03130 <span class="vhdlkeyword">end</span>
|
| 3094 |
|
|
<a name="l03131"></a>03131 <span class="keyword">// division in idle state</span>
|
| 3095 |
|
|
<a name="l03132"></a>03132 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 3096 |
|
|
<a name="l03133"></a>03133 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 3097 |
|
|
<a name="l03134"></a>03134 <span class="vhdlkeyword">end</span>
|
| 3098 |
|
|
<a name="l03135"></a>03135 <span class="keyword">// division overflow: divu, divs</span>
|
| 3099 |
|
|
<a name="l03136"></a>03136 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 3100 |
|
|
<a name="l03137"></a>03137 <span class="keyword">// X not affected</span>
|
| 3101 |
|
|
<a name="l03138"></a>03138 <span class="keyword">// C cleared</span>
|
| 3102 |
|
|
<a name="l03139"></a>03139 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3103 |
|
|
<a name="l03140"></a>03140 <span class="keyword">// V set</span>
|
| 3104 |
|
|
<a name="l03141"></a>03141 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 3105 |
|
|
<a name="l03142"></a>03142 <span class="keyword">// Z,N undefined: cleared and set</span>
|
| 3106 |
|
|
<a name="l03143"></a>03143 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3107 |
|
|
<a name="l03144"></a>03144 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 3108 |
13 |
alfik |
<a name="l03145"></a>03145
|
| 3109 |
14 |
alfik |
<a name="l03146"></a>03146 <span class="keyword">// set trap</span>
|
| 3110 |
|
|
<a name="l03147"></a>03147 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 3111 |
|
|
<a name="l03148"></a>03148 <span class="vhdlkeyword">end</span>
|
| 3112 |
|
|
<a name="l03149"></a>03149 <span class="keyword">// division</span>
|
| 3113 |
|
|
<a name="l03150"></a>03150 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> ) <span class="vhdlkeyword">begin</span>
|
| 3114 |
|
|
<a name="l03151"></a>03151 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= {<a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a>, <a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>};
|
| 3115 |
|
|
<a name="l03152"></a>03152
|
| 3116 |
|
|
<a name="l03153"></a>03153 <span class="keyword">// X not affected</span>
|
| 3117 |
|
|
<a name="l03154"></a>03154 <span class="keyword">// C cleared</span>
|
| 3118 |
|
|
<a name="l03155"></a>03155 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3119 |
|
|
<a name="l03156"></a>03156 <span class="keyword">// V cleared</span>
|
| 3120 |
|
|
<a name="l03157"></a>03157 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3121 |
|
|
<a name="l03158"></a>03158 <span class="keyword">// Z</span>
|
| 3122 |
|
|
<a name="l03159"></a>03159 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> == <span class="vhdllogic">16'b0</span>);
|
| 3123 |
|
|
<a name="l03160"></a>03160 <span class="keyword">// N</span>
|
| 3124 |
|
|
<a name="l03161"></a>03161 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>);
|
| 3125 |
|
|
<a name="l03162"></a>03162
|
| 3126 |
|
|
<a name="l03163"></a>03163 <span class="keyword">// set trap</span>
|
| 3127 |
|
|
<a name="l03164"></a>03164 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 3128 |
|
|
<a name="l03165"></a>03165 <span class="vhdlkeyword">end</span>
|
| 3129 |
|
|
<a name="l03166"></a>03166 <span class="keyword">// multiplication</span>
|
| 3130 |
|
|
<a name="l03167"></a>03167 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> ) <span class="vhdlkeyword">begin</span>
|
| 3131 |
|
|
<a name="l03168"></a>03168 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 3132 |
|
|
<a name="l03169"></a>03169
|
| 3133 |
|
|
<a name="l03170"></a>03170 <span class="keyword">// X not affected</span>
|
| 3134 |
|
|
<a name="l03171"></a>03171 <span class="keyword">// C cleared</span>
|
| 3135 |
|
|
<a name="l03172"></a>03172 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3136 |
|
|
<a name="l03173"></a>03173 <span class="keyword">// V cleared</span>
|
| 3137 |
|
|
<a name="l03174"></a>03174 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3138 |
|
|
<a name="l03175"></a>03175 <span class="keyword">// Z</span>
|
| 3139 |
|
|
<a name="l03176"></a>03176 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>);
|
| 3140 |
|
|
<a name="l03177"></a>03177 <span class="keyword">// N</span>
|
| 3141 |
|
|
<a name="l03178"></a>03178 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>);
|
| 3142 |
|
|
<a name="l03179"></a>03179
|
| 3143 |
|
|
<a name="l03180"></a>03180 <span class="keyword">// set trap</span>
|
| 3144 |
|
|
<a name="l03181"></a>03181 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 3145 |
|
|
<a name="l03182"></a>03182 <span class="vhdlkeyword">end</span>
|
| 3146 |
|
|
<a name="l03183"></a>03183 <span class="vhdlkeyword">end</span>
|
| 3147 |
|
|
<a name="l03184"></a>03184
|
| 3148 |
|
|
<a name="l03185"></a>03185
|
| 3149 |
|
|
<a name="l03186"></a>03186 <a class="code" href="ao68000_8v.html#a14b85ce3e5b4ede3b2c4e89f420c8c3c">`ALU_BCHG_BCLR_BSET_BTST</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 97 LE</span>
|
| 3150 |
|
|
<a name="l03187"></a>03187 <span class="keyword">// byte</span>
|
| 3151 |
|
|
<a name="l03188"></a>03188 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 3152 |
|
|
<a name="l03189"></a>03189 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]);
|
| 3153 |
|
|
<a name="l03190"></a>03190 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 3154 |
|
|
<a name="l03191"></a>03191 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 3155 |
|
|
<a name="l03192"></a>03192 <span class="vhdlkeyword">end</span>
|
| 3156 |
|
|
<a name="l03193"></a>03193 <span class="keyword">// long</span>
|
| 3157 |
|
|
<a name="l03194"></a>03194 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 3158 |
|
|
<a name="l03195"></a>03195 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]);
|
| 3159 |
|
|
<a name="l03196"></a>03196 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 3160 |
|
|
<a name="l03197"></a>03197 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 3161 |
|
|
<a name="l03198"></a>03198 <span class="vhdlkeyword">end</span>
|
| 3162 |
|
|
<a name="l03199"></a>03199
|
| 3163 |
|
|
<a name="l03200"></a>03200 <span class="keyword">// C,V,N,X not affected</span>
|
| 3164 |
|
|
<a name="l03201"></a>03201 <span class="vhdlkeyword">end</span>
|
| 3165 |
|
|
<a name="l03202"></a>03202
|
| 3166 |
|
|
<a name="l03203"></a>03203 <a class="code" href="ao68000_8v.html#ac7de3ab6c8eec4381bde5e4f61b45761">`ALU_TAS</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3167 |
|
|
<a name="l03204"></a>03204 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= { <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">6</span>:<span class="vhdllogic">0</span>] };
|
| 3168 |
|
|
<a name="l03205"></a>03205
|
| 3169 |
|
|
<a name="l03206"></a>03206 <span class="keyword">// X not affected</span>
|
| 3170 |
|
|
<a name="l03207"></a>03207 <span class="keyword">// C cleared</span>
|
| 3171 |
|
|
<a name="l03208"></a>03208 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3172 |
|
|
<a name="l03209"></a>03209 <span class="keyword">// V cleared</span>
|
| 3173 |
|
|
<a name="l03210"></a>03210 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3174 |
|
|
<a name="l03211"></a>03211
|
| 3175 |
|
|
<a name="l03212"></a>03212 <span class="keyword">// N set</span>
|
| 3176 |
|
|
<a name="l03213"></a>03213 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>);
|
| 3177 |
|
|
<a name="l03214"></a>03214 <span class="keyword">// Z set</span>
|
| 3178 |
|
|
<a name="l03215"></a>03215 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>);
|
| 3179 |
|
|
<a name="l03216"></a>03216 <span class="vhdlkeyword">end</span>
|
| 3180 |
|
|
<a name="l03217"></a>03217
|
| 3181 |
|
|
<a name="l03218"></a>03218
|
| 3182 |
|
|
<a name="l03219"></a>03219 <a class="code" href="ao68000_8v.html#a07c7e53af3f4995a167966ba18c2728f">`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3183 |
|
|
<a name="l03220"></a>03220 <span class="keyword">// NEGX / CLR / NEG / NOT</span>
|
| 3184 |
|
|
<a name="l03221"></a>03221 <span class="vhdlkeyword">if</span> ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span>))
|
| 3185 |
|
|
<a name="l03222"></a>03222 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <span class="vhdllogic">32'b0</span> - (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & {<span class="vhdllogic">32</span>{<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] | ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]}}) - ((<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]) | (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]));
|
| 3186 |
|
|
<a name="l03223"></a>03223 <span class="keyword">// NBCD</span>
|
| 3187 |
|
|
<a name="l03224"></a>03224 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span> ) <span class="vhdlkeyword">begin</span>
|
| 3188 |
|
|
<a name="l03225"></a>03225
|
| 3189 |
|
|
<a name="l03226"></a>03226 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>];
|
| 3190 |
|
|
<a name="l03227"></a>03227 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">4'd9</span>) ? (<span class="vhdllogic">5'd24</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]) : (<span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]);
|
| 3191 |
|
|
<a name="l03228"></a>03228
|
| 3192 |
|
|
<a name="l03229"></a>03229 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd9</span>) <span class="vhdlkeyword">begin</span>
|
| 3193 |
|
|
<a name="l03230"></a>03230 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
| 3194 |
|
|
<a name="l03231"></a>03231 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <span class="vhdllogic">4'd0</span>;
|
| 3195 |
|
|
<a name="l03232"></a>03232 <span class="vhdlkeyword">end</span>
|
| 3196 |
|
|
<a name="l03233"></a>03233 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> || <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd15</span>)) <span class="vhdlkeyword">begin</span>
|
| 3197 |
|
|
<a name="l03234"></a>03234 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
| 3198 |
|
|
<a name="l03235"></a>03235 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] + <span class="vhdllogic">4'd1</span>;
|
| 3199 |
|
|
<a name="l03236"></a>03236 <span class="vhdlkeyword">end</span>
|
| 3200 |
|
|
<a name="l03237"></a>03237 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 3201 |
|
|
<a name="l03238"></a>03238 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] + <span class="vhdllogic">4'd1</span>;
|
| 3202 |
|
|
<a name="l03239"></a>03239 <span class="vhdlkeyword">end</span>
|
| 3203 |
|
|
<a name="l03240"></a>03240
|
| 3204 |
|
|
<a name="l03241"></a>03241 <span class="keyword">//V undefined: unchanged</span>
|
| 3205 |
|
|
<a name="l03242"></a>03242 <span class="keyword">//Z</span>
|
| 3206 |
|
|
<a name="l03243"></a>03243 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 3207 |
|
|
<a name="l03244"></a>03244 <span class="keyword">//C,X</span>
|
| 3208 |
|
|
<a name="l03245"></a>03245 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 3209 |
|
|
<a name="l03246"></a>03246 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>; <span class="keyword">//=C</span>
|
| 3210 |
|
|
<a name="l03247"></a>03247 <span class="vhdlkeyword">end</span>
|
| 3211 |
|
|
<a name="l03248"></a>03248 <span class="keyword">// SWAP</span>
|
| 3212 |
|
|
<a name="l03249"></a>03249 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 3213 |
|
|
<a name="l03250"></a>03250 <span class="keyword">// EXT byte to word</span>
|
| 3214 |
|
|
<a name="l03251"></a>03251 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_10</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>], {<span class="vhdllogic">8</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 3215 |
|
|
<a name="l03252"></a>03252 <span class="keyword">// EXT word to long</span>
|
| 3216 |
|
|
<a name="l03253"></a>03253 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_11</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 3217 |
|
|
<a name="l03254"></a>03254
|
| 3218 |
|
|
<a name="l03255"></a>03255 <span class="keyword">// N set if negative else clear</span>
|
| 3219 |
|
|
<a name="l03256"></a>03256 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3220 |
13 |
alfik |
<a name="l03257"></a>03257
|
| 3221 |
14 |
alfik |
<a name="l03258"></a>03258 <span class="keyword">// CLR,NOT,SWAP,EXT</span>
|
| 3222 |
|
|
<a name="l03259"></a>03259 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> ) <span class="vhdlkeyword">begin</span>
|
| 3223 |
|
|
<a name="l03260"></a>03260 <span class="keyword">// X not affected</span>
|
| 3224 |
|
|
<a name="l03261"></a>03261 <span class="keyword">// C,V cleared</span>
|
| 3225 |
|
|
<a name="l03262"></a>03262 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3226 |
|
|
<a name="l03263"></a>03263 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 3227 |
|
|
<a name="l03264"></a>03264 <span class="keyword">// Z set</span>
|
| 3228 |
|
|
<a name="l03265"></a>03265 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 3229 |
|
|
<a name="l03266"></a>03266 <span class="vhdlkeyword">end</span>
|
| 3230 |
|
|
<a name="l03267"></a>03267 <span class="keyword">// NEGX</span>
|
| 3231 |
|
|
<a name="l03268"></a>03268 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> ) <span class="vhdlkeyword">begin</span>
|
| 3232 |
|
|
<a name="l03269"></a>03269 <span class="keyword">// C set if borrow</span>
|
| 3233 |
|
|
<a name="l03270"></a>03270 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3234 |
|
|
<a name="l03271"></a>03271 <span class="keyword">// X=C</span>
|
| 3235 |
|
|
<a name="l03272"></a>03272 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3236 |
|
|
<a name="l03273"></a>03273 <span class="keyword">// V set if overflow</span>
|
| 3237 |
|
|
<a name="l03274"></a>03274 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3238 |
|
|
<a name="l03275"></a>03275 <span class="keyword">// Z cleared if nonzero else unchanged</span>
|
| 3239 |
|
|
<a name="l03276"></a>03276 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 3240 |
13 |
alfik |
<a name="l03277"></a>03277 <span class="vhdlkeyword">end</span>
|
| 3241 |
14 |
alfik |
<a name="l03278"></a>03278 <span class="keyword">// NEG</span>
|
| 3242 |
|
|
<a name="l03279"></a>03279 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> ) <span class="vhdlkeyword">begin</span>
|
| 3243 |
|
|
<a name="l03280"></a>03280 <span class="keyword">// C clear if zero else set</span>
|
| 3244 |
|
|
<a name="l03281"></a>03281 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3245 |
|
|
<a name="l03282"></a>03282 <span class="keyword">// X=C</span>
|
| 3246 |
|
|
<a name="l03283"></a>03283 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3247 |
|
|
<a name="l03284"></a>03284 <span class="keyword">// V set if overflow</span>
|
| 3248 |
|
|
<a name="l03285"></a>03285 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 3249 |
|
|
<a name="l03286"></a>03286 <span class="keyword">// Z set if zero else clear</span>
|
| 3250 |
|
|
<a name="l03287"></a>03287 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 3251 |
|
|
<a name="l03288"></a>03288 <span class="vhdlkeyword">end</span>
|
| 3252 |
|
|
<a name="l03289"></a>03289 <span class="vhdlkeyword">end</span>
|
| 3253 |
|
|
<a name="l03290"></a>03290
|
| 3254 |
13 |
alfik |
<a name="l03291"></a>03291
|
| 3255 |
14 |
alfik |
<a name="l03292"></a>03292 <a class="code" href="ao68000_8v.html#a32c0e163ff437b07e40593ab59e42fe3">`ALU_SIMPLE_LONG_ADD</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3256 |
|
|
<a name="l03293"></a>03293 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 3257 |
|
|
<a name="l03294"></a>03294
|
| 3258 |
|
|
<a name="l03295"></a>03295 <span class="keyword">// CCR not affected</span>
|
| 3259 |
|
|
<a name="l03296"></a>03296 <span class="vhdlkeyword">end</span>
|
| 3260 |
13 |
alfik |
<a name="l03297"></a>03297
|
| 3261 |
14 |
alfik |
<a name="l03298"></a>03298 <a class="code" href="ao68000_8v.html#aea6fee15f3d775b1a8d262490203c713">`ALU_SIMPLE_LONG_SUB</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3262 |
|
|
<a name="l03299"></a>03299 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 3263 |
|
|
<a name="l03300"></a>03300
|
| 3264 |
|
|
<a name="l03301"></a>03301 <span class="keyword">// CCR not affected</span>
|
| 3265 |
|
|
<a name="l03302"></a>03302 <span class="vhdlkeyword">end</span>
|
| 3266 |
|
|
<a name="l03303"></a>03303
|
| 3267 |
|
|
<a name="l03304"></a>03304 <a class="code" href="ao68000_8v.html#a5083d98f4b785fe7af85ba1114f678ff">`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3268 |
|
|
<a name="l03305"></a>03305
|
| 3269 |
|
|
<a name="l03306"></a>03306 <span class="keyword">// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR</span>
|
| 3270 |
|
|
<a name="l03307"></a>03307 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ||
|
| 3271 |
|
|
<a name="l03308"></a>03308 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_01_111100</span>
|
| 3272 |
|
|
<a name="l03309"></a>03309 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
| 3273 |
|
|
<a name="l03310"></a>03310 <span class="keyword">// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR</span>
|
| 3274 |
|
|
<a name="l03311"></a>03311 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0111</span> ||
|
| 3275 |
|
|
<a name="l03312"></a>03312 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_00_111100</span>
|
| 3276 |
|
|
<a name="l03313"></a>03313 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
| 3277 |
|
|
<a name="l03314"></a>03314 <span class="vhdlkeyword">end</span>
|
| 3278 |
|
|
<a name="l03315"></a>03315
|
| 3279 |
|
|
<a name="l03316"></a>03316 <a class="code" href="ao68000_8v.html#ab6d6f774c41848f9c33c7b393620be2d">`ALU_SIMPLE_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3280 |
|
|
<a name="l03317"></a>03317 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 3281 |
|
|
<a name="l03318"></a>03318
|
| 3282 |
|
|
<a name="l03319"></a>03319 <span class="keyword">// CCR not affected</span>
|
| 3283 |
|
|
<a name="l03320"></a>03320 <span class="vhdlkeyword">end</span>
|
| 3284 |
|
|
<a name="l03321"></a>03321
|
| 3285 |
|
|
<a name="l03322"></a>03322 <a class="code" href="ao68000_8v.html#ac439a8b79bd4b213f0f33172bd5e5a73">`ALU_LINK_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 3286 |
|
|
<a name="l03323"></a>03323 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">3'b111</span>) <span class="vhdlkeyword">begin</span>
|
| 3287 |
|
|
<a name="l03324"></a>03324 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a> - <span class="vhdllogic">32'd4</span>;
|
| 3288 |
|
|
<a name="l03325"></a>03325 <span class="vhdlkeyword">end</span>
|
| 3289 |
|
|
<a name="l03326"></a>03326 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 3290 |
|
|
<a name="l03327"></a>03327 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 3291 |
|
|
<a name="l03328"></a>03328 <span class="vhdlkeyword">end</span>
|
| 3292 |
|
|
<a name="l03329"></a>03329
|
| 3293 |
|
|
<a name="l03330"></a>03330 <span class="keyword">// CCR not affected</span>
|
| 3294 |
|
|
<a name="l03331"></a>03331 <span class="vhdlkeyword">end</span>
|
| 3295 |
|
|
<a name="l03332"></a>03332
|
| 3296 |
|
|
<a name="l03333"></a>03333 <span class="vhdlkeyword">endcase</span>
|
| 3297 |
|
|
<a name="l03334"></a>03334 <span class="vhdlkeyword">end</span>
|
| 3298 |
|
|
<a name="l03335"></a>03335 <span class="vhdlkeyword">end</span>
|
| 3299 |
|
|
<a name="l03336"></a>03336
|
| 3300 |
|
|
<a name="l03337"></a>03337 <span class="vhdlkeyword">endmodule</span>
|
| 3301 |
|
|
<a name="l03338"></a>03338
|
| 3302 |
|
|
<a name="l03339"></a>03339 <span class="keyword">/***********************************************************************************************************************</span>
|
| 3303 |
|
|
<a name="l03340"></a>03340 <span class="keyword"> Microcode branch</span>
|
| 3304 |
|
|
<a name="l03341"></a>03341 <span class="keyword"> ***********************************************************************************************************************/</span>
|
| 3305 |
|
|
<a name="l03342"></a>03342
|
| 3306 |
|
|
<a name="l03343"></a>03343
|
| 3307 |
|
|
<a name="l03352"></a><a class="code" href="classmicrocode__branch.html">03352</a> <span class="vhdlkeyword">module</span> <a class="code" href="classmicrocode__branch.html">microcode_branch</a>(
|
| 3308 |
|
|
<a name="l03353"></a><a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">03353</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a>,
|
| 3309 |
|
|
<a name="l03354"></a><a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">03354</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>,
|
| 3310 |
|
|
<a name="l03355"></a>03355
|
| 3311 |
|
|
<a name="l03356"></a><a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">03356</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">movem_loop</a>,
|
| 3312 |
|
|
<a name="l03357"></a><a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">03357</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">movem_reg</a>,
|
| 3313 |
|
|
<a name="l03358"></a><a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">03358</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">operand2</a>,
|
| 3314 |
|
|
<a name="l03359"></a><a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">03359</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">alu_signal</a>,
|
| 3315 |
|
|
<a name="l03360"></a><a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">03360</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">alu_mult_div_ready</a>,
|
| 3316 |
|
|
<a name="l03361"></a><a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">03361</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a>,
|
| 3317 |
|
|
<a name="l03362"></a><a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">03362</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">result</a>,
|
| 3318 |
|
|
<a name="l03363"></a><a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">03363</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">overflow</a>,
|
| 3319 |
|
|
<a name="l03364"></a><a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">03364</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">stop_flag</a>,
|
| 3320 |
|
|
<a name="l03365"></a><a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">03365</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>,
|
| 3321 |
|
|
<a name="l03366"></a><a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">03366</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a>,
|
| 3322 |
|
|
<a name="l03367"></a><a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">03367</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a>,
|
| 3323 |
|
|
<a name="l03368"></a><a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">03368</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">group_0_flag</a>,
|
| 3324 |
|
|
<a name="l03369"></a><a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">03369</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a>,
|
| 3325 |
|
|
<a name="l03370"></a>03370
|
| 3326 |
|
|
<a name="l03371"></a><a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">03371</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a>,
|
| 3327 |
|
|
<a name="l03372"></a><a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">03372</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a>,
|
| 3328 |
|
|
<a name="l03373"></a><a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">03373</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a>,
|
| 3329 |
|
|
<a name="l03374"></a><a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">03374</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a>,
|
| 3330 |
|
|
<a name="l03375"></a><a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">03375</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">decoder_micropc</a>,
|
| 3331 |
13 |
alfik |
<a name="l03376"></a>03376
|
| 3332 |
14 |
alfik |
<a name="l03377"></a><a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">03377</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">prefetch_ir_valid_32</a>,
|
| 3333 |
|
|
<a name="l03378"></a><a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">03378</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a>,
|
| 3334 |
|
|
<a name="l03379"></a><a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">03379</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">jmp_address_trap</a>,
|
| 3335 |
|
|
<a name="l03380"></a><a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">03380</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">jmp_bus_trap</a>,
|
| 3336 |
|
|
<a name="l03381"></a><a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">03381</a> <span class="vhdlkeyword">input</span> <a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">finished</a>,
|
| 3337 |
|
|
<a name="l03382"></a>03382
|
| 3338 |
|
|
<a name="l03383"></a><a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">03383</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a>,
|
| 3339 |
|
|
<a name="l03384"></a><a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">03384</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a>,
|
| 3340 |
|
|
<a name="l03385"></a><a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">03385</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a>
|
| 3341 |
|
|
<a name="l03386"></a>03386 );
|
| 3342 |
|
|
<a name="l03387"></a>03387
|
| 3343 |
|
|
<a name="l03388"></a><a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">03388</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> = <span class="vhdllogic">9'd0</span>;
|
| 3344 |
|
|
<a name="l03389"></a><a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">03389</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
| 3345 |
|
|
<a name="l03390"></a><a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">03390</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3346 |
|
|
<a name="l03391"></a><a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">03391</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
| 3347 |
|
|
<a name="l03392"></a>03392
|
| 3348 |
|
|
<a name="l03393"></a>03393 <span class="vhdlkeyword">assign</span> <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a> =
|
| 3349 |
|
|
<a name="l03394"></a>03394 (<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">9'd0</span> :
|
| 3350 |
|
|
<a name="l03395"></a>03395 (<a class="code" href="classmicrocode__branch.html#abc45eb66161b645c69d4b6ad6457ff31">jmp_address_trap</a> == <span class="vhdllogic">1'b1</span> || <a class="code" href="classmicrocode__branch.html#a9ba804e0f049ed633f01c611e248a587">jmp_bus_trap</a> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="ao68000_8v.html#ada4b6f4df06a5dcac3ec15d4c8f4d31e">`MICROPC_ADDRESS_BUS_TRAP</a><span class="vhdlchar"></span> :
|
| 3351 |
|
|
<a name="l03396"></a>03396 ( (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#abdfc603db0ea3694052298e85fb6efad">`BRANCH_movem_loop</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a42e8abed644ad88712e3f12b88119b93">movem_loop</a> == <span class="vhdllogic">5'b10000</span>) ||
|
| 3352 |
|
|
<a name="l03397"></a>03397 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#acc65cf5ec49ce78ecf98c956cd2de769">`BRANCH_movem_reg</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#abad84561ae17084ceb7d2a623b446a14">movem_reg</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">0</span>) ||
|
| 3353 |
|
|
<a name="l03398"></a>03398 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#aa0b5846a5e98be60da75608078377571">`BRANCH_operand2</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a44a7fbf19a4641fb5007ba59ea7867b2">operand2</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">6'b0</span>) ||
|
| 3354 |
|
|
<a name="l03399"></a>03399 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a3db021156e8171951f6b91c78bbb7e1f">`BRANCH_alu_signal</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae0d0b0c347c453aed25820eb4d5ede60">alu_signal</a> == <span class="vhdllogic">1'b0</span>) ||
|
| 3355 |
|
|
<a name="l03400"></a>03400 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a62fe8e5939da15f9f391886fe174183a">`BRANCH_alu_mult_div_ready</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a6965faa1f8f535384a68703714d67d41">alu_mult_div_ready</a> == <span class="vhdllogic">1'b1</span>) ||
|
| 3356 |
|
|
<a name="l03401"></a>03401 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af3158a11a9fc793d4aeead4195871507">`BRANCH_condition_0</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a> == <span class="vhdllogic">1'b0</span>) ||
|
| 3357 |
|
|
<a name="l03402"></a>03402 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a48d5a0127f3bc738b8503c0713b9fba9">`BRANCH_condition_1</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a812465227c1ce82d3a227a04a5cc9a89">condition</a> == <span class="vhdllogic">1'b1</span>) ||
|
| 3358 |
|
|
<a name="l03403"></a>03403 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a0cbdc7b4e718d5cc690b435995bb7708">`BRANCH_result</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a07ec962ad743b1c4988f5b0f6332f393">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'hFFFF</span>) ||
|
| 3359 |
|
|
<a name="l03404"></a>03404 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a3861f0d4bd11e996bda23577348e86f7">`BRANCH_V</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a8e3878b37a15cbe9f5ac25d9d0c50ff5">overflow</a> == <span class="vhdllogic">1'b0</span>) ||
|
| 3360 |
|
|
<a name="l03405"></a>03405 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a5fb736520363d5359408ed4af63c6125">`BRANCH_movep_16</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b0</span>) ||
|
| 3361 |
|
|
<a name="l03406"></a>03406 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a76527514b31cb7de3a0f1f3a9b4fa039">stop_flag</a> == <span class="vhdllogic">1'b1</span>) ||
|
| 3362 |
|
|
<a name="l03407"></a>03407 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a719e200160515b706ebab9fe1e18c8c7">`BRANCH_ir</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a66d21fc86ad1b8a3b3f72d78b9c96aef">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] != <span class="vhdllogic">8'b0</span>) ||
|
| 3363 |
|
|
<a name="l03408"></a>03408 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af396200d0e5941fe60e8d960f2e3aa91">`BRANCH_trace_flag_and_interrupt</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> != <span class="vhdllogic">3'b000</span>) ||
|
| 3364 |
|
|
<a name="l03409"></a>03409 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a63f967b1bbe9ad356e3ccbbb2924e03f">`BRANCH_group_0_flag</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a1520537038c18470f595c0d2858431f3">group_0_flag</a> == <span class="vhdllogic">1'b0</span>)
|
| 3365 |
|
|
<a name="l03410"></a>03410 ) ? <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + { <span class="vhdllogic">5'd0</span>, <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> } :
|
| 3366 |
|
|
<a name="l03411"></a>03411 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a> == <span class="vhdllogic">8'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a1493bf14db63cdb7d2ce8b2410b1c33b">decoder_micropc</a> :
|
| 3367 |
|
|
<a name="l03412"></a>03412 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#af396200d0e5941fe60e8d960f2e3aa91">`BRANCH_trace_flag_and_interrupt</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a909c52e94961a97edb894efc59ecae40">trace_flag</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> == <span class="vhdllogic">3'b000</span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
| 3368 |
|
|
<a name="l03413"></a>03413 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a7950509479648899370516cfa0221c43">`PROCEDURE_jump_to_main_loop</a><span class="vhdlchar"></span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
| 3369 |
|
|
<a name="l03414"></a>03414 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a5c7af3686fb890de6242f973de1ee549">`PROCEDURE_call_load_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> :
|
| 3370 |
|
|
<a name="l03415"></a>03415 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a698b04745cbbec22896235d5cfffac43">`PROCEDURE_call_perform_ea_read</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a> :
|
| 3371 |
|
|
<a name="l03416"></a>03416 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa98c954da2ac9f709907c8c593b1439e">`PROCEDURE_call_perform_ea_write</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a> :
|
| 3372 |
|
|
<a name="l03417"></a>03417 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a30022c5eb1821e27dd5c70d4affbc835">`PROCEDURE_call_save_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> :
|
| 3373 |
|
|
<a name="l03418"></a>03418
|
| 3374 |
|
|
<a name="l03419"></a>03419 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> :
|
| 3375 |
|
|
<a name="l03420"></a>03420 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> == <span class="vhdllogic">9'd0</span>) ? <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a> :
|
| 3376 |
|
|
<a name="l03421"></a>03421
|
| 3377 |
|
|
<a name="l03422"></a>03422 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a50af2007588b7a528b934ae7672b1214">`PROCEDURE_call_write</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a6f20353ec8aea573354892ebe79e4aec">perform_ea_write</a> :
|
| 3378 |
|
|
<a name="l03423"></a>03423
|
| 3379 |
|
|
<a name="l03424"></a>03424 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a2c67cc2747b67d04684855e14c2b9fbb">`PROCEDURE_call_trap</a><span class="vhdlchar"></span>) ? <a class="code" href="ao68000_8v.html#a80e45e303a1ebe180eeb15b47454e13f">`MICROPC_TRAP_ENTRY</a><span class="vhdlchar"></span> :
|
| 3380 |
|
|
<a name="l03425"></a>03425 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#af842761d13933777546d76bd997e7494">`PROCEDURE_return</a><span class="vhdlchar"></span>) ? <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> :
|
| 3381 |
|
|
<a name="l03426"></a>03426 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#ac74b95b43e6c95ed82036002767bc22c">`PROCEDURE_interrupt_mask</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a474cb146bed7bdde681694c3f06a1106">interrupt_mask</a> == <span class="vhdllogic">3'b000</span>) ? <a class="code" href="ao68000_8v.html#a1e7ad8f4b421f72f5bdea07bef35f864">`MICROPC_MAIN_LOOP</a><span class="vhdlchar"></span> :
|
| 3382 |
|
|
<a name="l03427"></a>03427 ( (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a26a2f20a92ff8ab6f13d6633f3c9475c">`PROCEDURE_wait_finished</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ab3eb1598fd8ff755ee7811485c4b9849">finished</a> == <span class="vhdllogic">1'b0</span>) ||
|
| 3383 |
|
|
<a name="l03428"></a>03428 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa072f73b12cd178a44f47980e1bb98cb">`PROCEDURE_wait_prefetch_valid</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b0</span>) ||
|
| 3384 |
|
|
<a name="l03429"></a>03429 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a0ef2adec86a42dd30d78e9d259d828fd">`PROCEDURE_wait_prefetch_valid_32</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#aef8500b16e788430917ee03f003d10a9">prefetch_ir_valid_32</a> == <span class="vhdllogic">1'b0</span>) ||
|
| 3385 |
|
|
<a name="l03430"></a>03430 (<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b0</span>)
|
| 3386 |
|
|
<a name="l03431"></a>03431 ) ? <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> :
|
| 3387 |
|
|
<a name="l03432"></a>03432 <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>
|
| 3388 |
|
|
<a name="l03433"></a>03433 ;
|
| 3389 |
|
|
<a name="l03434"></a>03434
|
| 3390 |
|
|
<a name="l03435"></a><a class="code" href="classmicrocode__branch.html#a5c48a82153e9796a3913029cde0cc182">03435</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 3391 |
|
|
<a name="l03436"></a>03436 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> <= <span class="vhdllogic">9'd0</span>;
|
| 3392 |
|
|
<a name="l03437"></a>03437 <span class="vhdlkeyword">else</span> <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> <= <a class="code" href="classmicrocode__branch.html#a53df336945e1387fada5822142621f2f">micro_pc</a>;
|
| 3393 |
|
|
<a name="l03438"></a>03438 <span class="vhdlkeyword">end</span>
|
| 3394 |
|
|
<a name="l03439"></a>03439
|
| 3395 |
|
|
<a name="l03440"></a><a class="code" href="classmicrocode__branch.html#a4e2c393980b78c66fbb22710e14a1cbb">03440</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmicrocode__branch.html#aa97186c6a6c8f8229219bceb1750b753">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 3396 |
|
|
<a name="l03441"></a>03441 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a446d61eb34eb480a38661d473bf25fd4">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 3397 |
|
|
<a name="l03442"></a>03442 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <span class="vhdllogic">9'd0</span>;
|
| 3398 |
|
|
<a name="l03443"></a>03443 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <span class="vhdllogic">9'd0</span>;
|
| 3399 |
|
|
<a name="l03444"></a>03444 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
| 3400 |
|
|
<a name="l03445"></a>03445 <span class="vhdlkeyword">end</span>
|
| 3401 |
|
|
<a name="l03446"></a>03446 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a79ce1f7b2aa4e141d52316a04977ee60">`BRANCH_stop_flag_wait_ir_decode</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#ae627b4cdc5e73300a5166eb7636468ea">prefetch_ir_valid</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classmicrocode__branch.html#a96f331edcf8cb8bb65f80139b5248456">decoder_trap</a> == <span class="vhdllogic">8'd0</span>)
|
| 3402 |
|
|
<a name="l03447"></a>03447 <span class="vhdlkeyword">begin</span>
|
| 3403 |
|
|
<a name="l03448"></a>03448 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + { <span class="vhdllogic">5'd0</span>, <a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> };
|
| 3404 |
|
|
<a name="l03449"></a>03449 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
| 3405 |
|
|
<a name="l03450"></a>03450 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3406 |
|
|
<a name="l03451"></a>03451 <span class="vhdlkeyword">end</span>
|
| 3407 |
|
|
<a name="l03452"></a>03452 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a93f2469a63fd895a2a06d93b58735d41">branch_control</a> == <a class="code" href="ao68000_8v.html#a1f24f0ad71fd4d2edd6ead5ef6c3056a">`BRANCH_procedure</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
| 3408 |
|
|
<a name="l03453"></a>03453 <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 3409 |
|
|
<a name="l03454"></a>03454 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#acd130168642a726f7de176682a42e3ad">perform_ea_read</a>;
|
| 3410 |
|
|
<a name="l03455"></a>03455 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
| 3411 |
|
|
<a name="l03456"></a>03456 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
| 3412 |
|
|
<a name="l03457"></a>03457 <span class="vhdlkeyword">end</span>
|
| 3413 |
|
|
<a name="l03458"></a>03458 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a403d3720f31ad5a5895778bee758fb55">`PROCEDURE_call_read</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> == <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 3414 |
|
|
<a name="l03459"></a>03459 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
| 3415 |
|
|
<a name="l03460"></a>03460 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
| 3416 |
|
|
<a name="l03461"></a>03461 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3417 |
|
|
<a name="l03462"></a>03462 <span class="vhdlkeyword">end</span>
|
| 3418 |
|
|
<a name="l03463"></a>03463 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a50af2007588b7a528b934ae7672b1214">`PROCEDURE_call_write</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 3419 |
|
|
<a name="l03464"></a>03464 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a>;
|
| 3420 |
|
|
<a name="l03465"></a>03465 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
| 3421 |
|
|
<a name="l03466"></a>03466 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3422 |
|
|
<a name="l03467"></a>03467 <span class="vhdlkeyword">end</span>
|
| 3423 |
|
|
<a name="l03468"></a>03468 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>((<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a5c7af3686fb890de6242f973de1ee549">`PROCEDURE_call_load_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a029e3e9219332863900f71a52816c7ac">load_ea</a> != <span class="vhdllogic">9'd0</span>) ||
|
| 3424 |
|
|
<a name="l03469"></a>03469 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a698b04745cbbec22896235d5cfffac43">`PROCEDURE_call_perform_ea_read</a><span class="vhdlchar"></span>) ||
|
| 3425 |
|
|
<a name="l03470"></a>03470 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#aa98c954da2ac9f709907c8c593b1439e">`PROCEDURE_call_perform_ea_write</a><span class="vhdlchar"></span>) ||
|
| 3426 |
|
|
<a name="l03471"></a>03471 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a30022c5eb1821e27dd5c70d4affbc835">`PROCEDURE_call_save_ea</a><span class="vhdlchar"></span> && <a class="code" href="classmicrocode__branch.html#a2bf9f1fb5125818e8eb47aa043e0a393">save_ea</a> != <span class="vhdllogic">9'd0</span>) ||
|
| 3427 |
|
|
<a name="l03472"></a>03472 (<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a2c67cc2747b67d04684855e14c2b9fbb">`PROCEDURE_call_trap</a><span class="vhdlchar"></span>) )
|
| 3428 |
|
|
<a name="l03473"></a>03473 <span class="vhdlkeyword">begin</span>
|
| 3429 |
|
|
<a name="l03474"></a>03474 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a> + <span class="vhdllogic">9'd1</span>;
|
| 3430 |
|
|
<a name="l03475"></a>03475 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
| 3431 |
|
|
<a name="l03476"></a>03476 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3432 |
|
|
<a name="l03477"></a>03477 <span class="vhdlkeyword">end</span>
|
| 3433 |
|
|
<a name="l03478"></a>03478 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#af842761d13933777546d76bd997e7494">`PROCEDURE_return</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
| 3434 |
|
|
<a name="l03479"></a>03479 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3435 |
|
|
<a name="l03480"></a>03480 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
| 3436 |
|
|
<a name="l03481"></a>03481 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
| 3437 |
|
|
<a name="l03482"></a>03482 <span class="vhdlkeyword">end</span>
|
| 3438 |
|
|
<a name="l03483"></a>03483 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#a318a0823db3c0aa8dfeae26f05495e5b">`PROCEDURE_push_micropc</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
| 3439 |
|
|
<a name="l03484"></a>03484 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#ad9bc2cb9966990b791c16ae418be756c">micro_pc_0</a>;
|
| 3440 |
|
|
<a name="l03485"></a>03485 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a>;
|
| 3441 |
|
|
<a name="l03486"></a>03486 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3442 |
|
|
<a name="l03487"></a>03487 <span class="vhdlkeyword">end</span>
|
| 3443 |
|
|
<a name="l03488"></a>03488 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmicrocode__branch.html#a4c922f8d1c3da7414164908004c6e60d">branch_offset</a> == <a class="code" href="ao68000_8v.html#acfe58e669e77374120e6e534fc621316">`PROCEDURE_pop_micropc</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
|
| 3444 |
|
|
<a name="l03489"></a>03489 <a class="code" href="classmicrocode__branch.html#a1759008367898c209d99232aaa1dfd6c">micro_pc_1</a> <= <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a>;
|
| 3445 |
|
|
<a name="l03490"></a>03490 <a class="code" href="classmicrocode__branch.html#a5f0609e6f83715642a34d65104c11e47">micro_pc_2</a> <= <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a>;
|
| 3446 |
|
|
<a name="l03491"></a>03491 <a class="code" href="classmicrocode__branch.html#a8d7713b0340f69c7eae6282373e3bf7b">micro_pc_3</a> <= <span class="vhdllogic">9'd0</span>;
|
| 3447 |
|
|
<a name="l03492"></a>03492 <span class="vhdlkeyword">end</span>
|
| 3448 |
|
|
<a name="l03493"></a>03493 <span class="vhdlkeyword">end</span>
|
| 3449 |
|
|
<a name="l03494"></a>03494 <span class="vhdlkeyword">end</span>
|
| 3450 |
|
|
<a name="l03495"></a>03495
|
| 3451 |
|
|
<a name="l03496"></a>03496 <span class="vhdlkeyword">endmodule</span>
|
| 3452 |
12 |
alfik |
</pre></div></div>
|
| 3453 |
|
|
</div>
|
| 3454 |
15 |
alfik |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 17:55:17 for ao68000 by 
|
| 3455 |
12 |
alfik |
<a href="http://www.doxygen.org/index.html">
|
| 3456 |
|
|
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
|
| 3457 |
|
|
</body>
|
| 3458 |
|
|
</html>
|
