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<title>ao68000: memory_registers Module Reference</title>
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<div class="header">
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  <div class="summary">
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<a href="#Inputs">Inputs</a> &#124;
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<a href="#Outputs">Outputs</a> &#124;
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<a href="#Signals">Signals</a> &#124;
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<a href="#Module Instances">Module Instances</a> &#124;
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<a href="#Always Constructs">Always Constructs</a>  </div>
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  <div class="headertitle">
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<h1>memory_registers Module Reference</h1>  </div>
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</div>
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<div class="contents">
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<!-- doxytag: class="memory_registers" -->
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<p>Contains the microcode ROM and D0-D7, A0-A7 registers.
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<a href="#_details">More...</a></p>
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<!-- startSectionHeader --><div class="dynheader">
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Inheritance diagram for memory_registers:<!-- endSectionHeader --></div>
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 <div class="center">
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  <img src="classmemory__registers.png" usemap="#memory_registers_map" alt=""/>
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 </div><!-- endSectionContent --></div>
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<p><a href="classmemory__registers-members.html">List of all members.</a></p>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
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Always Constructs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">ALWAYS_29</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
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Outputs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a2c906a8760a85b5370b8c7f56dc4e6f3">Dn_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Module Instances"></a>
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Module Instances</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram::an_ram_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram::dn_ram_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram::micro_rom_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
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Signals</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a> </td></tr>
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</table>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
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<p>Contains the microcode ROM and D0-D7, A0-A7 registers. </p>
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<p>The <a class="el" href="classmemory__registers.html" title="Contains the microcode ROM and D0-D7, A0-A7 registers.">memory_registers</a> module contains:</p>
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<ul>
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<li>data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.</li>
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<li>the microcode implemented as an on-chip ROM.</li>
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</ul>
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<p>Currently this module contains <em>altsyncram</em> instantiations from Altera Megafunction/LPM library. </p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02044">2044</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/><h2>Member Function Documentation</h2>
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<a class="anchor" id="a09281e3224878c570c81844785844fe0"></a><!-- doxytag: member="memory_registers::ALWAYS_29" ref="a09281e3224878c570c81844785844fe0" args="clock, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_29          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
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          <td class="paramkey"></td>
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          <td></td>
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          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02077">2077</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<div class="fragment"><pre class="fragment">
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<a name="l02077"></a>02077 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a>) <span class="vhdlkeyword">begin</span>
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<a name="l02078"></a>02078     <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                 <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> &lt;= <span class="vhdllogic">32&#39;d0</span>;
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<a name="l02079"></a>02079     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a> == <span class="vhdllogic">4&#39;b0111</span> &amp;&amp; <a class="code" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a>)   <a class="code" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a> &lt;= <a class="code" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a>;
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<a name="l02080"></a>02080 <span class="vhdlkeyword">end</span>
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</pre></div>
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</div>
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</div>
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<hr/><h2>Member Data Documentation</h2>
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<a class="anchor" id="a06690d046213efc68334643946af2b16"></a><!-- doxytag: member="memory_registers::clock" ref="a06690d046213efc68334643946af2b16" args="" -->
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<div class="memitem">
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a06690d046213efc68334643946af2b16">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02045">2045</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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<a class="anchor" id="a52bffc13966ddfc557c3c3a2cece1d97"></a><!-- doxytag: member="memory_registers::reset_n" ref="a52bffc13966ddfc557c3c3a2cece1d97" args="" -->
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<div class="memitem">
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<div class="memproto">
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a52bffc13966ddfc557c3c3a2cece1d97">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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        </tr>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02046">2046</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a8a67810353708d3652f619623692a545"></a><!-- doxytag: member="memory_registers::An_address" ref="a8a67810353708d3652f619623692a545" args="" -->
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<div class="memitem">
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a8a67810353708d3652f619623692a545">An_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02049">2049</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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<a class="anchor" id="a8e3deabb065d3e6aaaf647a83e7c84e9"></a><!-- doxytag: member="memory_registers::An_input" ref="a8e3deabb065d3e6aaaf647a83e7c84e9" args="" -->
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<div class="memitem">
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a8e3deabb065d3e6aaaf647a83e7c84e9">An_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02050">2050</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="af97dfc643a2fa9ae191cb68acb23ea91"></a><!-- doxytag: member="memory_registers::An_write_enable" ref="af97dfc643a2fa9ae191cb68acb23ea91" args="" -->
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<div class="memitem">
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#af97dfc643a2fa9ae191cb68acb23ea91">An_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02051">2051</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a806c8f12e4600aa02e87d61e072eb6e4"></a><!-- doxytag: member="memory_registers::An_output" ref="a806c8f12e4600aa02e87d61e072eb6e4" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a806c8f12e4600aa02e87d61e072eb6e4">An_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02052">2052</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a736b71ba5d8851ef8e883408751c9380"></a><!-- doxytag: member="memory_registers::usp" ref="a736b71ba5d8851ef8e883408751c9380" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a736b71ba5d8851ef8e883408751c9380">usp</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02054">2054</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a3faa61795c758b3d444c082be9ac5758"></a><!-- doxytag: member="memory_registers::Dn_address" ref="a3faa61795c758b3d444c082be9ac5758" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a3faa61795c758b3d444c082be9ac5758">Dn_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02056">2056</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a87f20385b6a12cc8249588a492930b31">Dn_input</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02057">2057</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a04d4474459a5b178f532443990dc10ed">Dn_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02058">2058</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#aa007104c0e9ef230ac07ad5b242ca8b5">Dn_size</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02060">2060</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a2c906a8760a85b5370b8c7f56dc4e6f3"></a><!-- doxytag: member="memory_registers::Dn_output" ref="a2c906a8760a85b5370b8c7f56dc4e6f3" args="" -->
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02061">2061</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ac8716768ab1d64ea847be358444da7ee"></a><!-- doxytag: member="memory_registers::micro_pc" ref="ac8716768ab1d64ea847be358444da7ee" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#ac8716768ab1d64ea847be358444da7ee">micro_pc</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02063">2063</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#ad13be4dbb1d8afc5ea1f9b5e8bb80e3c">micro_data</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02064">2064</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a2d55f5fd1b27c45d04af9b19559c2ae9">An_ram_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02067">2067</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a49af6a7e50d837d339f79765aa2b9ee7"></a><!-- doxytag: member="memory_registers::An_ram_output" ref="a49af6a7e50d837d339f79765aa2b9ee7" args="wire[31:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a49af6a7e50d837d339f79765aa2b9ee7">An_ram_output</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02069">2069</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a6d1775137e4a2f6a96e0cf49b76dc524"></a><!-- doxytag: member="memory_registers::dn_byteena" ref="a6d1775137e4a2f6a96e0cf49b76dc524" args="wire[3:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a6d1775137e4a2f6a96e0cf49b76dc524">dn_byteena</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[3:0]]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02072">2072</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></span> <b><span class="vhdlchar">micro_rom_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02115">2115</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02099">2099</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a892186b1bfe856b1ddaf1d8b3a448f50"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a892186b1bfe856b1ddaf1d8b3a448f50" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></span> <b><span class="vhdlchar">an_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02083">2083</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:54:37 for ao68000 by&#160;
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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