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<a href="#Inputs">Inputs</a> &#124;
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<h1>registers Module Reference</h1>  </div>
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<p>Microcode controlled registers.
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Inheritance diagram for registers:<!-- endSectionHeader --></div>
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Always Constructs</h2></td></tr>
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83 12 alfik 
<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
85 16 alfik 
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87 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a0cdf5b5316a0edcd85909fc9da5ca864">data_read</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a1864a58a4089bd5d72ba19730137c5ce">fc_state</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#acfc96bc559a0660239cb6b8a8836b862">fault_address_state</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a10ef9845f594ecc956dc1b1c8cdef44e">interrupt_trap</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aa92eeffb2c5af01c413399dfb1f58b17">interrupt_mask</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a278b33a84015867a530ac4279331d570">decoder_trap</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a6810e76be48010f9b34a91c27ddd636b">usp</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
99 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
100 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
101 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#ae09341fa22dc0b4675dc02dc4a5fb918">ea_reg_control</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
105 
Outputs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a73f335a76d3869b20956c67a67ff8f6e">pc_change</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
109 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
110 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
111 12 alfik 
<tr><td colspan="2"><h2><a name="Signals"></a>
112 
Signals</h2></td></tr>
113 16 alfik 
 <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classregisters.html#af160a45a0b3cd7794efb7fea1ed60526">pc_valid</a> </td></tr>
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</table>
115 
<hr/><a name="_details"></a><h2>Detailed Description</h2>
116 
<p>Microcode controlled registers. </p>
117 
<p>Most of the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP core registers are located in this module. At every clock cycle the microcode controls what to save into these registers. Some of the more important registers include:</p>
118 
<ul>
119 
<li>operand1, operand2 registers are inputs to the ALU,</li>
120 
<li>address, size, do_read_flag, do_write_flag, do_interrupt_flag registers tell the <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> module what kind of bus cycle to perform,</li>
121 
<li>pc register stores the current program counter,</li>
122 
<li>ir register stores the current instruction word,</li>
123 
<li>ea_mod, ea_type registers store the currently selected addressing mode. </li>
124 
</ul>
125 
 
126 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01626">1626</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/><h2>Member Function Documentation</h2>
128 
<a class="anchor" id="a7943ebd2393533b177f2cc9471614403"></a><!-- doxytag: member="registers::ALWAYS_10" ref="a7943ebd2393533b177f2cc9471614403" args="clock, reset_n" -->
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<div class="memitem">
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      <table class="memname">
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_10          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
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        <tr>
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          <td class="paramkey"></td>
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          <td></td>
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          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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        </tr>
141 
<code> [Always Construct]</code></td>
142 
        </tr>
143 
      </table>
144 
</div>
145 
<div class="memdoc">
146 
 
147 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01895">1895</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<div class="fragment"><pre class="fragment">
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<a name="l01895"></a>01895 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
150 
<a name="l01896"></a>01896     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">address_type</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
151 
<a name="l01897"></a>01897     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>)   <span class="vhdlchar">address_type</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
152 
<a name="l01898"></a>01898     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> != <a class="code" href="ao68000_8v.html#a3f7506465d358bddd4692916e422237d">`ADDRESS_IDLE</a><span class="vhdlchar"></span>)                   <span class="vhdlchar">address_type</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
153 
<a name="l01899"></a>01899 <span class="vhdlkeyword">end</span>
154 12 alfik 
</pre></div>
155 
</div>
156 
</div>
157 
<a class="anchor" id="a57a4884a23011ba445e6a69044c0b0bc"></a><!-- doxytag: member="registers::ALWAYS_11" ref="a57a4884a23011ba445e6a69044c0b0bc" args="clock, reset_n" -->
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<div class="memitem">
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      <table class="memname">
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        <tr>
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_11          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
165 
        <tr>
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          <td class="paramkey"></td>
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          <td></td>
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          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
169 12 alfik 
        </tr>
170 
<code> [Always Construct]</code></td>
171 
        </tr>
172 
      </table>
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</div>
174 
<div class="memdoc">
175 
 
176 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01901">1901</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<div class="fragment"><pre class="fragment">
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<a name="l01901"></a>01901 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
179 
<a name="l01902"></a>01902     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">movem_modreg</span> &lt;= <span class="vhdllogic">6&#39;b0</span>;
180 
<a name="l01903"></a>01903     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a59e6a074af6fbcf3490ecdb2d277e452">`MOVEM_MODREG_LOAD_0</a><span class="vhdlchar"></span>)       <span class="vhdlchar">movem_modreg</span> &lt;= <span class="vhdllogic">6&#39;b0</span>;
181 
<a name="l01904"></a>01904     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#a96857bc6f8514765cf6add0567891646">`MOVEM_MODREG_LOAD_6b001111</a><span class="vhdlchar"></span>)<span class="vhdlchar">movem_modreg</span> &lt;= <span class="vhdllogic">6&#39;b001111</span>;
182 
<a name="l01905"></a>01905     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#ab865a06c214356bb8906149ad6beebf2">`MOVEM_MODREG_INCR_BY_1</a><span class="vhdlchar"></span>)    <span class="vhdlchar">movem_modreg</span> &lt;= <span class="vhdlchar">movem_modreg</span> + <span class="vhdllogic">6&#39;d1</span>;
183 
<a name="l01906"></a>01906     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_modreg_control</span> == <a class="code" href="ao68000_8v.html#afc15f893a792d1af5e5c90f8ed788662">`MOVEM_MODREG_DECR_BY_1</a><span class="vhdlchar"></span>)    <span class="vhdlchar">movem_modreg</span> &lt;= <span class="vhdlchar">movem_modreg</span> - <span class="vhdllogic">6&#39;d1</span>;
184 
<a name="l01907"></a>01907 <span class="vhdlkeyword">end</span>
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</pre></div>
186 
</div>
187 
</div>
188 
<a class="anchor" id="a84ce568fcbe169cc02a3dc5c5bdbced2"></a><!-- doxytag: member="registers::ALWAYS_12" ref="a84ce568fcbe169cc02a3dc5c5bdbced2" args="clock, reset_n" -->
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<div class="memitem">
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<div class="memproto">
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        <tr>
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_12          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
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        <tr>
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          <td class="paramkey"></td>
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          <td></td>
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          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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        </tr>
201 
<code> [Always Construct]</code></td>
202 
        </tr>
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      </table>
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</div>
205 
<div class="memdoc">
206 
 
207 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01909">1909</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<div class="fragment"><pre class="fragment">
209 16 alfik 
<a name="l01909"></a>01909 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
210 
<a name="l01910"></a>01910     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">movem_loop</span> &lt;= <span class="vhdllogic">5&#39;b0</span>;
211 
<a name="l01911"></a>01911     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#a8465e4a24e72c1cb6e12015c4ff806c5">`MOVEM_LOOP_LOAD_0</a><span class="vhdlchar"></span>)           <span class="vhdlchar">movem_loop</span> &lt;= <span class="vhdllogic">5&#39;b0</span>;
212 
<a name="l01912"></a>01912     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_loop_control</span> == <a class="code" href="ao68000_8v.html#add999e8b65307d6d46547d776999f215">`MOVEM_LOOP_INCR_BY_1</a><span class="vhdlchar"></span>)        <span class="vhdlchar">movem_loop</span> &lt;= <span class="vhdlchar">movem_loop</span> + <span class="vhdllogic">5&#39;d1</span>;
213 
<a name="l01913"></a>01913 <span class="vhdlkeyword">end</span>
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</pre></div>
215 
</div>
216 
</div>
217 
<a class="anchor" id="a5ca9e5ee3853a6c58d80397ee08dcdfb"></a><!-- doxytag: member="registers::ALWAYS_13" ref="a5ca9e5ee3853a6c58d80397ee08dcdfb" args="clock, reset_n" -->
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<div class="memitem">
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<div class="memproto">
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      <table class="memname">
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        <tr>
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_13          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
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        <tr>
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          <td class="paramkey"></td>
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          <td></td>
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          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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        </tr>
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<code> [Always Construct]</code></td>
231 
        </tr>
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      </table>
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</div>
234 
<div class="memdoc">
235 
 
236 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01915">1915</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<div class="fragment"><pre class="fragment">
238 16 alfik 
<a name="l01915"></a>01915 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
239 
<a name="l01916"></a>01916     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">movem_reg</span> &lt;= <span class="vhdllogic">16&#39;b0</span>;
240 
<a name="l01917"></a>01917     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#aa7d78c26e9e37f761c7a0b178fe13cf8">`MOVEM_REG_FROM_OP1</a><span class="vhdlchar"></span>)           <span class="vhdlchar">movem_reg</span> &lt;= <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
241 
<a name="l01918"></a>01918     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">movem_reg_control</span> == <a class="code" href="ao68000_8v.html#ac34150d75e16d155befcfcb8a95e45a3">`MOVEM_REG_SHIFT_RIGHT</a><span class="vhdlchar"></span>)        <span class="vhdlchar">movem_reg</span> &lt;= { <span class="vhdllogic">1&#39;b0</span>, <span class="vhdlchar">movem_reg</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
242 
<a name="l01919"></a>01919 <span class="vhdlkeyword">end</span>
243 12 alfik 
</pre></div>
244 
</div>
245 
</div>
246 
<a class="anchor" id="a670e4db98926f8ddddaa84356173ff1a"></a><!-- doxytag: member="registers::ALWAYS_14" ref="a670e4db98926f8ddddaa84356173ff1a" args="clock, reset_n" -->
247 
<div class="memitem">
248 
<div class="memproto">
249 
      <table class="memname">
250 
        <tr>
251 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_14          <td></td>
252 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
253 12 alfik 
        </tr>
254 
        <tr>
255 
          <td class="paramkey"></td>
256 
          <td></td>
257 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
258 12 alfik 
        </tr>
259 
<code> [Always Construct]</code></td>
260 
        </tr>
261 
      </table>
262 
</div>
263 
<div class="memdoc">
264 
 
265 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01921">1921</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
266 12 alfik 
<div class="fragment"><pre class="fragment">
267 16 alfik 
<a name="l01921"></a>01921 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
268 
<a name="l01922"></a>01922     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">ir</span> &lt;= <span class="vhdllogic">16&#39;b0</span>;
269 
<a name="l01923"></a>01923     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">ir_control</span> == <a class="code" href="ao68000_8v.html#a987216cfc97019736d0251dcd5470e68">`IR_LOAD_WHEN_PREFETCH_VALID</a><span class="vhdlchar"></span> &amp;&amp; <a class="code" href="classregisters.html#a8031b93d1dc568b98697eb0c81b13bfd">prefetch_ir_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1&#39;b0</span>)
270 
<a name="l01924"></a>01924                                                                 <span class="vhdlchar">ir</span> &lt;= <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>];
271 
<a name="l01925"></a>01925 <span class="vhdlkeyword">end</span>
272 12 alfik 
</pre></div>
273 
</div>
274 
</div>
275 
<a class="anchor" id="a3a2e5a5ea0bbf7d06bee2afef1124393"></a><!-- doxytag: member="registers::ALWAYS_15" ref="a3a2e5a5ea0bbf7d06bee2afef1124393" args="clock, reset_n" -->
276 
<div class="memitem">
277 
<div class="memproto">
278 
      <table class="memname">
279 
        <tr>
280 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_15          <td></td>
281 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
282 12 alfik 
        </tr>
283 
        <tr>
284 
          <td class="paramkey"></td>
285 
          <td></td>
286 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
287 12 alfik 
        </tr>
288 
<code> [Always Construct]</code></td>
289 
        </tr>
290 
      </table>
291 
</div>
292 
<div class="memdoc">
293 
 
294 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01927">1927</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
295 12 alfik 
<div class="fragment"><pre class="fragment">
296 16 alfik 
<a name="l01927"></a>01927 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
297 
<a name="l01928"></a>01928     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">decoder_alu_reg</span> &lt;= <span class="vhdllogic">18&#39;b0</span>;
298 
<a name="l01929"></a>01929     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">ir_control</span> == <a class="code" href="ao68000_8v.html#a987216cfc97019736d0251dcd5470e68">`IR_LOAD_WHEN_PREFETCH_VALID</a><span class="vhdlchar"></span> &amp;&amp; <a class="code" href="classregisters.html#a8031b93d1dc568b98697eb0c81b13bfd">prefetch_ir_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1&#39;b0</span>)
299 
<a name="l01930"></a>01930                                                                 <span class="vhdlchar">decoder_alu_reg</span> &lt;= <span class="vhdlchar">decoder_alu</span>;
300 
<a name="l01931"></a>01931 <span class="vhdlkeyword">end</span>
301 12 alfik 
</pre></div>
302 
</div>
303 
</div>
304 
<a class="anchor" id="a931eb6b9c3c3c002a0eea00a7f10e10f"></a><!-- doxytag: member="registers::ALWAYS_16" ref="a931eb6b9c3c3c002a0eea00a7f10e10f" args="clock, reset_n" -->
305 
<div class="memitem">
306 
<div class="memproto">
307 
      <table class="memname">
308 
        <tr>
309 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_16          <td></td>
310 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
311 12 alfik 
        </tr>
312 
        <tr>
313 
          <td class="paramkey"></td>
314 
          <td></td>
315 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
316 12 alfik 
        </tr>
317 
<code> [Always Construct]</code></td>
318 
        </tr>
319 
      </table>
320 
</div>
321 
<div class="memdoc">
322 
 
323 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01933">1933</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
324 12 alfik 
<div class="fragment"><pre class="fragment">
325 16 alfik 
<a name="l01933"></a>01933 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
326 
<a name="l01934"></a>01934     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">trap</span> &lt;= <span class="vhdllogic">8&#39;d0</span>;
327 
<a name="l01935"></a>01935     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4267c71337dc6963db47aba754396f48">`TRAP_ILLEGAL_INSTR</a><span class="vhdlchar"></span>)                <span class="vhdlchar">trap</span> &lt;= <span class="vhdllogic">8&#39;d4</span>;
328 
<a name="l01936"></a>01936     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a111476f2c18a4085c9a5cea3692dc990">`TRAP_DIV_BY_ZERO</a><span class="vhdlchar"></span>)                  <span class="vhdlchar">trap</span> &lt;= <span class="vhdllogic">8&#39;d5</span>;
329 
<a name="l01937"></a>01937     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a7d97a1e77166d92c1d69452c3e836682">`TRAP_CHK</a><span class="vhdlchar"></span>)                          <span class="vhdlchar">trap</span> &lt;= <span class="vhdllogic">8&#39;d6</span>;
330 
<a name="l01938"></a>01938     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a66a7d33a63851daa49e101494acd6118">`TRAP_TRAPV</a><span class="vhdlchar"></span>)                        <span class="vhdlchar">trap</span> &lt;= <span class="vhdllogic">8&#39;d7</span>;
331 
<a name="l01939"></a>01939     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a940b41a2a1e4c585e15f1c2bef5d5c6f">`TRAP_PRIVIL_VIOLAT</a><span class="vhdlchar"></span>)                <span class="vhdlchar">trap</span> &lt;= <span class="vhdllogic">8&#39;d8</span>;
332 
<a name="l01940"></a>01940     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a84705ced93a01047ec829b7ea942cee0">`TRAP_TRACE</a><span class="vhdlchar"></span>)                        <span class="vhdlchar">trap</span> &lt;= <span class="vhdllogic">8&#39;d9</span>;
333 
<a name="l01941"></a>01941     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a4d09227bd9de91efc1a40bf676e10c72">`TRAP_TRAP</a><span class="vhdlchar"></span>)                         <span class="vhdlchar">trap</span> &lt;= { <span class="vhdllogic">4&#39;b0010</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] };
334 
<a name="l01942"></a>01942     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a8d6c015903e3a60339a6e8cc196bb440">`TRAP_FROM_DECODER</a><span class="vhdlchar"></span>)                 <span class="vhdlchar">trap</span> &lt;= <a class="code" href="classregisters.html#a278b33a84015867a530ac4279331d570">decoder_trap</a>;
335 
<a name="l01943"></a>01943     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trap_control</span> == <a class="code" href="ao68000_8v.html#a57812c3cf3905152a60361ae979a4c2d">`TRAP_FROM_INTERRUPT</a><span class="vhdlchar"></span>)               <span class="vhdlchar">trap</span> &lt;= <a class="code" href="classregisters.html#a10ef9845f594ecc956dc1b1c8cdef44e">interrupt_trap</a>;
336 
<a name="l01944"></a>01944 <span class="vhdlkeyword">end</span>
337 12 alfik 
</pre></div>
338 
</div>
339 
</div>
340 
<a class="anchor" id="a2a04a4a12e64f1ffb3ec95095716fee7"></a><!-- doxytag: member="registers::ALWAYS_17" ref="a2a04a4a12e64f1ffb3ec95095716fee7" args="clock, reset_n" -->
341 
<div class="memitem">
342 
<div class="memproto">
343 
      <table class="memname">
344 
        <tr>
345 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_17          <td></td>
346 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
347 12 alfik 
        </tr>
348 
        <tr>
349 
          <td class="paramkey"></td>
350 
          <td></td>
351 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
352 12 alfik 
        </tr>
353 
<code> [Always Construct]</code></td>
354 
        </tr>
355 
      </table>
356 
</div>
357 
<div class="memdoc">
358 
 
359 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01946">1946</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
360 12 alfik 
<div class="fragment"><pre class="fragment">
361 16 alfik 
<a name="l01946"></a>01946 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
362 
<a name="l01947"></a>01947     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">offset</span> &lt;= <span class="vhdllogic">32&#39;d0</span>;
363 
<a name="l01948"></a>01948     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#ad904ffb95a59f475e446877344adb415">`OFFSET_IMM_8</a><span class="vhdlchar"></span>)                    <span class="vhdlchar">offset</span> &lt;= { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] };
364 
<a name="l01949"></a>01949     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">offset_control</span> == <a class="code" href="ao68000_8v.html#a87c5da2d7633077683260709d88602e0">`OFFSET_IMM_16</a><span class="vhdlchar"></span>)                   <span class="vhdlchar">offset</span> &lt;= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
365 
<a name="l01950"></a>01950 <span class="vhdlkeyword">end</span>
366 12 alfik 
</pre></div>
367 
</div>
368 
</div>
369 
<a class="anchor" id="af284685eb0240e8fc444c84618b1af67"></a><!-- doxytag: member="registers::ALWAYS_18" ref="af284685eb0240e8fc444c84618b1af67" args="clock, reset_n" -->
370 
<div class="memitem">
371 
<div class="memproto">
372 
      <table class="memname">
373 
        <tr>
374 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_18          <td></td>
375 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
376 12 alfik 
        </tr>
377 
        <tr>
378 
          <td class="paramkey"></td>
379 
          <td></td>
380 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
381 12 alfik 
        </tr>
382 
<code> [Always Construct]</code></td>
383 
        </tr>
384 
      </table>
385 
</div>
386 
<div class="memdoc">
387 
 
388 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01952">1952</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
389 12 alfik 
<div class="fragment"><pre class="fragment">
390 16 alfik 
<a name="l01952"></a>01952 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
391 
<a name="l01953"></a>01953     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">index</span> &lt;= <span class="vhdllogic">32&#39;d0</span>;
392 
<a name="l01954"></a>01954     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#a1db54bd70d82cea2a77c6d5c823f04db">`INDEX_0</a><span class="vhdlchar"></span>)                          <span class="vhdlchar">index</span> &lt;= <span class="vhdllogic">32&#39;d0</span>;
393 
<a name="l01955"></a>01955     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">index_control</span> == <a class="code" href="ao68000_8v.html#af05405b84ee28262882d3c7ac7a5a80c">`INDEX_LOAD_EXTENDED</a><span class="vhdlchar"></span>)              <span class="vhdlchar">index</span> &lt;=
394 
<a name="l01956"></a>01956                                                                     (<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>] == <span class="vhdllogic">1&#39;b0</span>) ?
395 
<a name="l01957"></a>01957                                                                     (     (<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1&#39;b0</span>)  ?
396 
<a name="l01958"></a>01958                                                                             { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
397 
<a name="l01959"></a>01959                                                                     ) :
398 
<a name="l01960"></a>01960                                                                     (     (<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">75</span>] == <span class="vhdllogic">1&#39;b0</span>) ?
399 
<a name="l01961"></a>01961                                                                             { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } : <a class="code" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>]
400 
<a name="l01962"></a>01962                                                                     );
401 
<a name="l01963"></a>01963 <span class="vhdlkeyword">end</span>
402 12 alfik 
</pre></div>
403 
</div>
404 
</div>
405 
<a class="anchor" id="a12d4c2e0121456bcb2b23e7444c1da06"></a><!-- doxytag: member="registers::ALWAYS_19" ref="a12d4c2e0121456bcb2b23e7444c1da06" args="clock, reset_n" -->
406 
<div class="memitem">
407 
<div class="memproto">
408 
      <table class="memname">
409 
        <tr>
410 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_19          <td></td>
411 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
412 12 alfik 
        </tr>
413 
        <tr>
414 
          <td class="paramkey"></td>
415 
          <td></td>
416 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
417 12 alfik 
        </tr>
418 
<code> [Always Construct]</code></td>
419 
        </tr>
420 
      </table>
421 
</div>
422 
<div class="memdoc">
423 
 
424 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01965">1965</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
425 12 alfik 
<div class="fragment"><pre class="fragment">
426 16 alfik 
<a name="l01965"></a>01965 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
427 
<a name="l01966"></a>01966     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">stop_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
428 
<a name="l01967"></a>01967     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a5131e7ee341cd6f2ea5350a89b19a488">`STOP_FLAG_SET</a><span class="vhdlchar"></span>)                <span class="vhdlchar">stop_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
429 
<a name="l01968"></a>01968     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">stop_flag_control</span> == <a class="code" href="ao68000_8v.html#a0e63684fc863d639423c2d9f0f8e6cd9">`STOP_FLAG_CLEAR</a><span class="vhdlchar"></span>)              <span class="vhdlchar">stop_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
430 
<a name="l01969"></a>01969 <span class="vhdlkeyword">end</span>
431 12 alfik 
</pre></div>
432 
</div>
433 
</div>
434 
<a class="anchor" id="a1634ef9b02cbeb72da694a9145e2d276"></a><!-- doxytag: member="registers::ALWAYS_2" ref="a1634ef9b02cbeb72da694a9145e2d276" args="clock, reset_n" -->
435 
<div class="memitem">
436 
<div class="memproto">
437 
      <table class="memname">
438 
        <tr>
439 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_2          <td></td>
440 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
441 12 alfik 
        </tr>
442 
        <tr>
443 
          <td class="paramkey"></td>
444 
          <td></td>
445 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
446 12 alfik 
        </tr>
447 
<code> [Always Construct]</code></td>
448 
        </tr>
449 
      </table>
450 
</div>
451 
<div class="memdoc">
452 
 
453 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01746">1746</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
454 12 alfik 
<div class="fragment"><pre class="fragment">
455 16 alfik 
<a name="l01746"></a>01746 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
456 
<a name="l01747"></a>01747     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
457 
<a name="l01748"></a>01748         <span class="vhdlchar">pc</span> &lt;= <span class="vhdllogic">32&#39;d0</span>;
458 
<a name="l01749"></a>01749         <a class="code" href="classregisters.html#af160a45a0b3cd7794efb7fea1ed60526">pc_valid</a> &lt;= <span class="vhdllogic">32&#39;d0</span>;
459 
<a name="l01750"></a>01750     <span class="vhdlkeyword">end</span>
460 
<a name="l01751"></a>01751     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
461 
<a name="l01752"></a>01752         <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a63d3becb9e2a770cfd9df4a70298c30a">`PC_FROM_RESULT</a><span class="vhdlchar"></span>)                       <span class="vhdlchar">pc</span> = <a class="code" href="classregisters.html#ad27ecd2d9ef571fa88b998f3674fe9a6">result</a>;
462 
<a name="l01753"></a>01753         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a023942fcdb1eb88002847e9730cf62c2">`PC_INCR_BY_2</a><span class="vhdlchar"></span>)                    <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32&#39;d2</span>;
463 
<a name="l01754"></a>01754         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6b8aff09ca5bd77e19e6d7a5076a58bd">`PC_INCR_BY_4</a><span class="vhdlchar"></span>)                    <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32&#39;d4</span>;
464 
<a name="l01755"></a>01755         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#aefc526541d0911ae626689caead407ab">`PC_INCR_BY_SIZE</a><span class="vhdlchar"></span>)                 <span class="vhdlchar">pc</span> = (<span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1&#39;b0</span>) ? <span class="vhdlchar">pc</span> + <span class="vhdllogic">32&#39;d2</span> : <span class="vhdlchar">pc</span> + <span class="vhdllogic">32&#39;d4</span>;
465 
<a name="l01756"></a>01756         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a48c2827ab160beae0aab354b09b59e1a">`PC_FROM_PREFETCH_IR</a><span class="vhdlchar"></span>)             <span class="vhdlchar">pc</span> = <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">47</span>:<span class="vhdllogic">16</span>];
466 
<a name="l01757"></a>01757         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_control</span> == <a class="code" href="ao68000_8v.html#a6f1c276d75adca2b0290b7936476fde8">`PC_INCR_BY_2_IN_MAIN_LOOP</a><span class="vhdlchar"></span> &amp;&amp; <a class="code" href="classregisters.html#a8031b93d1dc568b98697eb0c81b13bfd">prefetch_ir_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classregisters.html#a278b33a84015867a530ac4279331d570">decoder_trap</a> == <span class="vhdllogic">8&#39;d0</span> &amp;&amp; <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1&#39;b0</span>)
467 
<a name="l01758"></a>01758                                                                 <span class="vhdlchar">pc</span> = <span class="vhdlchar">pc</span> + <span class="vhdllogic">32&#39;d2</span>;
468 
<a name="l01759"></a>01759         <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b0</span>)  <a class="code" href="classregisters.html#af160a45a0b3cd7794efb7fea1ed60526">pc_valid</a> &lt;= <span class="vhdlchar">pc</span>;
469 
<a name="l01760"></a>01760     <span class="vhdlkeyword">end</span>
470 
<a name="l01761"></a>01761 <span class="vhdlkeyword">end</span>
471 12 alfik 
</pre></div>
472 
</div>
473 
</div>
474 
<a class="anchor" id="acf180186b03cdc0ad93be0efb7fa2815"></a><!-- doxytag: member="registers::ALWAYS_20" ref="acf180186b03cdc0ad93be0efb7fa2815" args="clock, reset_n" -->
475 
<div class="memitem">
476 
<div class="memproto">
477 
      <table class="memname">
478 
        <tr>
479 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_20          <td></td>
480 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
481 12 alfik 
        </tr>
482 
        <tr>
483 
          <td class="paramkey"></td>
484 
          <td></td>
485 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
486 12 alfik 
        </tr>
487 
<code> [Always Construct]</code></td>
488 
        </tr>
489 
      </table>
490 
</div>
491 
<div class="memdoc">
492 
 
493 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01971">1971</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
494 12 alfik 
<div class="fragment"><pre class="fragment">
495 16 alfik 
<a name="l01971"></a>01971 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
496 
<a name="l01972"></a>01972     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">trace_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
497 
<a name="l01973"></a>01973     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">trace_flag_control</span> == <a class="code" href="ao68000_8v.html#a3cb5bcdd68537f527007213efe5c2d4f">`TRACE_FLAG_COPY_WHEN_NO_STOP</a><span class="vhdlchar"></span> &amp;&amp; <a class="code" href="classregisters.html#a8031b93d1dc568b98697eb0c81b13bfd">prefetch_ir_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classregisters.html#a278b33a84015867a530ac4279331d570">decoder_trap</a> == <span class="vhdllogic">8&#39;d0</span> &amp;&amp; <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1&#39;b0</span>)
498 
<a name="l01974"></a>01974                                                                 <span class="vhdlchar">trace_flag</span> &lt;= <a class="code" href="classregisters.html#a116473c99b3cbf75fd0f48a25ea9227e">sr</a>[<span class="vhdllogic">15</span>];
499 
<a name="l01975"></a>01975 <span class="vhdlkeyword">end</span>
500 12 alfik 
</pre></div>
501 
</div>
502 
</div>
503 
<a class="anchor" id="a328ee93f9ab0ed3ebab4dc5936a7c5a0"></a><!-- doxytag: member="registers::ALWAYS_21" ref="a328ee93f9ab0ed3ebab4dc5936a7c5a0" args="clock, reset_n" -->
504 
<div class="memitem">
505 
<div class="memproto">
506 
      <table class="memname">
507 
        <tr>
508 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_21          <td></td>
509 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
510 12 alfik 
        </tr>
511 
        <tr>
512 
          <td class="paramkey"></td>
513 
          <td></td>
514 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
515 12 alfik 
        </tr>
516 
<code> [Always Construct]</code></td>
517 
        </tr>
518 
      </table>
519 
</div>
520 
<div class="memdoc">
521 
 
522 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01977">1977</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
523 12 alfik 
<div class="fragment"><pre class="fragment">
524 16 alfik 
<a name="l01977"></a>01977 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
525 
<a name="l01978"></a>01978     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">group_0_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
526 
<a name="l01979"></a>01979     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a5333b31d43f3c7de70d3cad313720ef4">`GROUP_0_FLAG_SET</a><span class="vhdlchar"></span>)          <span class="vhdlchar">group_0_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
527 
<a name="l01980"></a>01980     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">group_0_flag_control</span> == <a class="code" href="ao68000_8v.html#a28adb393ace594d548dfe7f070fd837b">`GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH</a><span class="vhdlchar"></span> &amp;&amp; <a class="code" href="classregisters.html#a8031b93d1dc568b98697eb0c81b13bfd">prefetch_ir_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1&#39;b0</span>)
528 
<a name="l01981"></a>01981                                                                 <span class="vhdlchar">group_0_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
529 
<a name="l01982"></a>01982 <span class="vhdlkeyword">end</span>
530 12 alfik 
</pre></div>
531 
</div>
532 
</div>
533 
<a class="anchor" id="ad172a9061d9bb3653a3996dc4a74e101"></a><!-- doxytag: member="registers::ALWAYS_22" ref="ad172a9061d9bb3653a3996dc4a74e101" args="clock, reset_n" -->
534 
<div class="memitem">
535 
<div class="memproto">
536 
      <table class="memname">
537 
        <tr>
538 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_22          <td></td>
539 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
540 12 alfik 
        </tr>
541 
        <tr>
542 
          <td class="paramkey"></td>
543 
          <td></td>
544 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
545 12 alfik 
        </tr>
546 
<code> [Always Construct]</code></td>
547 
        </tr>
548 
      </table>
549 
</div>
550 
<div class="memdoc">
551 
 
552 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01984">1984</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
553 12 alfik 
<div class="fragment"><pre class="fragment">
554 16 alfik 
<a name="l01984"></a>01984 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
555 
<a name="l01985"></a>01985     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">instruction_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
556 
<a name="l01986"></a>01986     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#a6882447365cc7940c16017ee13305875">`INSTRUCTION_FLAG_SET</a><span class="vhdlchar"></span>)  <span class="vhdlchar">instruction_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
557 
<a name="l01987"></a>01987     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">instruction_flag_control</span> == <a class="code" href="ao68000_8v.html#adaf70d0e1aaa9fe89fc79971d67bc172">`INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP</a><span class="vhdlchar"></span> &amp;&amp; <a class="code" href="classregisters.html#a8031b93d1dc568b98697eb0c81b13bfd">prefetch_ir_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classregisters.html#a278b33a84015867a530ac4279331d570">decoder_trap</a> == <span class="vhdllogic">8&#39;d0</span> &amp;&amp; <span class="vhdlchar">stop_flag</span> == <span class="vhdllogic">1&#39;b0</span>)
558 
<a name="l01988"></a>01988                                                                 <span class="vhdlchar">instruction_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
559 
<a name="l01989"></a>01989 <span class="vhdlkeyword">end</span>
560 12 alfik 
</pre></div>
561 
</div>
562 
</div>
563 
<a class="anchor" id="a34326a20d0a44ce95c7da4da53005097"></a><!-- doxytag: member="registers::ALWAYS_23" ref="a34326a20d0a44ce95c7da4da53005097" args="clock, reset_n" -->
564 
<div class="memitem">
565 
<div class="memproto">
566 
      <table class="memname">
567 
        <tr>
568 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_23          <td></td>
569 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
570 12 alfik 
        </tr>
571 
        <tr>
572 
          <td class="paramkey"></td>
573 
          <td></td>
574 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
575 12 alfik 
        </tr>
576 
<code> [Always Construct]</code></td>
577 
        </tr>
578 
      </table>
579 
</div>
580 
<div class="memdoc">
581 
 
582 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01991">1991</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
583 12 alfik 
<div class="fragment"><pre class="fragment">
584 16 alfik 
<a name="l01991"></a>01991 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
585 
<a name="l01992"></a>01992     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                                         <span class="vhdlchar">read_modify_write_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
586 
<a name="l01993"></a>01993     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a2ba2dbb4697aa9a3559b775da0ade761">`READ_MODIFY_WRITE_FLAG_SET</a><span class="vhdlchar"></span>)      <span class="vhdlchar">read_modify_write_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
587 
<a name="l01994"></a>01994     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ace5de6cd5ad33427e8efd5ec8191c297">`READ_MODIFY_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>)    <span class="vhdlchar">read_modify_write_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
588 
<a name="l01995"></a>01995 <span class="vhdlkeyword">end</span>
589 12 alfik 
</pre></div>
590 
</div>
591 
</div>
592 
<a class="anchor" id="ad881b4aebf8b3df42129f9731b6f6098"></a><!-- doxytag: member="registers::ALWAYS_24" ref="ad881b4aebf8b3df42129f9731b6f6098" args="clock, reset_n" -->
593 
<div class="memitem">
594 
<div class="memproto">
595 
      <table class="memname">
596 
        <tr>
597 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_24          <td></td>
598 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
599 12 alfik 
        </tr>
600 
        <tr>
601 
          <td class="paramkey"></td>
602 
          <td></td>
603 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
604 12 alfik 
        </tr>
605 
<code> [Always Construct]</code></td>
606 
        </tr>
607 
      </table>
608 
</div>
609 
<div class="memdoc">
610 
 
611 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01997">1997</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
612 12 alfik 
<div class="fragment"><pre class="fragment">
613 16 alfik 
<a name="l01997"></a>01997 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
614 
<a name="l01998"></a>01998     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">do_reset_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
615 
<a name="l01999"></a>01999     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#a682472d63f131aa31c38abd6f2d577ab">`DO_RESET_FLAG_SET</a><span class="vhdlchar"></span>)        <span class="vhdlchar">do_reset_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
616 
<a name="l02000"></a>02000     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_flag_control</span> == <a class="code" href="ao68000_8v.html#afd7c962bcd95f3629d247e7790f9cf95">`DO_RESET_FLAG_CLEAR</a><span class="vhdlchar"></span>)      <span class="vhdlchar">do_reset_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
617 
<a name="l02001"></a>02001 <span class="vhdlkeyword">end</span>
618 12 alfik 
</pre></div>
619 
</div>
620 
</div>
621 
<a class="anchor" id="aa69b93f001339d4b8ae1295a5cb215ec"></a><!-- doxytag: member="registers::ALWAYS_25" ref="aa69b93f001339d4b8ae1295a5cb215ec" args="clock, reset_n" -->
622 
<div class="memitem">
623 
<div class="memproto">
624 
      <table class="memname">
625 
        <tr>
626 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_25          <td></td>
627 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
628 12 alfik 
        </tr>
629 
        <tr>
630 
          <td class="paramkey"></td>
631 
          <td></td>
632 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
633 12 alfik 
        </tr>
634 
<code> [Always Construct]</code></td>
635 
        </tr>
636 
      </table>
637 
</div>
638 
<div class="memdoc">
639 
 
640 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02003">2003</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
641 12 alfik 
<div class="fragment"><pre class="fragment">
642 16 alfik 
<a name="l02003"></a>02003 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
643 
<a name="l02004"></a>02004     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                                         <span class="vhdlchar">do_interrupt_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
644 
<a name="l02005"></a>02005     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#acc420165ae00aa63b4d40c220dc1ed79">`DO_INTERRUPT_FLAG_SET_IF_ACTIVE</a><span class="vhdlchar"></span>)      <span class="vhdlchar">do_interrupt_flag</span> &lt;= (<a class="code" href="classregisters.html#aa92eeffb2c5af01c413399dfb1f58b17">interrupt_mask</a> != <span class="vhdllogic">3&#39;b000</span>) ? <span class="vhdllogic">1&#39;b1</span> : <span class="vhdllogic">1&#39;b0</span>;
645 
<a name="l02006"></a>02006     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_flag_control</span> == <a class="code" href="ao68000_8v.html#abe668eeea71491f898b31b9c66a4db96">`DO_INTERRUPT_FLAG_CLEAR</a><span class="vhdlchar"></span>)              <span class="vhdlchar">do_interrupt_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
646 
<a name="l02007"></a>02007 <span class="vhdlkeyword">end</span>
647 12 alfik 
</pre></div>
648 
</div>
649 
</div>
650 
<a class="anchor" id="a63d22bb9298a179653d09d6b21e6c68b"></a><!-- doxytag: member="registers::ALWAYS_26" ref="a63d22bb9298a179653d09d6b21e6c68b" args="clock, reset_n" -->
651 
<div class="memitem">
652 
<div class="memproto">
653 
      <table class="memname">
654 
        <tr>
655 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_26          <td></td>
656 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
657 12 alfik 
        </tr>
658 
        <tr>
659 
          <td class="paramkey"></td>
660 
          <td></td>
661 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
662 12 alfik 
        </tr>
663 
<code> [Always Construct]</code></td>
664 
        </tr>
665 
      </table>
666 
</div>
667 
<div class="memdoc">
668 
 
669 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02009">2009</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
670 12 alfik 
<div class="fragment"><pre class="fragment">
671 16 alfik 
<a name="l02009"></a>02009 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
672 
<a name="l02010"></a>02010     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">do_read_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
673 
<a name="l02011"></a>02011     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a210a4746c070617bd4272cf091ce4977">`DO_READ_FLAG_SET</a><span class="vhdlchar"></span>)          <span class="vhdlchar">do_read_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
674 
<a name="l02012"></a>02012     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_flag_control</span> == <a class="code" href="ao68000_8v.html#a3186ce27b4c9202d124c4bee6b07e2fd">`DO_READ_FLAG_CLEAR</a><span class="vhdlchar"></span>)        <span class="vhdlchar">do_read_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
675 
<a name="l02013"></a>02013 <span class="vhdlkeyword">end</span>
676 12 alfik 
</pre></div>
677 
</div>
678 
</div>
679 
<a class="anchor" id="a66ffba6d56dd08fe7b968605c3b68465"></a><!-- doxytag: member="registers::ALWAYS_27" ref="a66ffba6d56dd08fe7b968605c3b68465" args="clock, reset_n" -->
680 
<div class="memitem">
681 
<div class="memproto">
682 
      <table class="memname">
683 
        <tr>
684 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_27          <td></td>
685 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
686 12 alfik 
        </tr>
687 
        <tr>
688 
          <td class="paramkey"></td>
689 
          <td></td>
690 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
691 12 alfik 
        </tr>
692 
<code> [Always Construct]</code></td>
693 
        </tr>
694 
      </table>
695 
</div>
696 
<div class="memdoc">
697 
 
698 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02015">2015</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
699 12 alfik 
<div class="fragment"><pre class="fragment">
700 16 alfik 
<a name="l02015"></a>02015 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
701 
<a name="l02016"></a>02016     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">do_write_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
702 
<a name="l02017"></a>02017     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#a97fc325edc48a555daf24f1757c5e7bf">`DO_WRITE_FLAG_SET</a><span class="vhdlchar"></span>)        <span class="vhdlchar">do_write_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
703 
<a name="l02018"></a>02018     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_flag_control</span> == <a class="code" href="ao68000_8v.html#ad6f9aea669c0c0233f4155f29afc4d1d">`DO_WRITE_FLAG_CLEAR</a><span class="vhdlchar"></span>)      <span class="vhdlchar">do_write_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
704 
<a name="l02019"></a>02019 <span class="vhdlkeyword">end</span>
705 12 alfik 
</pre></div>
706 
</div>
707 
</div>
708 
<a class="anchor" id="ab3c53c1dc1763e2d051eaa736e429d58"></a><!-- doxytag: member="registers::ALWAYS_28" ref="ab3c53c1dc1763e2d051eaa736e429d58" args="clock, reset_n" -->
709 
<div class="memitem">
710 
<div class="memproto">
711 
      <table class="memname">
712 
        <tr>
713 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_28          <td></td>
714 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
715 12 alfik 
        </tr>
716 
        <tr>
717 
          <td class="paramkey"></td>
718 
          <td></td>
719 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
720 12 alfik 
        </tr>
721 
<code> [Always Construct]</code></td>
722 
        </tr>
723 
      </table>
724 
</div>
725 
<div class="memdoc">
726 
 
727 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02021">2021</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
728 12 alfik 
<div class="fragment"><pre class="fragment">
729 16 alfik 
<a name="l02021"></a>02021 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
730 
<a name="l02022"></a>02022     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">do_blocked_flag</span> &lt;= <span class="vhdllogic">1&#39;b0</span>;
731 
<a name="l02023"></a>02023     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_blocked_flag_control</span> == <a class="code" href="ao68000_8v.html#ac69029fe984c3090537ed247a8106344">`DO_BLOCKED_FLAG_SET</a><span class="vhdlchar"></span>)    <span class="vhdlchar">do_blocked_flag</span> &lt;= <span class="vhdllogic">1&#39;b1</span>;
732 
<a name="l02024"></a>02024 <span class="vhdlkeyword">end</span>
733 12 alfik 
</pre></div>
734 
</div>
735 
</div>
736 16 alfik 
<a class="anchor" id="a09281e3224878c570c81844785844fe0"></a><!-- doxytag: member="registers::ALWAYS_29" ref="a09281e3224878c570c81844785844fe0" args="clock, reset_n" -->
737 
<div class="memitem">
738 
<div class="memproto">
739 
      <table class="memname">
740 
        <tr>
741 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_29          <td></td>
742 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
743 
        </tr>
744 
        <tr>
745 
          <td class="paramkey"></td>
746 
          <td></td>
747 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
748 
        </tr>
749 
<code> [Always Construct]</code></td>
750 
        </tr>
751 
      </table>
752 
</div>
753 
<div class="memdoc">
754 
 
755 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02026">2026</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
756 
<div class="fragment"><pre class="fragment">
757 
<a name="l02026"></a>02026 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
758 
<a name="l02027"></a>02027     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">data_write</span> &lt;= <span class="vhdllogic">32&#39;d0</span>;
759 
<a name="l02028"></a>02028     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">data_write_control</span> == <a class="code" href="ao68000_8v.html#ab576808298f9e1938241b8843e55c54e">`DATA_WRITE_FROM_RESULT</a><span class="vhdlchar"></span>)      <span class="vhdlchar">data_write</span> &lt;= <a class="code" href="classregisters.html#ad27ecd2d9ef571fa88b998f3674fe9a6">result</a>;
760 
<a name="l02029"></a>02029 <span class="vhdlkeyword">end</span>
761 
</pre></div>
762 
</div>
763 
</div>
764 12 alfik 
<a class="anchor" id="a160e4dadb225ac705317bf8de0c78277"></a><!-- doxytag: member="registers::ALWAYS_3" ref="a160e4dadb225ac705317bf8de0c78277" args="clock, reset_n" -->
765 
<div class="memitem">
766 
<div class="memproto">
767 
      <table class="memname">
768 
        <tr>
769 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_3          <td></td>
770 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
771 12 alfik 
        </tr>
772 
        <tr>
773 
          <td class="paramkey"></td>
774 
          <td></td>
775 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
776 12 alfik 
        </tr>
777 
<code> [Always Construct]</code></td>
778 
        </tr>
779 
      </table>
780 
</div>
781 
<div class="memdoc">
782 
 
783 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01773">1773</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
784 12 alfik 
<div class="fragment"><pre class="fragment">
785 16 alfik 
<a name="l01773"></a>01773 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
786 
<a name="l01774"></a>01774     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
787 
<a name="l01775"></a>01775         <span class="vhdlchar">size</span> &lt;= <span class="vhdllogic">2&#39;b00</span>;
788 
<a name="l01776"></a>01776     <span class="vhdlkeyword">end</span>
789 
<a name="l01777"></a>01777     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">size_control</span> != <a class="code" href="ao68000_8v.html#a85698146140d774ffe2b54e5be255726">`SIZE_IDLE</a><span class="vhdlchar"></span>) <span class="vhdlkeyword">begin</span>
790 
<a name="l01778"></a>01778         <span class="keyword">// BYTE</span>
791 
<a name="l01779"></a>01779         <span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] &lt;= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a8a04b85bed76a4381d1187aec9694a7e">`SIZE_BYTE</a><span class="vhdlchar"></span>)
792 
<a name="l01780"></a>01780                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2&#39;b00</span>))
793 
<a name="l01781"></a>01781                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2&#39;b01</span>))
794 
<a name="l01782"></a>01782                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3&#39;b000</span>));
795 
<a name="l01783"></a>01783         <span class="keyword">// WORD</span>
796 
<a name="l01784"></a>01784         <span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] &lt;= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a9da3fa515a6d6e5949573714c5682999">`SIZE_WORD</a><span class="vhdlchar"></span>)
797 
<a name="l01785"></a>01785                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">`SIZE_1</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2&#39;b00</span>))
798 
<a name="l01786"></a>01786                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">`SIZE_1_PLUS</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2&#39;b10</span>))
799 
<a name="l01787"></a>01787                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">`SIZE_2</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1&#39;b0</span>))
800 
<a name="l01788"></a>01788                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2&#39;b01</span>))
801 
<a name="l01789"></a>01789                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">13</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">2&#39;b11</span>))
802 
<a name="l01790"></a>01790                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1&#39;b0</span>));
803 
<a name="l01791"></a>01791         <span class="keyword">// LONG</span>
804 
<a name="l01792"></a>01792         <span class="vhdlchar">size</span>[<span class="vhdllogic">2</span>] &lt;= (<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ae54bb350f5d3a019211af2a214f46273">`SIZE_LONG</a><span class="vhdlchar"></span>)
805 
<a name="l01793"></a>01793                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1b8724879ab643802f27348fa58f7208">`SIZE_1</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2&#39;b00</span>))
806 
<a name="l01794"></a>01794                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a83d20a891b85a7fabe3d8c74b66ad884">`SIZE_1_PLUS</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2&#39;b10</span>))
807 
<a name="l01795"></a>01795                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a1eca0e7e9287916bcfa96b96b0c46154">`SIZE_2</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1&#39;b1</span>))
808 
<a name="l01796"></a>01796                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#ad8d417f0548efb4299bed1ed75004cbe">`SIZE_3</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1&#39;b1</span>))
809 
<a name="l01797"></a>01797                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a4d9196508aad9e995d45bfda3f7c6884">`SIZE_4</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">12</span>] == <span class="vhdllogic">1&#39;b0</span>))
810 
<a name="l01798"></a>01798                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a0e07cba66f352b53ebb2dd2a48c58cff">`SIZE_5</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1&#39;b1</span>))
811 
<a name="l01799"></a>01799                 | ((<span class="vhdlchar">size_control</span> == <a class="code" href="ao68000_8v.html#a3ce4d5e820fe7c438d0bd9c7f067ac3f">`SIZE_6</a><span class="vhdlchar"></span>) &amp;&amp; (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3&#39;b000</span>));
812 
<a name="l01800"></a>01800     <span class="vhdlkeyword">end</span>
813 
<a name="l01801"></a>01801 <span class="vhdlkeyword">end</span>
814 12 alfik 
</pre></div>
815 
</div>
816 
</div>
817 
<a class="anchor" id="a098bb8c5f886c173a49d1e015dd37289"></a><!-- doxytag: member="registers::ALWAYS_4" ref="a098bb8c5f886c173a49d1e015dd37289" args="clock, reset_n" -->
818 
<div class="memitem">
819 
<div class="memproto">
820 
      <table class="memname">
821 
        <tr>
822 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_4          <td></td>
823 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
824 12 alfik 
        </tr>
825 
        <tr>
826 
          <td class="paramkey"></td>
827 
          <td></td>
828 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
829 12 alfik 
        </tr>
830 
<code> [Always Construct]</code></td>
831 
        </tr>
832 
      </table>
833 
</div>
834 
<div class="memdoc">
835 
 
836 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01803">1803</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
837 12 alfik 
<div class="fragment"><pre class="fragment">
838 16 alfik 
<a name="l01803"></a>01803 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
839 
<a name="l01804"></a>01804     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> &lt;= <span class="vhdllogic">3&#39;b000</span>;
840 
<a name="l01805"></a>01805     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ae09341fa22dc0b4675dc02dc4a5fb918">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab608c5385657295b902b8ffc21c43d03">`EA_REG_IR_2_0</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> &lt;= <span class="vhdlchar">ir</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
841 
<a name="l01806"></a>01806     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ae09341fa22dc0b4675dc02dc4a5fb918">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#a56f29ecaaf69843219c88d8e0f252048">`EA_REG_IR_11_9</a><span class="vhdlchar"></span>)                  <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> &lt;= <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>];
842 
<a name="l01807"></a>01807     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ae09341fa22dc0b4675dc02dc4a5fb918">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#af2b8ce7c793c79dee8394ad309a1ef71">`EA_REG_MOVEM_REG_2_0</a><span class="vhdlchar"></span>)            <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> &lt;= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
843 
<a name="l01808"></a>01808     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ae09341fa22dc0b4675dc02dc4a5fb918">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#aa5ef414e1c0f769a38cdd8b3aeef5184">`EA_REG_3b111</a><span class="vhdlchar"></span>)                    <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> &lt;= <span class="vhdllogic">3&#39;b111</span>;
844 
<a name="l01809"></a>01809     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#ae09341fa22dc0b4675dc02dc4a5fb918">ea_reg_control</a> == <a class="code" href="ao68000_8v.html#ab4936576a8613273a6487d2b78812c55">`EA_REG_3b100</a><span class="vhdlchar"></span>)                    <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> &lt;= <span class="vhdllogic">3&#39;b100</span>;
845 
<a name="l01810"></a>01810 <span class="vhdlkeyword">end</span>
846 12 alfik 
</pre></div>
847 
</div>
848 
</div>
849 
<a class="anchor" id="a6fc98500064486297076cc7c8e99e16f"></a><!-- doxytag: member="registers::ALWAYS_5" ref="a6fc98500064486297076cc7c8e99e16f" args="clock, reset_n" -->
850 
<div class="memitem">
851 
<div class="memproto">
852 
      <table class="memname">
853 
        <tr>
854 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_5          <td></td>
855 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
856 12 alfik 
        </tr>
857 
        <tr>
858 
          <td class="paramkey"></td>
859 
          <td></td>
860 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
861 12 alfik 
        </tr>
862 
<code> [Always Construct]</code></td>
863 
        </tr>
864 
      </table>
865 
</div>
866 
<div class="memdoc">
867 
 
868 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01812">1812</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
869 12 alfik 
<div class="fragment"><pre class="fragment">
870 16 alfik 
<a name="l01812"></a>01812 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
871 
<a name="l01813"></a>01813     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdllogic">3&#39;b000</span>;
872 
<a name="l01814"></a>01814     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a0c094175d5b6718611708b08af5e6342">`EA_MOD_IR_5_3</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
873 
<a name="l01815"></a>01815     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a45b520ba3dd813510ddca0ebe0a652f4">`EA_MOD_MOVEM_MOD_5_3</a><span class="vhdlchar"></span>)            <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdlchar">movem_modreg</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>];
874 
<a name="l01816"></a>01816     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a46d304e545e3f136f9bc7fe83ffe61df">`EA_MOD_IR_8_6</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdlchar">ir</span>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>];
875 
<a name="l01817"></a>01817     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a2e15ad20aa0f28ef9042982260a21316">`EA_MOD_PREDEC</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdllogic">3&#39;b100</span>;
876 
<a name="l01818"></a>01818     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ae4ecbd320f11539d132c8e6aa3fdcb5c">`EA_MOD_3b111</a><span class="vhdlchar"></span>)                    <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdllogic">3&#39;b111</span>;
877 
<a name="l01819"></a>01819     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#aee18d2c3a30bdec23a7de0889deb0d94">`EA_MOD_DN_PREDEC</a><span class="vhdlchar"></span>)                <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">3</span>] == <span class="vhdllogic">1&#39;b0</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3&#39;b000</span> : <span class="keyword">/* -(An) **/</span> <span class="vhdllogic">3&#39;b100</span>;
878 
<a name="l01820"></a>01820     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#ac190b9646213ddb87ec06a5858d479b3">`EA_MOD_DN_AN_EXG</a><span class="vhdlchar"></span>)                <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5&#39;b01000</span> || <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">5&#39;b10001</span>) ? <span class="keyword">/* Dn **/</span> <span class="vhdllogic">3&#39;b000</span> : <span class="keyword">/* An **/</span> <span class="vhdllogic">3&#39;b001</span>;
879 
<a name="l01821"></a>01821     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a51a36024571aca1d7d7c7fa928956589">`EA_MOD_POSTINC</a><span class="vhdlchar"></span>)                  <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdllogic">3&#39;b011</span>;
880 
<a name="l01822"></a>01822     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a7a6ccf87a21e66605e4672e95a6578e4">`EA_MOD_AN</a><span class="vhdlchar"></span>)                       <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdllogic">3&#39;b001</span>;
881 
<a name="l01823"></a>01823     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a8a000a242ea6cc51ac97ec35753faf7b">`EA_MOD_DN</a><span class="vhdlchar"></span>)                       <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdllogic">3&#39;b000</span>;
882 
<a name="l01824"></a>01824     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a> == <a class="code" href="ao68000_8v.html#a88ded717145b6f89a3cd3416577225f0">`EA_MOD_INDIRECTOFFSET</a><span class="vhdlchar"></span>)           <a class="code" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a> &lt;= <span class="vhdllogic">3&#39;b101</span>;
883 
<a name="l01825"></a>01825 <span class="vhdlkeyword">end</span>
884 12 alfik 
</pre></div>
885 
</div>
886 
</div>
887 
<a class="anchor" id="aa536be1ed88148e7c828c0183e8a0757"></a><!-- doxytag: member="registers::ALWAYS_6" ref="aa536be1ed88148e7c828c0183e8a0757" args="clock, reset_n" -->
888 
<div class="memitem">
889 
<div class="memproto">
890 
      <table class="memname">
891 
        <tr>
892 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_6          <td></td>
893 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
894 12 alfik 
        </tr>
895 
        <tr>
896 
          <td class="paramkey"></td>
897 
          <td></td>
898 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
899 12 alfik 
        </tr>
900 
<code> [Always Construct]</code></td>
901 
        </tr>
902 
      </table>
903 
</div>
904 
<div class="memdoc">
905 
 
906 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01827">1827</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
907 12 alfik 
<div class="fragment"><pre class="fragment">
908 16 alfik 
<a name="l01827"></a>01827 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
909 
<a name="l01828"></a>01828     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a30b69aee8fb5af4ab38fc9f0d92a28d3">`EA_TYPE_IDLE</a><span class="vhdlchar"></span>;
910 
<a name="l01829"></a>01829     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>)                    <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a6f693ee79161bffa99f05d9f5b89a2d0">`EA_TYPE_ALL</a><span class="vhdlchar"></span>;
911 
<a name="l01830"></a>01830     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>)        <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a925f0004ba49b82dbdf7c4ae969ba6ed">`EA_TYPE_CONTROL_POSTINC</a><span class="vhdlchar"></span>;
912 
<a name="l01831"></a>01831     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>)    <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a41499eaa1b7aa62f455a07e5435d754a">`EA_TYPE_CONTROLALTER_PREDEC</a><span class="vhdlchar"></span>;
913 
<a name="l01832"></a>01832     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>)                <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#ae2c794f81236993a23138cbf3f7eda44">`EA_TYPE_CONTROL</a><span class="vhdlchar"></span>;
914 
<a name="l01833"></a>01833     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>)              <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a17a8a468ddfc3bdb178081a368f4dd6c">`EA_TYPE_DATAALTER</a><span class="vhdlchar"></span>;
915 
<a name="l01834"></a>01834     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>)                  <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a8e7bc745d4def25f5a995a6955dbdb4b">`EA_TYPE_DN_AN</a><span class="vhdlchar"></span>;
916 
<a name="l01835"></a>01835     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>)            <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a653530f090b85ba7bcd93912b8834412">`EA_TYPE_MEMORYALTER</a><span class="vhdlchar"></span>;
917 
<a name="l01836"></a>01836     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a> == <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a> &lt;= <a class="code" href="ao68000_8v.html#a1b85de8c778c471fdc569b4ef5f3bc60">`EA_TYPE_DATA</a><span class="vhdlchar"></span>;
918 
<a name="l01837"></a>01837 <span class="vhdlkeyword">end</span>
919 12 alfik 
</pre></div>
920 
</div>
921 
</div>
922 
<a class="anchor" id="a8fa9503b229756474eafc4b087aa6511"></a><!-- doxytag: member="registers::ALWAYS_7" ref="a8fa9503b229756474eafc4b087aa6511" args="clock, reset_n" -->
923 
<div class="memitem">
924 
<div class="memproto">
925 
      <table class="memname">
926 
        <tr>
927 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_7          <td></td>
928 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
929 12 alfik 
        </tr>
930 
        <tr>
931 
          <td class="paramkey"></td>
932 
          <td></td>
933 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
934 12 alfik 
        </tr>
935 
<code> [Always Construct]</code></td>
936 
        </tr>
937 
      </table>
938 
</div>
939 
<div class="memdoc">
940 
 
941 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01839">1839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
942 12 alfik 
<div class="fragment"><pre class="fragment">
943 16 alfik 
<a name="l01839"></a>01839 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
944 
<a name="l01840"></a>01840     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <span class="vhdllogic">32&#39;hFFFFFFFF</span>;
945 
<a name="l01841"></a>01841     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a29e287eda5813f253f9f1cd527021533">`OP1_FROM_OP2</a><span class="vhdlchar"></span>)                  <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <span class="vhdlchar">operand2</span>;
946 
<a name="l01842"></a>01842     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ab601cf0d52e5fe6ae155ab8084b236e1">`OP1_FROM_ADDRESS</a><span class="vhdlchar"></span>)              <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <span class="vhdlchar">address</span>;
947 
<a name="l01843"></a>01843     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aec7f41507eab6c659f5d544c942b441e">`OP1_FROM_DATA</a><span class="vhdlchar"></span>)                 <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;=
948 
<a name="l01844"></a>01844                                                                     (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a0cdf5b5316a0edcd85909fc9da5ca864">data_read</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a0cdf5b5316a0edcd85909fc9da5ca864">data_read</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
949 
<a name="l01845"></a>01845                                                                     (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1&#39;b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a0cdf5b5316a0edcd85909fc9da5ca864">data_read</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a0cdf5b5316a0edcd85909fc9da5ca864">data_read</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
950 
<a name="l01846"></a>01846                                                                     <a class="code" href="classregisters.html#a0cdf5b5316a0edcd85909fc9da5ca864">data_read</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
951 
<a name="l01847"></a>01847     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#abc0874c9141535c9c6a071653810c8fc">`OP1_FROM_IMMEDIATE</a><span class="vhdlchar"></span>)            <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;=
952 
<a name="l01848"></a>01848                                                                     (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">71</span>]}}, <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">71</span>:<span class="vhdllogic">64</span>] } :
953 
<a name="l01849"></a>01849                                                                     (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1&#39;b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] } :
954 
<a name="l01850"></a>01850                                                                     <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
955 
<a name="l01851"></a>01851     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a2adbf20e4776f4f5449563560fcfea3e">`OP1_FROM_RESULT</a><span class="vhdlchar"></span>)               <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <a class="code" href="classregisters.html#ad27ecd2d9ef571fa88b998f3674fe9a6">result</a>;
956 
<a name="l01852"></a>01852     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ac2bd7be96e464a7a06affeb71024f266">`OP1_MOVEQ</a><span class="vhdlchar"></span>)                     <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
957 
<a name="l01853"></a>01853     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#aade66d4090f1aea9ed568a4e17ff1eae">`OP1_FROM_PC</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <a class="code" href="classregisters.html#af160a45a0b3cd7794efb7fea1ed60526">pc_valid</a>;
958 
<a name="l01854"></a>01854     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4db6f8d952dd7d7cfffeb0de4ad4a08b">`OP1_LOAD_ZEROS</a><span class="vhdlchar"></span>)                <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <span class="vhdllogic">32&#39;b0</span>;
959 
<a name="l01855"></a>01855     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#ae8489ec12e458975d614347191ba2004">`OP1_LOAD_ONES</a><span class="vhdlchar"></span>)                 <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <span class="vhdllogic">32&#39;hFFFFFFFF</span>;
960 
<a name="l01856"></a>01856     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a9e1d49d77f5b144fff6cc8c0c021e5d2">`OP1_FROM_SR</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= { <span class="vhdllogic">16&#39;b0</span>, <a class="code" href="classregisters.html#a116473c99b3cbf75fd0f48a25ea9227e">sr</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1&#39;b0</span>, <a class="code" href="classregisters.html#a116473c99b3cbf75fd0f48a25ea9227e">sr</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2&#39;b0</span>, <a class="code" href="classregisters.html#a116473c99b3cbf75fd0f48a25ea9227e">sr</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3&#39;b0</span>, <a class="code" href="classregisters.html#a116473c99b3cbf75fd0f48a25ea9227e">sr</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
961 
<a name="l01857"></a>01857     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a1a44c33265ec779ad10e437621cda43b">`OP1_FROM_USP</a><span class="vhdlchar"></span>)                  <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <a class="code" href="classregisters.html#a6810e76be48010f9b34a91c27ddd636b">usp</a>;
962 
<a name="l01858"></a>01858     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a4900ac90de9fd53eaeb1acddf51a9008">`OP1_FROM_AN</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;=
963 
<a name="l01859"></a>01859                                                                     (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1&#39;b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
964 
<a name="l01860"></a>01860                                                                     <a class="code" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
965 
<a name="l01861"></a>01861     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a3aa722db3503e9370be36b3d409f3e17">`OP1_FROM_DN</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;=
966 
<a name="l01862"></a>01862                                                                     (<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b1</span>) ? { {<span class="vhdllogic">24</span>{<a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] } :
967 
<a name="l01863"></a>01863                                                                     (<span class="vhdlchar">size</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1&#39;b1</span>) ? { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] } :
968 
<a name="l01864"></a>01864                                                                     <a class="code" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
969 
<a name="l01865"></a>01865     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a083db35259f035ab10f606d2c7dd82c6">`OP1_FROM_IR</a><span class="vhdlchar"></span>)                   <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= { <span class="vhdllogic">16&#39;b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
970 
<a name="l01866"></a>01866     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand1_control</span> == <a class="code" href="ao68000_8v.html#a707f0ca7fa1a08446ba113ede9d5d8a4">`OP1_FROM_FAULT_ADDRESS</a><span class="vhdlchar"></span>)        <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a> &lt;= <a class="code" href="classregisters.html#acfc96bc559a0660239cb6b8a8836b862">fault_address_state</a>;
971 
<a name="l01867"></a>01867 <span class="vhdlkeyword">end</span>
972 12 alfik 
</pre></div>
973 
</div>
974 
</div>
975 
<a class="anchor" id="ae6143c84411ad159cbe1662f3909e726"></a><!-- doxytag: member="registers::ALWAYS_8" ref="ae6143c84411ad159cbe1662f3909e726" args="clock, reset_n" -->
976 
<div class="memitem">
977 
<div class="memproto">
978 
      <table class="memname">
979 
        <tr>
980 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_8          <td></td>
981 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
982 12 alfik 
        </tr>
983 
        <tr>
984 
          <td class="paramkey"></td>
985 
          <td></td>
986 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
987 12 alfik 
        </tr>
988 
<code> [Always Construct]</code></td>
989 
        </tr>
990 
      </table>
991 
</div>
992 
<div class="memdoc">
993 
 
994 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01869">1869</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
995 12 alfik 
<div class="fragment"><pre class="fragment">
996 16 alfik 
<a name="l01869"></a>01869 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
997 
<a name="l01870"></a>01870     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">operand2</span> &lt;= <span class="vhdllogic">32&#39;hFFFFFFFF</span>;
998 
<a name="l01871"></a>01871     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a092ca695ecfa2de9e4d4a27bbd89d40f">`OP2_FROM_OP1</a><span class="vhdlchar"></span>)                  <span class="vhdlchar">operand2</span> &lt;= <a class="code" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a>;
999 
<a name="l01872"></a>01872     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a5c2c8ed577b6ab91a5ae3861643575e7">`OP2_LOAD_1</a><span class="vhdlchar"></span>)                    <span class="vhdlchar">operand2</span> &lt;= <span class="vhdllogic">32&#39;d1</span>;
1000 
<a name="l01873"></a>01873     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a7c904b70c2347aaee330105f74a69fc1">`OP2_LOAD_COUNT</a><span class="vhdlchar"></span>)                <span class="vhdlchar">operand2</span> &lt;=
1001 
<a name="l01874"></a>01874                                                                     (<span class="vhdlchar">ir</span>[<span class="vhdllogic">5</span>] == <span class="vhdllogic">1&#39;b0</span>) ? ( (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3&#39;b000</span>) ? <span class="vhdllogic">32&#39;b1000</span> : { <span class="vhdllogic">29&#39;b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] } ) :
1002 
<a name="l01875"></a>01875                                                                     { <span class="vhdllogic">26&#39;b0</span>, <span class="vhdlchar">operand2</span>[<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] };
1003 
<a name="l01876"></a>01876     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#aacec01f4da467eb6785c611710c1219d">`OP2_ADDQ_SUBQ</a><span class="vhdlchar"></span>)                 <span class="vhdlchar">operand2</span> &lt;= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3&#39;b000</span>) ? <span class="vhdllogic">32&#39;b1000</span> : { <span class="vhdllogic">29&#39;b0</span>, <span class="vhdlchar">ir</span>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] };
1004 
<a name="l01877"></a>01877     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#ad8cdca7f0cbac16e09b4e1a1e3ab4f11">`OP2_MOVE_OFFSET</a><span class="vhdlchar"></span>)               <span class="vhdlchar">operand2</span> &lt;= (<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8&#39;b0</span>) ? <span class="vhdlchar">operand2</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] : { {<span class="vhdllogic">24</span>{<span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>]}}, <span class="vhdlchar">ir</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
1005 
<a name="l01878"></a>01878     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a041be53a35bc1a415713d34c839c81c5">`OP2_MOVE_ADDRESS_BUS_INFO</a><span class="vhdlchar"></span>)     <span class="vhdlchar">operand2</span> &lt;= { <span class="vhdllogic">16&#39;b0</span>, <span class="vhdllogic">11&#39;b0</span>, <a class="code" href="classregisters.html#ae12d419de758617259ab74281fd09f03">rw_state</a>, <span class="vhdlchar">instruction_flag</span>, <a class="code" href="classregisters.html#a1864a58a4089bd5d72ba19730137c5ce">fc_state</a>};
1006 
<a name="l01879"></a>01879     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">operand2_control</span> == <a class="code" href="ao68000_8v.html#a81d303d3fcf43bd2ed3b99072571f816">`OP2_DECR_BY_1</a><span class="vhdlchar"></span>)                 <span class="vhdlchar">operand2</span> &lt;= <span class="vhdlchar">operand2</span> - <span class="vhdllogic">32&#39;b1</span>;
1007 
<a name="l01880"></a>01880 <span class="vhdlkeyword">end</span>
1008 12 alfik 
</pre></div>
1009 
</div>
1010 
</div>
1011 
<a class="anchor" id="ae04888e60d745f9f64ca5c52d0969adb"></a><!-- doxytag: member="registers::ALWAYS_9" ref="ae04888e60d745f9f64ca5c52d0969adb" args="clock, reset_n" -->
1012 
<div class="memitem">
1013 
<div class="memproto">
1014 
      <table class="memname">
1015 
        <tr>
1016 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_9          <td></td>
1017 16 alfik 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
1018 12 alfik 
        </tr>
1019 
        <tr>
1020 
          <td class="paramkey"></td>
1021 
          <td></td>
1022 16 alfik 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
1023 12 alfik 
        </tr>
1024 
<code> [Always Construct]</code></td>
1025 
        </tr>
1026 
      </table>
1027 
</div>
1028 
<div class="memdoc">
1029 
 
1030 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01882">1882</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1031 12 alfik 
<div class="fragment"><pre class="fragment">
1032 16 alfik 
<a name="l01882"></a>01882 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a>) <span class="vhdlkeyword">begin</span>
1033 
<a name="l01883"></a>01883     <span class="vhdlkeyword">if</span>(<a class="code" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>)                                         <span class="vhdlchar">address</span> &lt;= <span class="vhdllogic">32&#39;b0</span>;
1034 
<a name="l01884"></a>01884     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a864e0b06304816dec2d4658503d97495">`ADDRESS_INCR_BY_SIZE</a><span class="vhdlchar"></span>)           <span class="vhdlchar">address</span> &lt;= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) &amp;&amp; <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> == <span class="vhdllogic">3&#39;b111</span>) ? <span class="vhdlchar">address</span> + <span class="vhdllogic">32&#39;d2</span> : <span class="vhdlchar">address</span> + {<span class="vhdllogic">29&#39;d0</span>,<span class="vhdlchar">size</span>};
1035 
<a name="l01885"></a>01885     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa479827c57933eb9ff03788bbe9d6e3a">`ADDRESS_DECR_BY_SIZE</a><span class="vhdlchar"></span>)           <span class="vhdlchar">address</span> &lt;= ((<span class="vhdlchar">size</span>[<span class="vhdllogic">0</span>]) &amp;&amp; <a class="code" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a> == <span class="vhdllogic">3&#39;b111</span>) ? <span class="vhdlchar">address</span> - <span class="vhdllogic">32&#39;d2</span> : <span class="vhdlchar">address</span> - {<span class="vhdllogic">29&#39;d0</span>,<span class="vhdlchar">size</span>};
1036 
<a name="l01886"></a>01886     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac4044068e496c3393c6336b72873a958">`ADDRESS_INCR_BY_2</a><span class="vhdlchar"></span>)              <span class="vhdlchar">address</span> &lt;= <span class="vhdlchar">address</span> + <span class="vhdllogic">32&#39;d2</span>;
1037 
<a name="l01887"></a>01887     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#afc15ad5da6b4afd71eb879476c603fe3">`ADDRESS_FROM_AN_OUTPUT</a><span class="vhdlchar"></span>)         <span class="vhdlchar">address</span> &lt;= <a class="code" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a>;
1038 
<a name="l01888"></a>01888     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#ac1143ff5a059fc5609c9419fcd402ae1">`ADDRESS_FROM_BASE_INDEX_OFFSET</a><span class="vhdlchar"></span>) <span class="vhdlchar">address</span> &lt;= <span class="vhdlchar">address</span> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
1039 
<a name="l01889"></a>01889     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa6ba908e680fe87e46ac1cf014eed463">`ADDRESS_FROM_IMM_16</a><span class="vhdlchar"></span>)            <span class="vhdlchar">address</span> &lt;= { {<span class="vhdllogic">16</span>{<a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>]}}, <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>] };
1040 
<a name="l01890"></a>01890     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa688332c940cad3a10561a5c9f74698a">`ADDRESS_FROM_IMM_32</a><span class="vhdlchar"></span>)            <span class="vhdlchar">address</span> &lt;= <a class="code" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>];
1041 
<a name="l01891"></a>01891     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#aa7a6ef5c21bbbf8a3c5a0437bdda3c85">`ADDRESS_FROM_PC_INDEX_OFFSET</a><span class="vhdlchar"></span>)   <span class="vhdlchar">address</span> &lt;= <a class="code" href="classregisters.html#af160a45a0b3cd7794efb7fea1ed60526">pc_valid</a> + <span class="vhdlchar">index</span> + <span class="vhdlchar">offset</span>;
1042 
<a name="l01892"></a>01892     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_control</span> == <a class="code" href="ao68000_8v.html#a2a30a0ecfa48e96cc5be837e7db71cab">`ADDRESS_FROM_TRAP</a><span class="vhdlchar"></span>)              <span class="vhdlchar">address</span> &lt;= {<span class="vhdllogic">22&#39;b0</span>, <span class="vhdlchar">trap</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">2&#39;b0</span>};
1043 
<a name="l01893"></a>01893 <span class="vhdlkeyword">end</span>
1044 12 alfik 
</pre></div>
1045 
</div>
1046 
</div>
1047 
<hr/><h2>Member Data Documentation</h2>
1048 16 alfik 
<a class="anchor" id="aa395a813867161909f2bd9ed1dd481b6"></a><!-- doxytag: member="registers::clock" ref="aa395a813867161909f2bd9ed1dd481b6" args="" -->
1049 12 alfik 
<div class="memitem">
1050 
<div class="memproto">
1051 
      <table class="memname">
1052 
        <tr>
1053 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aa395a813867161909f2bd9ed1dd481b6">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1054 12 alfik 
        </tr>
1055 
      </table>
1056 
</div>
1057 
<div class="memdoc">
1058 
 
1059 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01627">1627</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1060 12 alfik 
 
1061 
</div>
1062 
</div>
1063 16 alfik 
<a class="anchor" id="a015ee03d06fbd101adca95c762a5f99a"></a><!-- doxytag: member="registers::reset_n" ref="a015ee03d06fbd101adca95c762a5f99a" args="" -->
1064 12 alfik 
<div class="memitem">
1065 
<div class="memproto">
1066 
      <table class="memname">
1067 
        <tr>
1068 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a015ee03d06fbd101adca95c762a5f99a">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1069 12 alfik 
        </tr>
1070 
      </table>
1071 
</div>
1072 
<div class="memdoc">
1073 
 
1074 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01628">1628</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1075 12 alfik 
 
1076 
</div>
1077 
</div>
1078 16 alfik 
<a class="anchor" id="a0cdf5b5316a0edcd85909fc9da5ca864"></a><!-- doxytag: member="registers::data_read" ref="a0cdf5b5316a0edcd85909fc9da5ca864" args="" -->
1079 12 alfik 
<div class="memitem">
1080 
<div class="memproto">
1081 
      <table class="memname">
1082 
        <tr>
1083 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a0cdf5b5316a0edcd85909fc9da5ca864">data_read</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1084 12 alfik 
        </tr>
1085 
      </table>
1086 
</div>
1087 
<div class="memdoc">
1088 
 
1089 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01630">1630</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1090 12 alfik 
 
1091 
</div>
1092 
</div>
1093 16 alfik 
<a class="anchor" id="a4d5882d1f9437d14d18d0c08bd6907ba"></a><!-- doxytag: member="registers::prefetch_ir" ref="a4d5882d1f9437d14d18d0c08bd6907ba" args="" -->
1094 12 alfik 
<div class="memitem">
1095 
<div class="memproto">
1096 
      <table class="memname">
1097 
        <tr>
1098 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a4d5882d1f9437d14d18d0c08bd6907ba">prefetch_ir</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">79</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1099 12 alfik 
        </tr>
1100 
      </table>
1101 
</div>
1102 
<div class="memdoc">
1103 
 
1104 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01631">1631</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1105 12 alfik 
 
1106 
</div>
1107 
</div>
1108 16 alfik 
<a class="anchor" id="a8031b93d1dc568b98697eb0c81b13bfd"></a><!-- doxytag: member="registers::prefetch_ir_valid" ref="a8031b93d1dc568b98697eb0c81b13bfd" args="" -->
1109 12 alfik 
<div class="memitem">
1110 
<div class="memproto">
1111 
      <table class="memname">
1112 
        <tr>
1113 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a8031b93d1dc568b98697eb0c81b13bfd">prefetch_ir_valid</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1114 12 alfik 
        </tr>
1115 
      </table>
1116 
</div>
1117 
<div class="memdoc">
1118 
 
1119 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01632">1632</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1120 12 alfik 
 
1121 
</div>
1122 
</div>
1123 16 alfik 
<a class="anchor" id="ad27ecd2d9ef571fa88b998f3674fe9a6"></a><!-- doxytag: member="registers::result" ref="ad27ecd2d9ef571fa88b998f3674fe9a6" args="" -->
1124 12 alfik 
<div class="memitem">
1125 
<div class="memproto">
1126 
      <table class="memname">
1127 
        <tr>
1128 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#ad27ecd2d9ef571fa88b998f3674fe9a6">result</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1129 12 alfik 
        </tr>
1130 
      </table>
1131 
</div>
1132 
<div class="memdoc">
1133 
 
1134 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01633">1633</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1135 12 alfik 
 
1136 
</div>
1137 
</div>
1138 16 alfik 
<a class="anchor" id="a116473c99b3cbf75fd0f48a25ea9227e"></a><!-- doxytag: member="registers::sr" ref="a116473c99b3cbf75fd0f48a25ea9227e" args="" -->
1139 12 alfik 
<div class="memitem">
1140 
<div class="memproto">
1141 
      <table class="memname">
1142 
        <tr>
1143 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a116473c99b3cbf75fd0f48a25ea9227e">sr</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1144 12 alfik 
        </tr>
1145 
      </table>
1146 
</div>
1147 
<div class="memdoc">
1148 
 
1149 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01634">1634</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1150 12 alfik 
 
1151 
</div>
1152 
</div>
1153 16 alfik 
<a class="anchor" id="ae12d419de758617259ab74281fd09f03"></a><!-- doxytag: member="registers::rw_state" ref="ae12d419de758617259ab74281fd09f03" args="" -->
1154 12 alfik 
<div class="memitem">
1155 
<div class="memproto">
1156 
      <table class="memname">
1157 
        <tr>
1158 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#ae12d419de758617259ab74281fd09f03">rw_state</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1159 12 alfik 
        </tr>
1160 
      </table>
1161 
</div>
1162 
<div class="memdoc">
1163 
 
1164 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01635">1635</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1165 12 alfik 
 
1166 
</div>
1167 
</div>
1168 16 alfik 
<a class="anchor" id="a1864a58a4089bd5d72ba19730137c5ce"></a><!-- doxytag: member="registers::fc_state" ref="a1864a58a4089bd5d72ba19730137c5ce" args="" -->
1169 12 alfik 
<div class="memitem">
1170 
<div class="memproto">
1171 
      <table class="memname">
1172 
        <tr>
1173 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a1864a58a4089bd5d72ba19730137c5ce">fc_state</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1174 12 alfik 
        </tr>
1175 
      </table>
1176 
</div>
1177 
<div class="memdoc">
1178 
 
1179 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01636">1636</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1180 12 alfik 
 
1181 
</div>
1182 
</div>
1183 16 alfik 
<a class="anchor" id="acfc96bc559a0660239cb6b8a8836b862"></a><!-- doxytag: member="registers::fault_address_state" ref="acfc96bc559a0660239cb6b8a8836b862" args="" -->
1184 12 alfik 
<div class="memitem">
1185 
<div class="memproto">
1186 
      <table class="memname">
1187 
        <tr>
1188 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#acfc96bc559a0660239cb6b8a8836b862">fault_address_state</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1189 12 alfik 
        </tr>
1190 
      </table>
1191 
</div>
1192 
<div class="memdoc">
1193 
 
1194 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01637">1637</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1195 12 alfik 
 
1196 
</div>
1197 
</div>
1198 16 alfik 
<a class="anchor" id="a10ef9845f594ecc956dc1b1c8cdef44e"></a><!-- doxytag: member="registers::interrupt_trap" ref="a10ef9845f594ecc956dc1b1c8cdef44e" args="" -->
1199 12 alfik 
<div class="memitem">
1200 
<div class="memproto">
1201 
      <table class="memname">
1202 
        <tr>
1203 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a10ef9845f594ecc956dc1b1c8cdef44e">interrupt_trap</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1204 12 alfik 
        </tr>
1205 
      </table>
1206 
</div>
1207 
<div class="memdoc">
1208 
 
1209 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01638">1638</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1210 12 alfik 
 
1211 
</div>
1212 
</div>
1213 16 alfik 
<a class="anchor" id="aa92eeffb2c5af01c413399dfb1f58b17"></a><!-- doxytag: member="registers::interrupt_mask" ref="aa92eeffb2c5af01c413399dfb1f58b17" args="" -->
1214 12 alfik 
<div class="memitem">
1215 
<div class="memproto">
1216 
      <table class="memname">
1217 
        <tr>
1218 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aa92eeffb2c5af01c413399dfb1f58b17">interrupt_mask</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1219 12 alfik 
        </tr>
1220 
      </table>
1221 
</div>
1222 
<div class="memdoc">
1223 
 
1224 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01639">1639</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1225 12 alfik 
 
1226 
</div>
1227 
</div>
1228 16 alfik 
<a class="anchor" id="a278b33a84015867a530ac4279331d570"></a><!-- doxytag: member="registers::decoder_trap" ref="a278b33a84015867a530ac4279331d570" args="" -->
1229 12 alfik 
<div class="memitem">
1230 
<div class="memproto">
1231 
      <table class="memname">
1232 
        <tr>
1233 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a278b33a84015867a530ac4279331d570">decoder_trap</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1234 12 alfik 
        </tr>
1235 
      </table>
1236 
</div>
1237 
<div class="memdoc">
1238 
 
1239 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01640">1640</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1240 12 alfik 
 
1241 
</div>
1242 
</div>
1243 16 alfik 
<a class="anchor" id="a6810e76be48010f9b34a91c27ddd636b"></a><!-- doxytag: member="registers::usp" ref="a6810e76be48010f9b34a91c27ddd636b" args="" -->
1244 12 alfik 
<div class="memitem">
1245 
<div class="memproto">
1246 
      <table class="memname">
1247 
        <tr>
1248 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a6810e76be48010f9b34a91c27ddd636b">usp</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1249 12 alfik 
        </tr>
1250 
      </table>
1251 
</div>
1252 
<div class="memdoc">
1253 
 
1254 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01642">1642</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1255 12 alfik 
 
1256 
</div>
1257 
</div>
1258 16 alfik 
<a class="anchor" id="a659bea909e94f7512c4311bcff473a5d"></a><!-- doxytag: member="registers::Dn_output" ref="a659bea909e94f7512c4311bcff473a5d" args="" -->
1259 12 alfik 
<div class="memitem">
1260 
<div class="memproto">
1261 
      <table class="memname">
1262 
        <tr>
1263 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a659bea909e94f7512c4311bcff473a5d">Dn_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1264 12 alfik 
        </tr>
1265 
      </table>
1266 
</div>
1267 
<div class="memdoc">
1268 
 
1269 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01643">1643</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1270 12 alfik 
 
1271 
</div>
1272 
</div>
1273 16 alfik 
<a class="anchor" id="a7fdc26691a005524667257529b1c1212"></a><!-- doxytag: member="registers::An_output" ref="a7fdc26691a005524667257529b1c1212" args="" -->
1274 12 alfik 
<div class="memitem">
1275 
<div class="memproto">
1276 
      <table class="memname">
1277 
        <tr>
1278 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a7fdc26691a005524667257529b1c1212">An_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1279 12 alfik 
        </tr>
1280 
      </table>
1281 
</div>
1282 
<div class="memdoc">
1283 
 
1284 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01644">1644</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1285 12 alfik 
 
1286 
</div>
1287 
</div>
1288 16 alfik 
<a class="anchor" id="a73f335a76d3869b20956c67a67ff8f6e"></a><!-- doxytag: member="registers::pc_change" ref="a73f335a76d3869b20956c67a67ff8f6e" args="" -->
1289 12 alfik 
<div class="memitem">
1290 
<div class="memproto">
1291 
      <table class="memname">
1292 
        <tr>
1293 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a73f335a76d3869b20956c67a67ff8f6e">pc_change</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
1294 12 alfik 
        </tr>
1295 
      </table>
1296 
</div>
1297 
<div class="memdoc">
1298 
 
1299 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01646">1646</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1300 12 alfik 
 
1301 
</div>
1302 
</div>
1303 16 alfik 
<a class="anchor" id="aa1a45d113f21dba8f82a93ddfe1d6409"></a><!-- doxytag: member="registers::ea_reg" ref="aa1a45d113f21dba8f82a93ddfe1d6409" args="" -->
1304 12 alfik 
<div class="memitem">
1305 
<div class="memproto">
1306 
      <table class="memname">
1307 
        <tr>
1308 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aa1a45d113f21dba8f82a93ddfe1d6409">ea_reg</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
1309 12 alfik 
        </tr>
1310 
      </table>
1311 
</div>
1312 
<div class="memdoc">
1313 
 
1314 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01648">1648</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1315 12 alfik 
 
1316 
</div>
1317 
</div>
1318 16 alfik 
<a class="anchor" id="ae09341fa22dc0b4675dc02dc4a5fb918"></a><!-- doxytag: member="registers::ea_reg_control" ref="ae09341fa22dc0b4675dc02dc4a5fb918" args="" -->
1319 12 alfik 
<div class="memitem">
1320 
<div class="memproto">
1321 
      <table class="memname">
1322 
        <tr>
1323 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#ae09341fa22dc0b4675dc02dc4a5fb918">ea_reg_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1324 12 alfik 
        </tr>
1325 
      </table>
1326 
</div>
1327 
<div class="memdoc">
1328 
 
1329 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01649">1649</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1330 12 alfik 
 
1331 
</div>
1332 
</div>
1333 16 alfik 
<a class="anchor" id="a2d43cbef77f8243106b33e68a592dcef"></a><!-- doxytag: member="registers::ea_mod" ref="a2d43cbef77f8243106b33e68a592dcef" args="" -->
1334 12 alfik 
<div class="memitem">
1335 
<div class="memproto">
1336 
      <table class="memname">
1337 
        <tr>
1338 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a2d43cbef77f8243106b33e68a592dcef">ea_mod</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
1339 12 alfik 
        </tr>
1340 
      </table>
1341 
</div>
1342 
<div class="memdoc">
1343 
 
1344 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01651">1651</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1345 12 alfik 
 
1346 
</div>
1347 
</div>
1348 16 alfik 
<a class="anchor" id="af6205981eadd3ee1e9fa193f04b6a893"></a><!-- doxytag: member="registers::ea_mod_control" ref="af6205981eadd3ee1e9fa193f04b6a893" args="" -->
1349 12 alfik 
<div class="memitem">
1350 
<div class="memproto">
1351 
      <table class="memname">
1352 
        <tr>
1353 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#af6205981eadd3ee1e9fa193f04b6a893">ea_mod_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1354 12 alfik 
        </tr>
1355 
      </table>
1356 
</div>
1357 
<div class="memdoc">
1358 
 
1359 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01652">1652</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1360 12 alfik 
 
1361 
</div>
1362 
</div>
1363 16 alfik 
<a class="anchor" id="a34f0e8ea4d6f79a3c8cf7e3ba129ea58"></a><!-- doxytag: member="registers::ea_type" ref="a34f0e8ea4d6f79a3c8cf7e3ba129ea58" args="" -->
1364 12 alfik 
<div class="memitem">
1365 
<div class="memproto">
1366 
      <table class="memname">
1367 
        <tr>
1368 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a34f0e8ea4d6f79a3c8cf7e3ba129ea58">ea_type</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
1369 12 alfik 
        </tr>
1370 
      </table>
1371 
</div>
1372 
<div class="memdoc">
1373 
 
1374 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01654">1654</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1375 12 alfik 
 
1376 
</div>
1377 
</div>
1378 16 alfik 
<a class="anchor" id="aa22fa504627eea9bff308c3358ef9240"></a><!-- doxytag: member="registers::ea_type_control" ref="aa22fa504627eea9bff308c3358ef9240" args="" -->
1379 12 alfik 
<div class="memitem">
1380 
<div class="memproto">
1381 
      <table class="memname">
1382 
        <tr>
1383 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#aa22fa504627eea9bff308c3358ef9240">ea_type_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
1384 12 alfik 
        </tr>
1385 
      </table>
1386 
</div>
1387 
<div class="memdoc">
1388 
 
1389 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01655">1655</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1390 12 alfik 
 
1391 
</div>
1392 
</div>
1393 16 alfik 
<a class="anchor" id="a3b18ddbc3e465c4baf391903b10bb446"></a><!-- doxytag: member="registers::operand1" ref="a3b18ddbc3e465c4baf391903b10bb446" args="" -->
1394 12 alfik 
<div class="memitem">
1395 
<div class="memproto">
1396 
      <table class="memname">
1397 
        <tr>
1398 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#a3b18ddbc3e465c4baf391903b10bb446">operand1</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
1399 12 alfik 
        </tr>
1400 
      </table>
1401 
</div>
1402 
<div class="memdoc">
1403 
 
1404 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01658">1658</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1405 12 alfik 
 
1406 
</div>
1407 
</div>
1408 16 alfik 
<a class="anchor" id="af160a45a0b3cd7794efb7fea1ed60526"></a><!-- doxytag: member="registers::pc_valid" ref="af160a45a0b3cd7794efb7fea1ed60526" args="reg[31:0]" -->
1409 12 alfik 
<div class="memitem">
1410 
<div class="memproto">
1411 
      <table class="memname">
1412 
        <tr>
1413 16 alfik 
          <td class="memname"><span class="stringliteral"><a class="el" href="classregisters.html#af160a45a0b3cd7794efb7fea1ed60526">pc_valid</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[31:0]]</code></td>
1414 12 alfik 
        </tr>
1415 
      </table>
1416 
</div>
1417 
<div class="memdoc">
1418 
 
1419 16 alfik 
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l01743">1743</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
1420 12 alfik 
 
1421 
</div>
1422 
</div>
1423 
<hr/>The documentation for this class was generated from the following file:<ul>
1424 
<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
1425 
</ul>
1426 
</div>
1427 16 alfik 
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 22:20:15 for ao68000 by&#160;
1428 12 alfik 
<a href="http://www.doxygen.org/index.html">
1429 
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
1430 
</body>
1431 
</html>

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