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<h1>MC68000 notes </h1> </div>
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</div>
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<div class="contents">
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<div class="fragment"><pre class="fragment">Registers:
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| 32 |
|
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D0,D1,D2,D3,D4,D5,D6,D7 32-bit
|
| 33 |
|
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A0,A1,A2,A3,A4,A5,A6 32-bit
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| 34 |
|
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A7 USP 32-bit
|
| 35 |
|
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A7' SSP 32-bit
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| 36 |
|
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PC 32-bit
|
| 37 |
|
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CCR condition code reg, SR status register 8-bit User, 16-bit Supervisor
|
| 38 |
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| 39 |
|
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Address registers:
|
| 40 |
|
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base address registers, word and long-word operations,
|
| 41 |
|
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operations always affect 32-bits, word operations sign-extended
|
| 42 |
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All 16: index registers
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| 43 |
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| 44 |
|
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SR
|
| 45 |
|
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Condition Code Register:
|
| 46 |
|
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0: C Carry
|
| 47 |
|
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1: V Overflow
|
| 48 |
|
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2: Z Zero
|
| 49 |
|
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3: N Negative
|
| 50 |
|
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4: X Extend
|
| 51 |
|
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Status register:
|
| 52 |
|
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8-10: I Interrupt mask
|
| 53 |
|
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13: S Supervisor
|
| 54 |
|
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15: T Trace mode
|
| 55 |
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| 56 |
|
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MC68000 Addressing modes
|
| 57 |
|
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Number of extension words
|
| 58 |
|
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Register Direct Addressing
|
| 59 |
|
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Data Register Direct <ea> = Dn 0
|
| 60 |
|
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Address Register Direct <ea> = An 0
|
| 61 |
|
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Absolute Data Addressing
|
| 62 |
|
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Absolute Short <ea> = (Next Word) 1
|
| 63 |
|
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Absolute Long <ea> = (Next Two Words) 2
|
| 64 |
|
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Program Counter Relative Addressing
|
| 65 |
|
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Relative with Offset <ea> = (PC + d16) 1
|
| 66 |
|
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Relative with Index and Offset <ea> = (PC + Rn + d8) 1*
|
| 67 |
|
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Register Indirect Addressing
|
| 68 |
|
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Register Indirect <ea> = (An) 0
|
| 69 |
|
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Postincrement Register Indirect <ea> = (An), An <- An + N 0
|
| 70 |
|
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Predecrement Register Indirect An <- An–N, <ea> = (An) 0
|
| 71 |
|
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Register Indirect with Offset <ea> = (An + d16) 1
|
| 72 |
|
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Indexed Register Indirect with Offset <ea> = (An + Rn + d8) 1*
|
| 73 |
|
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Immediate Data Addressing
|
| 74 |
|
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Immediate DATA = Next Word(s) 1 or 2
|
| 75 |
|
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Quick Immediate Inherent Data 0
|
| 76 |
|
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Implied Addressing
|
| 77 |
|
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Implied Register <ea> = SR, USP, SSP, PC 0
|
| 78 |
|
|
|
| 79 |
|
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N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and
|
| 80 |
|
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the operand size is byte, N = 2 to keep the stack pointer on a word
|
| 81 |
|
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boundary.
|
| 82 |
|
|
|
| 83 |
|
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1*: format of brief extension word
|
| 84 |
|
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Data/Address(1 bit) Rn(3 bits) word/long(1 bit) 000 d8(8 bits)
|
| 85 |
|
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word/long: size of sign-extended index register
|
| 86 |
|
|
|
| 87 |
|
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Exceptions
|
| 88 |
|
|
|
| 89 |
|
|
1 Reset: Initial PC (Supervisor Program Space)
|
| 90 |
|
|
|
| 91 |
|
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2 Bus Error From external logic
|
| 92 |
|
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3 Address Error Odd address fetch
|
| 93 |
|
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4 Illegal Instruction $4AFA, $4AFB, $4AFC
|
| 94 |
|
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5 Zero Divide
|
| 95 |
|
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6 CHK Instruction Trap check bounds
|
| 96 |
|
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7 TRAPV Instruction Trap overflow
|
| 97 |
|
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8 Privilege Violation
|
| 98 |
|
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9 Trace
|
| 99 |
|
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10 Line 1010 Emulator Illegal instruction
|
| 100 |
|
|
11 Line 1111 Emulator Illegal instruction
|
| 101 |
|
|
12-14 RESERVED
|
| 102 |
|
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15 Uninitialized Interrupt Vector Default for uninitialized ext hw
|
| 103 |
|
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16-23 RESERVED
|
| 104 |
|
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24 Spurious Interrupt Bus error while int ack cycle
|
| 105 |
|
|
25 Level 1 Interrupt Autovector
|
| 106 |
|
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26 Level 2 Interrupt Autovector
|
| 107 |
|
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27 Level 3 Interrupt Autovector
|
| 108 |
|
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28 Level 4 Interrupt Autovector
|
| 109 |
|
|
29 Level 5 Interrupt Autovector
|
| 110 |
|
|
30 Level 6 Interrupt Autovector
|
| 111 |
|
|
31 Level 7 Interrupt Autovector
|
| 112 |
|
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32-47 Trap Instruction Vectors Trap instruction
|
| 113 |
|
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48-63 RESERVED
|
| 114 |
|
|
64-255 User Interrupt Vectors
|
| 115 |
|
|
|
| 116 |
|
|
Ack cycle: DACK + vector number, VPA, AVEC, BERR
|
| 117 |
|
|
|
| 118 |
|
|
Privilege violations: PC address current
|
| 119 |
|
|
AND Immediate to SR
|
| 120 |
|
|
EOR Immediate to SR
|
| 121 |
|
|
OR Immediate to SR
|
| 122 |
|
|
MOVE to SR?
|
| 123 |
|
|
MOVE USP
|
| 124 |
|
|
RESET
|
| 125 |
|
|
RTE
|
| 126 |
|
|
STOP
|
| 127 |
|
|
|
| 128 |
|
|
Tracing
|
| 129 |
|
|
Not: when interrupt, illegal, privileged, reset, bus error, address error
|
| 130 |
|
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Before: pending interrupt
|
| 131 |
|
|
After: instruction generated exception
|
| 132 |
|
|
|
| 133 |
|
|
Stack Frame
|
| 134 |
|
|
Reset:
|
| 135 |
|
|
None
|
| 136 |
|
|
|
| 137 |
|
|
Bus/Address error:
|
| 138 |
|
|
00. reset, 01. address error, 02. bus error: immediate reaction: abort current bus cycle, abort instruction or exception processing
|
| 139 |
|
|
if bus error/address error while address error,bus error or reset: block processor
|
| 140 |
|
|
address error: access word or long operand or instruction from odd address
|
| 141 |
|
|
bus error: BERR
|
| 142 |
|
|
processing an instruction: normal state or in group 2 exception
|
| 143 |
|
|
not processing an instruction: group 0 or 1 exception
|
| 144 |
|
|
Stack frame:
|
| 145 |
|
|
Undefined 11 bits, Read/Write bit 4, Instruction/Not bit 3, Function code bits 2-0,
|
| 146 |
|
|
Access address 32 bits,
|
| 147 |
|
|
Instruction register 16 bits,
|
| 148 |
|
|
Status register 16 bits,
|
| 149 |
|
|
Program counter 32 bits
|
| 150 |
|
|
|
| 151 |
|
|
Rest:
|
| 152 |
|
|
Status register, Program counter
|
| 153 |
|
|
|
| 154 |
|
|
Processing sequence
|
| 155 |
|
|
From TRAP: 1 -> S-bit of SR; SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
|
| 156 |
|
|
From ILLEGAL: SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
|
| 157 |
|
|
Copy status register
|
| 158 |
|
|
Enter Supervisor mode
|
| 159 |
|
|
Turn off tracing
|
| 160 |
|
|
Reset, interrupt exceptions: update interrupt priority mask
|
| 161 |
|
|
Determine vector number
|
| 162 |
|
|
Save on stack using SSP
|
| 163 |
|
|
|
| 164 |
|
|
PC value in exceptions:
|
| 165 |
|
|
usualy: trap: trace: interrupt: with address of next instruction,
|
| 166 |
|
|
address and bus errors: advanced 2-10 bytes after first word of current instruction
|
| 167 |
|
|
privilege violation: illegal: address of first word of current instruction
|
| 168 |
|
|
|
| 169 |
|
|
|
| 170 |
|
|
Without:
|
| 171 |
|
|
- Function Codes
|
| 172 |
|
|
- Bus arbitration
|
| 173 |
|
|
- Synchronous 6800 bus cycles
|
| 174 |
|
|
|
| 175 |
|
|
|
| 176 |
|
|
Operation code map:
|
| 177 |
|
|
0000 Bit Manipulation/MOVEP/Immediate
|
| 178 |
|
|
0001 Move Byte
|
| 179 |
|
|
0010 Move Long
|
| 180 |
|
|
0011 Move Word
|
| 181 |
|
|
0100 Miscellaneous
|
| 182 |
|
|
0101 ADDQ/SUBQ/Scc/DBcc/TRAPc
|
| 183 |
|
|
0110 Bcc/BSR/BRA
|
| 184 |
|
|
0111 MOVEQ
|
| 185 |
|
|
1000 OR/DIV/SBCD
|
| 186 |
|
|
1001 SUB/SUBX
|
| 187 |
|
|
1010 (Unassigned, Reserved)
|
| 188 |
|
|
1011 CMP/EOR
|
| 189 |
|
|
1100 AND/MUL/ABCD/EXG
|
| 190 |
|
|
1101 ADD/ADDX
|
| 191 |
|
|
1110 Shift/Rotate/Bit Field
|
| 192 |
|
|
1111 Coprocessor Interface/MC68040 and CPU32 Extensions
|
| 193 |
|
|
|
| 194 |
|
|
|
| 195 |
|
|
*******************************************************************************************************************************************
|
| 196 |
|
|
*******************************************************************************************************************************************
|
| 197 |
|
|
*******************************************************************************************************************************************
|
| 198 |
|
|
|
| 199 |
|
|
|
| 200 |
|
|
*******************************************************************************************************************************************
|
| 201 |
|
|
* add, sub
|
| 202 |
|
|
*******************************************************************************************************************************************
|
| 203 |
|
|
*
|
| 204 |
|
|
ABCD Add Decimal with Extend
|
| 205 |
|
|
[SBCD Subtract Decimal with Extend]
|
| 206 |
|
|
Destination10 +[-] Source10 +[-] X -> Destination
|
| 207 |
|
|
Byte operation, packed BCD
|
| 208 |
|
|
CC: X=C set if decimal carry [borrow] else cleared; Z cleared if result nonzero else unchanged; N,V undefined
|
| 209 |
|
|
1100[1000] Ry dest(3 bits) 1 0000 R/M Rx source(3 bits)
|
| 210 |
|
|
R/M = 0 data registers, 1 = address registers predecrement: -(An)
|
| 211 |
|
|
*
|
| 212 |
|
|
ADD Add
|
| 213 |
|
|
[SUB Subtract]
|
| 214 |
|
|
Destination +[-] Source -> Destination
|
| 215 |
|
|
Byte, Word, Long
|
| 216 |
|
|
CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
|
| 217 |
|
|
N set if result negative else cleared
|
| 218 |
|
|
1101[1001] register(3 bits) opmode(3 bits) ea mode register (3,3 bits)
|
| 219 |
|
|
register: data reg
|
| 220 |
|
|
opmode: 000,001,010 byte,word,long: ea +[-] Dn -> Dn; 100, 101, 110 byte,word,long: Dn +[-] ea -> ea
|
| 221 |
|
|
ea source, all modes: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
|
| 222 |
|
|
(xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
|
| 223 |
|
|
ea dest, memory alter: (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
|
| 224 |
|
|
(xxx).W 111 000, (xxx).L 111 001
|
| 225 |
|
|
*
|
| 226 |
|
|
ADDA Add Address
|
| 227 |
|
|
[SUBA Subtract Address]
|
| 228 |
|
|
Destination +[-] Source -> Destination
|
| 229 |
|
|
Word, Long
|
| 230 |
|
|
CC: not affected
|
| 231 |
|
|
1101[1001] register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
|
| 232 |
|
|
register: destination An
|
| 233 |
|
|
opmode: 011 word operation sign extended to 32 bits; 111 long operation
|
| 234 |
|
|
ea source, all modes.
|
| 235 |
|
|
*
|
| 236 |
|
|
ADDI Add Immediate
|
| 237 |
|
|
[SUBI Subtract Immediate]
|
| 238 |
|
|
Destination +[-] Immediate data -> Destination
|
| 239 |
|
|
Byte, Word, Long
|
| 240 |
|
|
CC: same as ADD
|
| 241 |
|
|
0000 0110[0100] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
|
| 242 |
|
|
size: 00,01,10 byte,word,long
|
| 243 |
|
|
ea dest, data alter: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
|
| 244 |
|
|
(xxx).W 111 000, (xxx).L 111 001,
|
| 245 |
|
|
*
|
| 246 |
|
|
ADDQ Add Quick
|
| 247 |
|
|
[SUBQ Subtract Quick]
|
| 248 |
|
|
Destination +[-] Immediate data -> Destination
|
| 249 |
|
|
Byte, Word, Long
|
| 250 |
|
|
CC: same as ADD,ADDA; not affected when destiantion is An
|
| 251 |
|
|
0101 data(3 bits) 0[1] size(2 bits) ea mode register (3,3 bits)
|
| 252 |
|
|
data: immediate data: 0=8, 1=1, ..., 7=7
|
| 253 |
|
|
size: 00,01,10 byte,word,long
|
| 254 |
|
|
ea dest, alter: Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
|
| 255 |
|
|
(xxx).W 111 000, (xxx).L 111 001,
|
| 256 |
|
|
*
|
| 257 |
|
|
ADDX Add with Extend
|
| 258 |
|
|
[SUBX Subtract with Extend]
|
| 259 |
|
|
Destination +[-] Source +[-] X -> Destination
|
| 260 |
|
|
Byte, Word, Long
|
| 261 |
|
|
CC: X=C set if carry[borrow] else cleared; V set if overflow else cleared; Z cleared if nonzero else unchanged; N set if negative else cleared
|
| 262 |
|
|
1101[1001] Ry dest(3 bits) 1 size(2 bits) 00 R/M Rx source(3 bits)
|
| 263 |
|
|
R/M = 0 data registers, 1 = address registers predecrement: -(An)
|
| 264 |
|
|
size: 00,01,10 byte,word,long
|
| 265 |
|
|
|
| 266 |
|
|
*******************************************************************************************************************************************
|
| 267 |
|
|
* cmp
|
| 268 |
|
|
*******************************************************************************************************************************************
|
| 269 |
|
|
*
|
| 270 |
|
|
CMP Compare
|
| 271 |
|
|
Destination - Source -> CC
|
| 272 |
|
|
Byte, Word, Long
|
| 273 |
|
|
CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
|
| 274 |
|
|
1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
|
| 275 |
|
|
register: destination Dn
|
| 276 |
|
|
opmode: 000,001,010 byte,word,long: Dn - ea
|
| 277 |
|
|
ea source, all modes.
|
| 278 |
|
|
*
|
| 279 |
|
|
CMPA Compare Address
|
| 280 |
|
|
Destination - Source -> CC
|
| 281 |
|
|
CC: same as CMP
|
| 282 |
|
|
1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
|
| 283 |
|
|
register: destination An
|
| 284 |
|
|
opmode: 011 word operation sign extended to 32 bits; 111 long operation
|
| 285 |
|
|
ea source, all modes.
|
| 286 |
|
|
*
|
| 287 |
|
|
CMPI Compare Immediate
|
| 288 |
|
|
Destination - Immediate Data -> CC
|
| 289 |
|
|
Byte, Word, Long
|
| 290 |
|
|
CC: same as CMP
|
| 291 |
|
|
0000 1100 size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
|
| 292 |
|
|
size: 00,01,10 byte,word,long
|
| 293 |
|
|
ea dest, data alter.
|
| 294 |
|
|
*
|
| 295 |
|
|
CMPM Compare Memory to Memory
|
| 296 |
|
|
Destination - Source -> CC
|
| 297 |
|
|
Byte, Word, Long
|
| 298 |
|
|
CC: same as CMP
|
| 299 |
|
|
1011 Ax dest(3 bits) 1 size(2 bits) 00 1 Ay source(3 bits)
|
| 300 |
|
|
Ax dest, Ay source: postincrement: +(An)
|
| 301 |
|
|
size: 00,01,10 byte,word,long
|
| 302 |
|
|
|
| 303 |
|
|
*******************************************************************************************************************************************
|
| 304 |
|
|
* mul, div
|
| 305 |
|
|
*******************************************************************************************************************************************
|
| 306 |
|
|
*
|
| 307 |
|
|
MULS Signed Multiply
|
| 308 |
|
|
[MULU Unsigned Multiply]
|
| 309 |
|
|
Source x Destination -> Destination
|
| 310 |
|
|
Word operation: source and dest 16 bit lower order -> destination 32 bit
|
| 311 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
|
| 312 |
|
|
1100 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits)
|
| 313 |
|
|
ea source, data: Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
|
| 314 |
|
|
(xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
|
| 315 |
|
|
|
| 316 |
|
|
*
|
| 317 |
|
|
DIVS Signed Divide
|
| 318 |
|
|
[DIVU Unsigned Divide]
|
| 319 |
|
|
Destination / Source -> Destination
|
| 320 |
|
|
Word operation: dest 32 bits, source 16 bits -> 16 bit MSB remainder, 16 bit LSB quotient, sign of remainder = sign of dividend
|
| 321 |
|
|
CC: X not affected; C cleared; V set if overflow else if trap undefined else cleared;
|
| 322 |
|
|
Z set if quotient zero else if trap or overflow undefined else cleared;
|
| 323 |
|
|
Z set if quotient negative else if trap or overflow undefined else cleared;
|
| 324 |
|
|
1000 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits)
|
| 325 |
|
|
ea source, data.
|
| 326 |
|
|
|
| 327 |
|
|
Overflow: if quotient larger than a 16-bit signed integer.
|
| 328 |
|
|
Division by 0: trap.
|
| 329 |
|
|
If overflow detected: operands unaffected.
|
| 330 |
|
|
|
| 331 |
|
|
*******************************************************************************************************************************************
|
| 332 |
|
|
* ext, neg
|
| 333 |
|
|
*******************************************************************************************************************************************
|
| 334 |
|
|
*
|
| 335 |
|
|
EXT Sign Extend
|
| 336 |
|
|
Destination sign-extended -> Destination
|
| 337 |
|
|
Word, Long
|
| 338 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
|
| 339 |
|
|
0100 100 opmode(3 bits) 00 0 Dn dest(3 bits)
|
| 340 |
|
|
opmode: 010,011 byte to word, word to long
|
| 341 |
|
|
*
|
| 342 |
|
|
NEGX Negate with Extend
|
| 343 |
|
|
|
| 344 |
|
|
Byte, Word, Long
|
| 345 |
|
|
CC: X=C set if borrow else clear; V set if overflow else clear; Z set if nonzero else unchanged; N set if negative else clear
|
| 346 |
|
|
0100 0000 size(2 bits) ea mode register(3,3 bits)
|
| 347 |
|
|
size: 00,01,10 byte,word,long
|
| 348 |
|
|
ea dest, data alter.
|
| 349 |
|
|
*
|
| 350 |
|
|
NBCD Negate Decimal with Extend
|
| 351 |
|
|
|
| 352 |
|
|
Byte operation
|
| 353 |
|
|
CC: X=C set if decimal borrow else cleared; Z cleared if nonzero else unchanged; N,V undefined
|
| 354 |
|
|
0100 1000 00 ea mode register(3,3 bits)
|
| 355 |
|
|
ea dest, data alter.
|
| 356 |
|
|
*
|
| 357 |
|
|
NEG Negate
|
| 358 |
|
|
|
| 359 |
|
|
Byte, Word, Long
|
| 360 |
|
|
CC: X=C clear if zero else set; V set if overflow else clear; Z set if zero else clear; N set if negative else clear
|
| 361 |
|
|
0100 0100 size(2 bits) ea mode register(3,3 bits)
|
| 362 |
|
|
size: 00,01,10 byte,word,long
|
| 363 |
|
|
ea dest, data alter.
|
| 364 |
|
|
|
| 365 |
|
|
*******************************************************************************************************************************************
|
| 366 |
|
|
* and,eor,or,not
|
| 367 |
|
|
*******************************************************************************************************************************************
|
| 368 |
|
|
*
|
| 369 |
|
|
AND Logical AND
|
| 370 |
|
|
[OR Logical Inclusive-OR]
|
| 371 |
|
|
Source &[|] Destination -> Destination
|
| 372 |
|
|
Byte, Word, Long: not on An
|
| 373 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
|
| 374 |
|
|
1100[1000] Dn register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
|
| 375 |
|
|
opmode: 000,001,010 byte,word,long: ea & Dn -> Dn; 100,101,110 byte,word,long: Dn & ea -> ea
|
| 376 |
|
|
ea source, data.
|
| 377 |
|
|
ea dest, memory alter.
|
| 378 |
|
|
*
|
| 379 |
|
|
ANDI Logical AND Immediate
|
| 380 |
|
|
[EORI Logical Exclusive-OR Immediate]
|
| 381 |
|
|
[ORI Logical Inclusive-OR Immediate]
|
| 382 |
|
|
Immediate data &[^][|] Destination -> Destination
|
| 383 |
|
|
Byte, Word, Long
|
| 384 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
|
| 385 |
|
|
0000 0010[1010][0000] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
|
| 386 |
|
|
size: 00,01,10 byte,word,long
|
| 387 |
|
|
ea dest, data alter.
|
| 388 |
|
|
*
|
| 389 |
|
|
ANDI to CCR AND Immediate to Condition Code Register
|
| 390 |
|
|
[EORI to CCR Exclusive-OR Immediate to Condition Code Register]
|
| 391 |
|
|
[ORI to CCR Inclusive-OR Immediate to Condition Code Register]
|
| 392 |
|
|
Source &[^][|] CCR -> CCR
|
| 393 |
|
|
Byte operation
|
| 394 |
|
|
CC: result
|
| 395 |
|
|
0000 0010[1010][0000] 00 111 100; 0000 0000 data(8 bit)
|
| 396 |
|
|
*
|
| 397 |
|
|
ANDI to SR AND Immediate to Status Register/Privilege/
|
| 398 |
|
|
[EORI to SR Exclusive-OR Immediate to Status Register/Privilege/]
|
| 399 |
|
|
[ORI to SR Inclusive-OR Immediate to Status Register/Privilege/]
|
| 400 |
|
|
Source &[^][|] SR -> SR
|
| 401 |
|
|
Word operation
|
| 402 |
|
|
CC: result
|
| 403 |
|
|
0000 0010[1010][0000] 01 111 100; data(16 bit)
|
| 404 |
|
|
*
|
| 405 |
|
|
EOR Logical Exclusive-OR
|
| 406 |
|
|
Source ^ Destination -> Destination
|
| 407 |
|
|
Byte, Word, Long
|
| 408 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
|
| 409 |
|
|
1011 Dn source(3 bits) opmode(3 bits) ea mode register(3,3 bits)
|
| 410 |
|
|
opmode: 100,101,110 byte,word,long: ea ^ Dn -> ea
|
| 411 |
|
|
ea dest, data alter.
|
| 412 |
|
|
*
|
| 413 |
|
|
NOT Logical Complement
|
| 414 |
|
|
~ Destination -> Destination
|
| 415 |
|
|
Byte, Word, Long
|
| 416 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
|
| 417 |
|
|
0100 0110 size(2 bits) ea mode register(3,3 bits)
|
| 418 |
|
|
size: 00,01,10 byte,word,long
|
| 419 |
|
|
ea dest, data alter.
|
| 420 |
|
|
|
| 421 |
|
|
*******************************************************************************************************************************************
|
| 422 |
|
|
* shift,rotate
|
| 423 |
|
|
*******************************************************************************************************************************************
|
| 424 |
|
|
*
|
| 425 |
|
|
ASL, ASR Arithmetic Shift Left and Right
|
| 426 |
|
|
[LSL, LSR Logical Shift Left and Right]
|
| 427 |
|
|
[ROL, ROR Rotate Left and Right]
|
| 428 |
|
|
[ROXL, ROXR Rotate with Extend Left and Right]
|
| 429 |
|
|
Destination shifted[shifted][rotated][rotated with X] by count -> Destination
|
| 430 |
|
|
Byte, Word, Long, in memory: 1 bit shift[shift][rotate][rotate] and word
|
| 431 |
|
|
CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared;
|
| 432 |
|
|
Z set if zero else cleared; V set if MSB bit changed during shift else cleared[cleared][cleared][cleared];
|
| 433 |
|
|
C set to last bit, cleared if zero shift[same][same][set to X]
|
| 434 |
|
|
1110 count/register(3 bits) dr(1 bit) size(2 bits) i/r(1 bit) 00[01][11][10] Dn dest(3 bit)
|
| 435 |
|
|
i/r = 0 count/register=count: 0=8, 1=1, ..., 7=7; i/r = 0 count/register=register: modulo 64
|
| 436 |
|
|
dr = 0 right shift; dr = 1 left shift
|
| 437 |
|
|
size: 00,01,10 byte,word,long
|
| 438 |
|
|
1110 000[001][011][010] dr(1 bit) 11 ea mode register(3,3 bits)
|
| 439 |
|
|
dr = 0 right shift; dr = 1 left shift
|
| 440 |
|
|
ea dest: memory alter.
|
| 441 |
|
|
|
| 442 |
|
|
*******************************************************************************************************************************************
|
| 443 |
|
|
* move,clr,exg,swap
|
| 444 |
|
|
*******************************************************************************************************************************************
|
| 445 |
|
|
*
|
| 446 |
|
|
MOVE Move
|
| 447 |
|
|
Source -> Destination
|
| 448 |
|
|
Byte, Word, Long
|
| 449 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
|
| 450 |
|
|
00 size(2 bits) ea dest register mode(3,3 bits) ea source mode register(3,3 bits)
|
| 451 |
|
|
size: 01,11,10 byte,word,long
|
| 452 |
|
|
ea dest, data alter.
|
| 453 |
|
|
ea source, all modes.
|
| 454 |
|
|
*
|
| 455 |
|
|
MOVEA Move Address
|
| 456 |
|
|
Source -> Destination
|
| 457 |
|
|
Word, Long
|
| 458 |
|
|
CC: not affected
|
| 459 |
|
|
00 size(2 bits) An dest(3 bits) 0 01 ea source mode register(3,3 bits)
|
| 460 |
|
|
size: 11,10 word,long: word operands are sign extended
|
| 461 |
|
|
ea source, all modes.
|
| 462 |
|
|
*
|
| 463 |
|
|
MOVE to CCR Move to Condition Code Register
|
| 464 |
|
|
Source -> CC
|
| 465 |
|
|
Word operation: upper byte ignored
|
| 466 |
|
|
0100 0100 11 ea source mode register(3,3 bits)
|
| 467 |
|
|
ea source, data.
|
| 468 |
|
|
*
|
| 469 |
|
|
MOVE from SR Move from Status Register
|
| 470 |
|
|
SR -> Destination
|
| 471 |
|
|
Word operation
|
| 472 |
|
|
CC: not affected
|
| 473 |
|
|
0100 0000 11 ea dest mode register(3,3 bits)
|
| 474 |
|
|
ea dest, data alter.
|
| 475 |
|
|
*
|
| 476 |
|
|
MOVE to SR Move to Status Register/Privileged/
|
| 477 |
|
|
Source -> SR
|
| 478 |
|
|
Word operation
|
| 479 |
|
|
CC: result
|
| 480 |
|
|
0100 0110 11 ea source mode register(3,3 bits)
|
| 481 |
|
|
ea source, data.
|
| 482 |
|
|
*
|
| 483 |
|
|
MOVE USP Move User Stack Pointer/Privileged/
|
| 484 |
|
|
USP -> An; An -> USP
|
| 485 |
|
|
Long operation
|
| 486 |
|
|
CC: not affected
|
| 487 |
|
|
0100 1110 0110 dr(1 bit) An reg(3 bits)
|
| 488 |
|
|
dr: 0 An -> USP; 1 USP -> An
|
| 489 |
|
|
*
|
| 490 |
|
|
MOVEM Move Multiple Registers
|
| 491 |
|
|
Registers -> Destination; Source -> Registers
|
| 492 |
|
|
Word, Long: word operations to An or Dn are sign extended
|
| 493 |
|
|
CC: not affected
|
| 494 |
|
|
0100 1 dr(1 bit) 00 1 size(1 bit) ea mode register(3,3 bits); register list mask
|
| 495 |
|
|
dr: 0 register to memory; 1 memory to register
|
| 496 |
|
|
size: 0,1 word,long operation
|
| 497 |
|
|
ea dest: register to memory, control alter or predecrement available:
|
| 498 |
|
|
(An) 010, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
|
| 499 |
|
|
(xxx).W 111 000, (xxx).L 111 001,
|
| 500 |
|
|
ea source: memory to register, control or postincrement available:
|
| 501 |
|
|
(An) 010, (An)+ 011, (d16, An) 101, (d8, An, Xn) 110,
|
| 502 |
|
|
(xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011
|
| 503 |
|
|
list mask: control or postincrement: A7-A0, D7-D0; predecrement: D0-D7; A0-A7
|
| 504 |
|
|
*
|
| 505 |
|
|
MOVEP Move Peripheral
|
| 506 |
|
|
Source -> Destination
|
| 507 |
|
|
Word, Long
|
| 508 |
|
|
CC: not affected
|
| 509 |
|
|
0000 data reg(3 bits) opmode(3 bits) 00 1 address reg(3 bits); 16 bit displacement
|
| 510 |
|
|
opmode: 100,101 word,long: memory -> register; 110,111 word,long: register -> memory
|
| 511 |
|
|
address reg: (An, d16)
|
| 512 |
|
|
*
|
| 513 |
|
|
MOVEQ Move Quick
|
| 514 |
|
|
Immediate data -> Destination
|
| 515 |
|
|
Long operation; 8 bit data is sign extended to 32 bits
|
| 516 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
|
| 517 |
|
|
0111 Dn dest(3 bits) 0 data(8 bits)
|
| 518 |
|
|
*
|
| 519 |
|
|
CLR Clear
|
| 520 |
|
|
|
| 521 |
|
|
Byte, Word, Long
|
| 522 |
|
|
CC: X not affected; C cleared; V cleared; Z set; N cleared
|
| 523 |
|
|
0100 0010 size(2 bits) ea dest mode register(3,3 bits)
|
| 524 |
|
|
size: 00,01,10 byte,word,long
|
| 525 |
|
|
ea dest, data alter.
|
| 526 |
|
|
*
|
| 527 |
|
|
EXG Exchange Registers
|
| 528 |
|
|
Rx <-> Ry
|
| 529 |
|
|
Long operation
|
| 530 |
|
|
CC: not affected
|
| 531 |
|
|
1100 Rx reg(3 bits) 1 opmode(5 bits) Ry reg(3 bits)
|
| 532 |
|
|
Rx reg: if Dn <-> An always Dn
|
| 533 |
|
|
Ry reg: if Dn <-> An always An
|
| 534 |
|
|
opmode: 01000 data regs; 01001 address regs; 10001 mix regs
|
| 535 |
|
|
*
|
| 536 |
|
|
SWAP Swap Register Words
|
| 537 |
|
|
Reg 31-16 <-> Reg 15-0
|
| 538 |
|
|
Word operation
|
| 539 |
|
|
CC: X not affected; C cleared; V cleared; Z set if 32 bits are zero else cleared; N set if result MSB set else cleared
|
| 540 |
|
|
0100 1000 0100 0 reg(3 bits)
|
| 541 |
|
|
|
| 542 |
|
|
*******************************************************************************************************************************************
|
| 543 |
|
|
* branch,jump
|
| 544 |
|
|
*******************************************************************************************************************************************
|
| 545 |
|
|
*
|
| 546 |
|
|
Bcc Branch Conditionally
|
| 547 |
|
|
if condition PC + d8/d16 -> PC
|
| 548 |
|
|
Byte, Word
|
| 549 |
|
|
CC: not affected
|
| 550 |
|
|
0110 condition(4 bits) disp8(8 bit); 16 bit displacement if disp8 == 0
|
| 551 |
|
|
condition: high(!C & !Z) 0010, low or same(C | V) 0011,
|
| 552 |
|
|
carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
|
| 553 |
|
|
overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
|
| 554 |
|
|
greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V) 1101,
|
| 555 |
|
|
greater than(N & V & !Z | !N & !V & !Z) 1110, less or equal(Z | N & !V | !N & V) 1111
|
| 556 |
|
|
*
|
| 557 |
|
|
BRA Branch
|
| 558 |
|
|
if condition PC + d8/d16 -> PC
|
| 559 |
|
|
Byte, Word
|
| 560 |
|
|
CC: not affected
|
| 561 |
|
|
0110 0000 disp8(8 bit); 16 bit displacement if disp8 == 0
|
| 562 |
|
|
*
|
| 563 |
|
|
BSR Branch to Subroutine
|
| 564 |
|
|
SP -= 4; PC -> (SP); PC + d8/d16 -> PC
|
| 565 |
|
|
Byte, Word
|
| 566 |
|
|
CC: not affected
|
| 567 |
|
|
0110 0001 disp8(8 bit); 16 bit displacement if disp8 == 0
|
| 568 |
|
|
*
|
| 569 |
|
|
DBcc Test Condition, Decrement, and Branch
|
| 570 |
|
|
if !condition { Dn(lower order 16 bits) -= 1; if Dn != -1 then PC + d16 -> PC }
|
| 571 |
|
|
Word operation
|
| 572 |
|
|
CC: not affected
|
| 573 |
|
|
0101 condition(4 bits) 1100 1 Dn register(3 bits); 16 bit displacement
|
| 574 |
|
|
condition: true(1) 0000, false(0) 0001, high(!C & !Z) 0010, low or same(C | V) 0011,
|
| 575 |
|
|
carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
|
| 576 |
|
|
overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
|
| 577 |
|
|
greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V),
|
| 578 |
|
|
greater than(N & V & !Z | !N & !V & !Z), less or equal(Z | N & !V | !N & V) 1111
|
| 579 |
|
|
*
|
| 580 |
|
|
JMP Jump
|
| 581 |
|
|
Destination address -> PC
|
| 582 |
|
|
Unsized
|
| 583 |
|
|
CC: not affected
|
| 584 |
|
|
0100 1110 11 ea mode register(3,3 bits)
|
| 585 |
|
|
ea, control: (An) 010, (d16, An) 101, (d8, An, Xn) 110,
|
| 586 |
|
|
(xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011
|
| 587 |
|
|
*
|
| 588 |
|
|
JSR Jump to Subroutine
|
| 589 |
|
|
SP -= 4; PC -> (SP); Destination address -> PC
|
| 590 |
|
|
Unsized
|
| 591 |
|
|
CC: not affected
|
| 592 |
|
|
0100 1110 10 ea mode register(3,3 bits)
|
| 593 |
|
|
ea, control.
|
| 594 |
|
|
*
|
| 595 |
|
|
RTR Return and Restore
|
| 596 |
|
|
(SP) -> CC; SP += 2; (SP) -> PC; SP += 4
|
| 597 |
|
|
Unsized
|
| 598 |
|
|
CC: set from stack; supervisor bits unaffected
|
| 599 |
|
|
0100 1110 0111 0111
|
| 600 |
|
|
*
|
| 601 |
|
|
RTS Return from Subroutine
|
| 602 |
|
|
(SP) -> PC; SP += 4
|
| 603 |
|
|
Unsized
|
| 604 |
|
|
CC: not affected
|
| 605 |
|
|
0100 1110 0111 0101
|
| 606 |
|
|
|
| 607 |
|
|
*******************************************************************************************************************************************
|
| 608 |
|
|
* test bit,test,check
|
| 609 |
|
|
*******************************************************************************************************************************************
|
| 610 |
|
|
*
|
| 611 |
|
|
BCHG Test Bit and Change
|
| 612 |
|
|
[BCLR Test Bit and Clear]
|
| 613 |
|
|
[BSET Test Bit and Set]
|
| 614 |
|
|
[BTST Test Bit]
|
| 615 |
|
|
test( <number> of Destination ) -> Z; test( <number> of Destination )[0][1][nothing] -> <bit number> of Destination
|
| 616 |
|
|
Byte, Long
|
| 617 |
|
|
CC: X,N,V,C not affected; Z set if bit tested is zero else cleared
|
| 618 |
|
|
0000 Dn reg(3 bits) 101[110][111][100] ea mode register(3,3 bits)
|
| 619 |
|
|
Dn reg: bit number
|
| 620 |
|
|
ea dest, data alter.[same][same][data address]; Dn is long operation else byte operation
|
| 621 |
|
|
0000 1000 01[10][11][00] ea mode register(3,3 bits); 0000 0000 bit number(8 bits)
|
| 622 |
|
|
ea dest, data alter[same][same][data address]; Dn is long operation else byte operation
|
| 623 |
|
|
|
| 624 |
|
|
ea data address Dn 000, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
|
| 625 |
|
|
(xxx).W 111 000, (xxx).L 111 001, (d16, PC) 111 010, (d8, PC, Xn) 111 011
|
| 626 |
|
|
*
|
| 627 |
|
|
Scc Set Conditionally
|
| 628 |
|
|
if condition 1s -> Destination else 0s -> Destination
|
| 629 |
|
|
Byte operation
|
| 630 |
|
|
CC: not affected
|
| 631 |
|
|
0101 condition(4 bits) 11 ea mode register(3,3 bits)
|
| 632 |
|
|
condition: same as in DBcc
|
| 633 |
|
|
ea dest, data alter.
|
| 634 |
|
|
*
|
| 635 |
|
|
TAS Test Operand and Set/Read-modify-write bus operation/
|
| 636 |
|
|
Destination tested -> CC; 1 -> bit 7 of destination
|
| 637 |
|
|
Byte operation
|
| 638 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
|
| 639 |
|
|
0100 1010 11 ea mode register(3,3 bits)
|
| 640 |
|
|
ea operand, data alter.
|
| 641 |
|
|
*
|
| 642 |
|
|
TST Test Operand
|
| 643 |
|
|
Destination tested -> CC
|
| 644 |
|
|
Byte, Word, Long
|
| 645 |
|
|
CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
|
| 646 |
|
|
0100 1010 size(2 bits) ea mode register(3,3 bits)
|
| 647 |
|
|
size: 00,01,10 byte,word,long
|
| 648 |
|
|
ea operand, data alter.
|
| 649 |
|
|
*
|
| 650 |
|
|
CHK Check Register Against Bound
|
| 651 |
|
|
if Dn < 0 or Dn > Source then TRAP
|
| 652 |
|
|
Word operation
|
| 653 |
|
|
CC: X not affected; N set if Dn < 0; cleared if Dn > Source else undefined; C,V,Z udefined
|
| 654 |
|
|
0100 Dn reg(3 bits) size(2 bits) 0 ea mode register(3,3 bits)
|
| 655 |
|
|
size: 11 word
|
| 656 |
|
|
ea source, data.
|
| 657 |
|
|
|
| 658 |
|
|
*******************************************************************************************************************************************
|
| 659 |
|
|
* address,stack
|
| 660 |
|
|
*******************************************************************************************************************************************
|
| 661 |
|
|
*
|
| 662 |
|
|
LEA Load Effective Address
|
| 663 |
|
|
ea -> An
|
| 664 |
|
|
Long operation
|
| 665 |
|
|
CC: not affected
|
| 666 |
|
|
0100 An reg(3 bits) 1 11 ea mode register(3,3 bits)
|
| 667 |
|
|
ea, control.
|
| 668 |
|
|
*
|
| 669 |
|
|
PEA Push Effective Address
|
| 670 |
|
|
SP -= 4; ea -> (SP)
|
| 671 |
|
|
Long operation
|
| 672 |
|
|
CC: not affected
|
| 673 |
|
|
0100 1000 01 ea mode register(3,3 bits)
|
| 674 |
|
|
ea, control.
|
| 675 |
|
|
*
|
| 676 |
|
|
LINK Link and Allocate
|
| 677 |
|
|
SP -= 4; An -> (SP); SP -> An; SP + d16 -> SP
|
| 678 |
|
|
Word operation
|
| 679 |
|
|
CC: not affected
|
| 680 |
|
|
0100 1110 0101 0 An reg(3 bits); 16 bit displacement
|
| 681 |
|
|
*
|
| 682 |
|
|
UNLK Unlink
|
| 683 |
|
|
An -> SP; (SP) -> An; Sp += 4
|
| 684 |
|
|
Unsized
|
| 685 |
|
|
CC: not affected
|
| 686 |
|
|
0100 1110 0101 1 An reg(3 bits)
|
| 687 |
|
|
|
| 688 |
|
|
*******************************************************************************************************************************************
|
| 689 |
|
|
* exceptions
|
| 690 |
|
|
*******************************************************************************************************************************************
|
| 691 |
|
|
*
|
| 692 |
|
|
ILLEGAL Take Illegal Instruction Trap
|
| 693 |
|
|
SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
|
| 694 |
|
|
Unsized
|
| 695 |
|
|
CC: not affected
|
| 696 |
|
|
0100 1010 1111 1100
|
| 697 |
|
|
*
|
| 698 |
|
|
TRAP Trap
|
| 699 |
|
|
1 -> S-bit of SR; SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
|
| 700 |
|
|
Unsized
|
| 701 |
|
|
CC: not affected
|
| 702 |
|
|
0100 1110 0100 vector(4 bits)
|
| 703 |
|
|
*
|
| 704 |
|
|
TRAPV Trap on Overflow
|
| 705 |
|
|
if V then TRAP
|
| 706 |
|
|
Unsized
|
| 707 |
|
|
CC: not affected
|
| 708 |
|
|
0100 1110 0111 0110
|
| 709 |
|
|
*
|
| 710 |
|
|
RTE Return from Exception/Privileged/
|
| 711 |
|
|
if S-bit set in SR then { (SP) -> SR; SP += 2; (SP) -> PC; SP += 4; restore state and dealocate rest of stack according to (SP) } else TRAP
|
| 712 |
|
|
Unsized
|
| 713 |
|
|
CC: set from stack
|
| 714 |
|
|
0100 1110 0111 0011
|
| 715 |
|
|
|
| 716 |
|
|
*******************************************************************************************************************************************
|
| 717 |
|
|
* control
|
| 718 |
|
|
*******************************************************************************************************************************************
|
| 719 |
|
|
*
|
| 720 |
|
|
NOP No Operation
|
| 721 |
|
|
None
|
| 722 |
|
|
Unsized
|
| 723 |
|
|
CC: not affected
|
| 724 |
|
|
0100 1110 0111 0001
|
| 725 |
|
|
*
|
| 726 |
|
|
RESET Reset External Devices/Privileged/
|
| 727 |
|
|
if S-bit set in SR then { assert !RESET line for 124 clock cycles } else TRAP
|
| 728 |
|
|
Unsized
|
| 729 |
|
|
CC: not affected
|
| 730 |
|
|
0100 1110 0111 0000
|
| 731 |
|
|
*
|
| 732 |
|
|
STOP Stop/Privileged/
|
| 733 |
|
|
if S-bit set in SR then { immediate data -> SR; STOP } else TRAP
|
| 734 |
|
|
Unsized
|
| 735 |
|
|
CC: set according to immediate data
|
| 736 |
|
|
0100 1110 0111 0010; 16 bit immediate data
|
| 737 |
|
|
|
| 738 |
|
|
Resume when trace, interrupt or rest.
|
| 739 |
|
|
|
| 740 |
|
|
*******************************************************************************************************************************************
|
| 741 |
|
|
*******************************************************************************************************************************************
|
| 742 |
|
|
*******************************************************************************************************************************************
|
| 743 |
|
|
|
| 744 |
|
|
0000 0010[1010][0000] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
|
| 745 |
|
|
ANDI,EORI,ORI
|
| 746 |
|
|
|
| 747 |
|
|
0000 0010[1010][0000] 00 111 100; 0000 0000 data(8 bit) ANDI to CCR,EORI to CCR,ORI to CCR
|
| 748 |
|
|
0000 0010[1010][0000] 01 111 100; data(16 bit) ANDI to SR,EORI to SR,ORI to SR
|
| 749 |
|
|
|
| 750 |
|
|
0000 0110[0100] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
|
| 751 |
|
|
ADDI,SUBI
|
| 752 |
|
|
|
| 753 |
|
|
0000 1000 01[10][11][00] ea mode register(3,3 bits); 0000 0000 bit number(8 bits) BCHG,BCLR,BSET,BTST
|
| 754 |
|
|
|
| 755 |
|
|
0000 1100 size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
|
| 756 |
|
|
CMPI
|
| 757 |
|
|
|
| 758 |
|
|
0000 Dn reg(3 bits) 101[110][111][100] ea mode register(3,3 bits) BCHG,BCLR,BSET,BTST
|
| 759 |
|
|
|
| 760 |
|
|
0000 Dn reg(3 bits) opmode(3 bits) 001 address reg(3 bits); 16 bit displacement MOVEP
|
| 761 |
|
|
|
| 762 |
|
|
00 size(2 bits) ea dest register mode(3,3 bits) ea source mode register(3,3 bits) MOVE
|
| 763 |
|
|
00 size(2 bits) An dest(3 bits) 001 ea source mode register(3,3 bits) MOVEA
|
| 764 |
|
|
|
| 765 |
|
|
if( 0000 000 0 ** !111100 ) ORI
|
| 766 |
|
|
if( 0000 000 0 00 111100 ) ORI to CCR
|
| 767 |
|
|
if( 0000 000 0 01 111100 ) ORI to SR
|
| 768 |
|
|
if( 0000 001 0 ** !111100 ) ANDI
|
| 769 |
|
|
if( 0000 001 0 00 111100 ) ANDI to CCR
|
| 770 |
|
|
if( 0000 001 0 01 111100 ) ANDI to SR
|
| 771 |
|
|
if( 0000 010 0 ) SUBI
|
| 772 |
|
|
if( 0000 011 0 ) ADDI
|
| 773 |
|
|
if( 0000 100 0 ) BCHG,BCLR,BSET,BTST
|
| 774 |
|
|
if( 0000 101 0 ** !111100 ) EORI
|
| 775 |
|
|
if( 0000 101 0 00 111100 ) EORI to CCR
|
| 776 |
|
|
if( 0000 101 0 01 111100 ) EORI to SR
|
| 777 |
|
|
if( 0000 110 0 ) CMPI
|
| 778 |
|
|
if( 0000 *** 1** !001 ) BCHG,BCLR,BSET,BTST
|
| 779 |
|
|
if( 0000 *** 1** 001 ) MOVEP
|
| 780 |
|
|
if( 00 !00 *** !001 ) MOVE
|
| 781 |
|
|
if( 00 !00 *** 001 ) MOVEA
|
| 782 |
|
|
|
| 783 |
|
|
*******************************************************************************************************************************************
|
| 784 |
|
|
|
| 785 |
|
|
0100 0000 size(2 bits) ea mode register(3,3 bits) NEGX
|
| 786 |
|
|
0100 0000 11 ea dest mode register(3,3 bits) MOVE FROM SR
|
| 787 |
|
|
|
| 788 |
|
|
0100 Dn reg(3 bits) 1 10 ea mode register(3,3 bits) CHK
|
| 789 |
|
|
0100 An reg(3 bits) 1 11 ea mode register(3,3 bits) LEA
|
| 790 |
|
|
|
| 791 |
|
|
0100 0010 size(2 bits) ea dest mode register(3,3 bits) CLR
|
| 792 |
|
|
|
| 793 |
|
|
0100 0100 size(2 bits) ea mode register(3,3 bits) NEG
|
| 794 |
|
|
0100 0100 11 ea source mode register(3,3 bits) MOVE TO CCR
|
| 795 |
|
|
|
| 796 |
|
|
0100 0110 size(2 bits) ea mode register(3,3 bits) NOT
|
| 797 |
|
|
0100 0110 11 ea source mode register(3,3 bits) MOVE TO SR
|
| 798 |
|
|
|
| 799 |
|
|
0100 1000 00 ea mode register(3,3 bits) NBCD
|
| 800 |
|
|
0100 1000 01 000 reg(3 bits) SWAP
|
| 801 |
|
|
0100 1000 01 ea mode register(3,3 bits) PEA
|
| 802 |
|
|
0100 100 opmode(3 bits) 000 Dn dest(3 bits) EXT
|
| 803 |
|
|
|
| 804 |
|
|
0100 1 dr(1 bit) 00 1 size(1 bit) ea mode register(3,3 bits); register list mask MOVEM
|
| 805 |
|
|
|
| 806 |
|
|
0100 1010 size(2 bits) ea mode register(3,3 bits) TST
|
| 807 |
|
|
0100 1010 11 ea mode register(3,3 bits) TAS
|
| 808 |
|
|
0100 1010 1111 1100 ILLEGAL
|
| 809 |
|
|
|
| 810 |
|
|
0100 1110 0100 vector(4 bits) TRAP
|
| 811 |
|
|
|
| 812 |
|
|
0100 1110 0101 0 An reg(3 bits); 16 bit displacement LNK
|
| 813 |
|
|
0100 1110 0101 1 An reg(3 bits) UNLK
|
| 814 |
|
|
|
| 815 |
|
|
0100 1110 0110 dr(1 bit) An reg(3 bits) MOVE USP
|
| 816 |
|
|
|
| 817 |
|
|
0100 1110 0111 0000 RESET
|
| 818 |
|
|
0100 1110 0111 0001 NOP
|
| 819 |
|
|
0100 1110 0111 0010 STOP
|
| 820 |
|
|
0100 1110 0111 0011 RTE
|
| 821 |
|
|
0100 1110 0111 0101 RTS
|
| 822 |
|
|
0100 1110 0111 0110 TRAPV
|
| 823 |
|
|
0100 1110 0111 0111 RTR
|
| 824 |
|
|
|
| 825 |
|
|
0100 1110 10 ea mode register(3,3 bits) JSR
|
| 826 |
|
|
0100 1110 11 ea mode register(3,3 bits) JMP
|
| 827 |
|
|
|
| 828 |
|
|
if( 0100 0000 00|01|10 ) NEGX
|
| 829 |
|
|
if( 0100 0000 11 ) MOVE FROM SR
|
| 830 |
|
|
if( 0100 ***1 10 ) CHK
|
| 831 |
|
|
if( 0100 ***1 11 ) LEA
|
| 832 |
|
|
if( 0100 0010 ) CLR
|
| 833 |
|
|
if( 0100 0100 00|01|10 ) NEG
|
| 834 |
|
|
if( 0100 0100 11 ) MOVE TO CCR
|
| 835 |
|
|
if( 0100 0110 00|01|10 ) NOT
|
| 836 |
|
|
if( 0100 0110 11 ) MOVE TO SR
|
| 837 |
|
|
if( 0100 1000 00 ) NBCD
|
| 838 |
|
|
if( 0100 1000 01 000 ) SWAP
|
| 839 |
|
|
if( 0100 1000 01 !000 ) PEA
|
| 840 |
|
|
if( 0100 1000 1* 000 ) EXT
|
| 841 |
|
|
if( 0100 1*00 1* !000 ) MOVEM
|
| 842 |
|
|
if( 0100 1010 00|01|10 ) TST
|
| 843 |
|
|
if( 0100 1010 11 !111100 ) TAS
|
| 844 |
|
|
if( 0100 1010 11 111100 ) ILLEGAL
|
| 845 |
|
|
if( 0100 1110 0100 ) TRAP
|
| 846 |
|
|
if( 0100 1110 0101 0 ) LNK
|
| 847 |
|
|
if( 0100 1110 0101 1 ) ULNK
|
| 848 |
|
|
if( 0100 1110 0110 ) MOVE USP
|
| 849 |
|
|
if( 0100 1110 0111 0000 ) RESET
|
| 850 |
|
|
if( 0100 1110 0111 0001 ) NOP
|
| 851 |
|
|
if( 0100 1110 0111 0010 ) STOP
|
| 852 |
|
|
if( 0100 1110 0111 0011 ) RTE
|
| 853 |
|
|
if( 0100 1110 0111 0101 ) RTS
|
| 854 |
|
|
if( 0100 1110 0111 0110 ) TRAPV
|
| 855 |
|
|
if( 0100 1110 0111 0111 ) RTR
|
| 856 |
|
|
if( 0100 1110 10 ) JSR
|
| 857 |
|
|
if( 0100 1110 11 ) JMP
|
| 858 |
|
|
|
| 859 |
|
|
*******************************************************************************************************************************************
|
| 860 |
|
|
|
| 861 |
|
|
0101 data(3 bits) 0[1] size(2 bits) ea mode register (3,3 bits) ADDQ,SUBQ
|
| 862 |
|
|
0101 condition(4 bits) 11 ea mode register(3,3 bits) Scc
|
| 863 |
|
|
0101 condition(4 bits) 11 001 Dn register(3 bits); 16 bit displacement DBcc
|
| 864 |
|
|
|
| 865 |
|
|
if( 0101 *** 0 !11 ) ADDQ
|
| 866 |
|
|
if( 0101 *** 1 !11 ) SUBQ
|
| 867 |
|
|
if( 0101 *** * 11 !001 ) Scc
|
| 868 |
|
|
if( 0101 *** * 11 001 ) DBcc
|
| 869 |
|
|
|
| 870 |
|
|
*******************************************************************************************************************************************
|
| 871 |
|
|
|
| 872 |
|
|
0110 0000 disp8(8 bit); 16 bit displacement if disp8 == 0 BRA
|
| 873 |
|
|
0110 0001 disp8(8 bit); 16 bit displacement if disp8 == 0 BSR
|
| 874 |
|
|
0110 condition(4 bits) disp8(8 bit); 16 bit displacement if disp8 == 0 Bcc
|
| 875 |
|
|
|
| 876 |
|
|
if( 0110 0000 ) BRA
|
| 877 |
|
|
if( 0110 0001 ) BSR
|
| 878 |
|
|
if( 0110 !000 ) Bcc
|
| 879 |
|
|
|
| 880 |
|
|
*******************************************************************************************************************************************
|
| 881 |
|
|
|
| 882 |
|
|
0111 Dn dest(3 bits) 0 data(8 bits) MOVEQ
|
| 883 |
|
|
|
| 884 |
|
|
*******************************************************************************************************************************************
|
| 885 |
|
|
|
| 886 |
|
|
1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits) CMP
|
| 887 |
|
|
|
| 888 |
|
|
1011 Dn source(3 bits) opmode(3 bits) ea mode register(3,3 bits) EOR
|
| 889 |
|
|
1011 Ax dest(3 bits) 1 size(2 bits) 001 Ay source(3 bits) CMPM
|
| 890 |
|
|
|
| 891 |
|
|
1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits) CMPA
|
| 892 |
|
|
|
| 893 |
|
|
if( 1011 *** 000|001|010 ) CMP
|
| 894 |
|
|
if( 1011 *** 100|101|110 001 ) CMPM
|
| 895 |
|
|
if( 1011 *** 100|101|110 !001 ) EOR
|
| 896 |
|
|
if( 1011 *** 011|111 ) CMPA
|
| 897 |
|
|
|
| 898 |
|
|
*******************************************************************************************************************************************
|
| 899 |
|
|
|
| 900 |
|
|
1000 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits) DIVS,DIVU
|
| 901 |
|
|
|
| 902 |
|
|
1100[1000] Ry dest(3 bits) 1 0000 R/M Rx source(3 bits) ABCD,SBCD
|
| 903 |
|
|
1100[1000] Dn register(3 bits) opmode(3 bits) ea mode register(3,3 bits) AND,OR
|
| 904 |
|
|
|
| 905 |
|
|
1100 Rx reg(3 bits) 1 opmode(5 bits) Ry reg(3 bits) EXG
|
| 906 |
|
|
1100 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits) MULS,MULU
|
| 907 |
|
|
|
| 908 |
|
|
if( 1000 *** 011 ) DIVU
|
| 909 |
|
|
if( 1000 *** 111 ) DIVS
|
| 910 |
|
|
if( 1000 *** 10000 ) SBCD
|
| 911 |
|
|
if( 1000 *** 000**|001**|010**|10001|10010|10011|101**|110** ) OR
|
| 912 |
|
|
|
| 913 |
|
|
if( 1100 *** 011 ) MULU
|
| 914 |
|
|
if( 1100 *** 111 ) MULS
|
| 915 |
|
|
if( 1100 *** 10000 ) ABCD
|
| 916 |
|
|
if( 1100 *** 000**|001**|010**|10001|10010|10011|10101|10110|10111|11001|11010|11011 ) AND
|
| 917 |
|
|
if( 1100 *** 10100|11000 ) EXG
|
| 918 |
|
|
|
| 919 |
|
|
*******************************************************************************************************************************************
|
| 920 |
|
|
|
| 921 |
|
|
1101[1001] register(3 bits) opmode(3 bits) ea mode register (3,3 bits) ADD,SUB
|
| 922 |
|
|
1101[1001] register(3 bits) opmode(3 bits) ea mode register(3,3 bits) ADDA,SUBA
|
| 923 |
|
|
1101[1001] Ry dest(3 bits) 1 size(2 bits) 00 R/M Rx source(3 bits) ADDX,SUBX
|
| 924 |
|
|
|
| 925 |
|
|
if( 1001 *** 000|001|010|10001|10010|10011|10101|10110|10111|11001|11010|11011 ) SUB
|
| 926 |
|
|
if( 1001 *** 011|111 ) SUBA
|
| 927 |
|
|
if( 1001 *** 10000|10100|11000 ) SUBX
|
| 928 |
|
|
if( 1101 *** 000|001|010|10001|10010|10011|10101|10110|10111|11001|11010|11011 ) ADD
|
| 929 |
|
|
if( 1101 *** 011|111 ) ADDA
|
| 930 |
|
|
if( 1101 *** 10000|10100|11000) ADDX
|
| 931 |
|
|
|
| 932 |
|
|
*******************************************************************************************************************************************
|
| 933 |
|
|
|
| 934 |
|
|
1110 count/register(3 bits) dr(1 bit) size(2 bits) i/r(1 bit) 00[01][11][10] Dn dest(3 bit) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
|
| 935 |
|
|
1110 000[001][011][010] dr(1 bit) 11 ea mode register(3,3 bits) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
|
| 936 |
|
|
|
| 937 |
|
|
if( 1110 *** * !11 ) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
|
| 938 |
|
|
if( 1110 *** * 11 ) ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
|
| 939 |
|
|
|
| 940 |
|
|
*******************************************************************************************************************************************
|
| 941 |
|
|
|
| 942 |
|
|
microcode
|
| 943 |
|
|
instruction: XXXX *** XXX
|
| 944 |
|
|
|
| 945 |
|
|
0000 *** 000 ORI,ORI to CCR,ANDI,ANDI to CCR,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,EORI to CCR,CMPI
|
| 946 |
|
|
0000 *** 001 ORI,ORI to SR,ANDI,ANDI to SR,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,EORI to SR,CMPI
|
| 947 |
|
|
0000 *** 010 ORI,ANDI,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,CMPI
|
| 948 |
|
|
0000 *** 011 ORI,ANDI,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,CMPI
|
| 949 |
|
|
0000 *** 100 BCHG,BCLR,BSET,BTST,MOVEP
|
| 950 |
|
|
0000 *** 101 BCHG,BCLR,BSET,BTST,MOVEP
|
| 951 |
|
|
0000 *** 110 BCHG,BCLR,BSET,BTST,MOVEP
|
| 952 |
|
|
0000 *** 111 BCHG,BCLR,BSET,BTST,MOVEP
|
| 953 |
|
|
|
| 954 |
|
|
0001 *** 000 MOVE
|
| 955 |
|
|
0001 *** 001 MOVEA
|
| 956 |
|
|
0001 *** 010 MOVE
|
| 957 |
|
|
0001 *** 011 MOVE
|
| 958 |
|
|
0001 *** 100 MOVE
|
| 959 |
|
|
0001 *** 101 MOVE
|
| 960 |
|
|
0001 *** 110 MOVE
|
| 961 |
|
|
0001 *** 111 MOVE
|
| 962 |
|
|
|
| 963 |
|
|
0010 *** 000 MOVE
|
| 964 |
|
|
0010 *** 001 MOVEA
|
| 965 |
|
|
0010 *** 010 MOVE
|
| 966 |
|
|
0010 *** 011 MOVE
|
| 967 |
|
|
0010 *** 100 MOVE
|
| 968 |
|
|
0010 *** 101 MOVE
|
| 969 |
|
|
0010 *** 110 MOVE
|
| 970 |
|
|
0010 *** 111 MOVE
|
| 971 |
|
|
|
| 972 |
|
|
0011 *** 000 MOVE
|
| 973 |
|
|
0011 *** 001 MOVEA
|
| 974 |
|
|
0011 *** 010 MOVE
|
| 975 |
|
|
0011 *** 011 MOVE
|
| 976 |
|
|
0011 *** 100 MOVE
|
| 977 |
|
|
0011 *** 101 MOVE
|
| 978 |
|
|
0011 *** 110 MOVE
|
| 979 |
|
|
0011 *** 111 MOVE
|
| 980 |
|
|
|
| 981 |
|
|
0100 *** 000 NEGX,CLR,NEG,NOT,NBCD,TST
|
| 982 |
|
|
0100 *** 001 NEGX,CLR,NEG,NOT,SWAP,PEA,TST,TRAP,LNK,ULNK,MOVE USP,RESET,NOP,STOP,RTE,RTS,TRAPV,RTR
|
| 983 |
|
|
0100 *** 010 NEGX,CLR,NEG,NOT,EXT,MOVEM,TST,JSR
|
| 984 |
|
|
0100 *** 011 MOVE FROM SR,CLR,MOVE TO CCR,MOVE TO SR,EXT,MOVEM,TAS,ILLEGAL,JMP
|
| 985 |
|
|
0100 *** 100 invalid
|
| 986 |
|
|
0100 *** 101 invalid
|
| 987 |
|
|
0100 *** 110 CHK
|
| 988 |
|
|
0100 *** 111 LEA
|
| 989 |
|
|
|
| 990 |
|
|
0101 *** 000 ADDQ
|
| 991 |
|
|
0101 *** 001 ADDQ
|
| 992 |
|
|
0101 *** 010 ADDQ
|
| 993 |
|
|
0101 *** 011 Scc,DBcc
|
| 994 |
|
|
0101 *** 100 SUBQ
|
| 995 |
|
|
0101 *** 101 SUBQ
|
| 996 |
|
|
0101 *** 110 SUBQ
|
| 997 |
|
|
0101 *** 111 Scc,DBcc
|
| 998 |
|
|
|
| 999 |
|
|
0110 *** 000 BRA,Bcc
|
| 1000 |
|
|
0110 *** 001 BRA,Bcc
|
| 1001 |
|
|
0110 *** 010 BRA,Bcc
|
| 1002 |
|
|
0110 *** 011 BRA,Bcc
|
| 1003 |
|
|
0110 *** 100 BSR,Bcc
|
| 1004 |
|
|
0110 *** 101 BSR,Bcc
|
| 1005 |
|
|
0110 *** 110 BSR,Bcc
|
| 1006 |
|
|
0110 *** 111 BSR,Bcc
|
| 1007 |
|
|
|
| 1008 |
|
|
0111 *** 000 MOVEQ
|
| 1009 |
|
|
0111 *** 001 MOVEQ
|
| 1010 |
|
|
0111 *** 010 MOVEQ
|
| 1011 |
|
|
0111 *** 011 MOVEQ
|
| 1012 |
|
|
0111 *** 100 invalid
|
| 1013 |
|
|
0111 *** 101 invalid
|
| 1014 |
|
|
0111 *** 110 invalid
|
| 1015 |
|
|
0111 *** 111 invalid
|
| 1016 |
|
|
|
| 1017 |
|
|
1000 *** 000 OR
|
| 1018 |
|
|
1000 *** 001 OR
|
| 1019 |
|
|
1000 *** 010 OR
|
| 1020 |
|
|
1000 *** 011 DIVU
|
| 1021 |
|
|
1000 *** 100 SBCD,OR
|
| 1022 |
|
|
1000 *** 101 OR
|
| 1023 |
|
|
1000 *** 110 OR
|
| 1024 |
|
|
1000 *** 111 DIVS
|
| 1025 |
|
|
|
| 1026 |
|
|
1001 *** 000 SUB
|
| 1027 |
|
|
1001 *** 001 SUB
|
| 1028 |
|
|
1001 *** 010 SUB
|
| 1029 |
|
|
1001 *** 011 SUBA
|
| 1030 |
|
|
1001 *** 100 SUB,SUBX
|
| 1031 |
|
|
1001 *** 101 SUB,SUBX
|
| 1032 |
|
|
1001 *** 110 SUB,SUBX
|
| 1033 |
|
|
1001 *** 111 SUBA
|
| 1034 |
|
|
|
| 1035 |
|
|
1010 *** 000 invalid
|
| 1036 |
|
|
1010 *** 001 invalid
|
| 1037 |
|
|
1010 *** 010 invalid
|
| 1038 |
|
|
1010 *** 011 invalid
|
| 1039 |
|
|
1010 *** 100 invalid
|
| 1040 |
|
|
1010 *** 101 invalid
|
| 1041 |
|
|
1010 *** 110 invalid
|
| 1042 |
|
|
1010 *** 111 invalid
|
| 1043 |
|
|
|
| 1044 |
|
|
1011 *** 000 CMP
|
| 1045 |
|
|
1011 *** 001 CMP
|
| 1046 |
|
|
1011 *** 010 CMP
|
| 1047 |
|
|
1011 *** 011 CMPA
|
| 1048 |
|
|
1011 *** 100 CMPM,EOR
|
| 1049 |
|
|
1011 *** 101 CMPM,EOR
|
| 1050 |
|
|
1011 *** 110 CMPM,EOR
|
| 1051 |
|
|
1011 *** 111 CMPA
|
| 1052 |
|
|
|
| 1053 |
|
|
1100 *** 000 AND
|
| 1054 |
|
|
1100 *** 001 AND
|
| 1055 |
|
|
1100 *** 010 AND
|
| 1056 |
|
|
1100 *** 011 MULU
|
| 1057 |
|
|
1100 *** 100 ABCD,AND
|
| 1058 |
|
|
1100 *** 101 EXG,AND
|
| 1059 |
|
|
1100 *** 110 EXG,AND
|
| 1060 |
|
|
1100 *** 111 MULS
|
| 1061 |
|
|
|
| 1062 |
|
|
1101 *** 000 ADD
|
| 1063 |
|
|
1101 *** 001 ADD
|
| 1064 |
|
|
1101 *** 010 ADD
|
| 1065 |
|
|
1101 *** 011 ADDA
|
| 1066 |
|
|
1101 *** 100 ADD,ADDX
|
| 1067 |
|
|
1101 *** 101 ADD,ADDX
|
| 1068 |
|
|
1101 *** 110 ADD,ADDX
|
| 1069 |
|
|
1101 *** 111 ADDA
|
| 1070 |
|
|
|
| 1071 |
|
|
1110 *** 000 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
|
| 1072 |
|
|
1110 *** 001 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
|
| 1073 |
|
|
1110 *** 010 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
|
| 1074 |
|
|
1110 *** 011 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR ea
|
| 1075 |
|
|
1110 *** 100 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
|
| 1076 |
|
|
1110 *** 101 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
|
| 1077 |
|
|
1110 *** 110 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
|
| 1078 |
|
|
1110 *** 111 ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR ea
|
| 1079 |
|
|
|
| 1080 |
|
|
1111 *** 000 invalid
|
| 1081 |
|
|
1111 *** 001 invalid
|
| 1082 |
|
|
1111 *** 010 invalid
|
| 1083 |
|
|
1111 *** 011 invalid
|
| 1084 |
|
|
1111 *** 100 invalid
|
| 1085 |
|
|
1111 *** 101 invalid
|
| 1086 |
|
|
1111 *** 110 invalid
|
| 1087 |
|
|
1111 *** 111 invalid
|
| 1088 |
|
|
|
| 1089 |
|
|
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
| 1090 |
|
|
Original MC68000 Ports:
|
| 1091 |
|
|
|
| 1092 |
|
|
Address bus: A23-A1, output
|
| 1093 |
|
|
Data bus: D15-D0, bidirectional
|
| 1094 |
|
|
|
| 1095 |
|
|
Address Strobe: output
|
| 1096 |
|
|
Read/Write: 0 - write, 1 - read
|
| 1097 |
|
|
Upper and Lower data strobes: output
|
| 1098 |
|
|
|
| 1099 |
|
|
Data transfer acknowlege: input
|
| 1100 |
|
|
|
| 1101 |
|
|
A,D,AS,R/W,UDS,LDS: all tri-state
|
| 1102 |
|
|
|
| 1103 |
|
|
BERR: input
|
| 1104 |
|
|
BERR: perform exception handling, while BERR asserted wait in Hi-Z
|
| 1105 |
|
|
BERR + HALT: retry bus cycle, HALT longer than BERR for at least 1 clock cycle, while HALT asserted wait in Hi-Z,
|
| 1106 |
|
|
not for read-modify-write, retry count not limited
|
| 1107 |
|
|
|
| 1108 |
|
|
|
| 1109 |
|
|
FC[2:0]: valid with Address Strobe
|
| 1110 |
|
|
|
| 1111 |
|
|
1 - user data
|
| 1112 |
|
|
2 - user program
|
| 1113 |
|
|
3 - undefined
|
| 1114 |
|
|
4 - undefined
|
| 1115 |
|
|
5 - supervisor data : all exception vector entries except reset
|
| 1116 |
|
|
6 - supervisor program : exception vector for reset
|
| 1117 |
|
|
7 - cpu space : interrupt acknowlege bus cycle
|
| 1118 |
|
|
|
| 1119 |
|
|
interrupt IPL[2:0]:
|
| 1120 |
|
|
assert IPL until processor signals interrupt acknowlege
|
| 1121 |
|
|
interrupt acknowlege bus cycle:
|
| 1122 |
|
|
FC: 7
|
| 1123 |
|
|
A23-A4: high, A3-A1: interrupt number output
|
| 1124 |
|
|
D15-D8 ignored, D7-D0 + DACK: vector number
|
| 1125 |
|
|
input VPA: autovector, complete 6800 read cycle: assert VMA
|
| 1126 |
|
|
input BERR: spurious interrupt
|
| 1127 |
|
|
|
| 1128 |
|
|
HALT, RESET: inout
|
| 1129 |
|
|
input HALT + RESET: processor reset
|
| 1130 |
|
|
output RESET: RESET opcode: reset external devices
|
| 1131 |
|
|
output HALT: processor blocked
|
| 1132 |
|
|
input HALT: stop bus activity after current bus cycle, Hi-Z all three-state lines, bus arbitration as usual
|
| 1133 |
|
|
|
| 1134 |
|
|
|
| 1135 |
|
|
bus request: input, at any time
|
| 1136 |
|
|
bus grant: output, bus is to be released after current cycle
|
| 1137 |
|
|
bus grant acknowlege: input, bus in use by external device
|
| 1138 |
|
|
|
| 1139 |
|
|
E: clock: output, 6 clocks low, 4 clocks high
|
| 1140 |
|
|
Valid Peripheral Address: input, use autovector in interrupt acknowlege cycle, device is 6800 type: synchronize data on E
|
| 1141 |
|
|
Valid Memory Address: output, memory address valid and processor synchronized on E
|
| 1142 |
|
|
|
| 1143 |
|
|
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
| 1144 |
|
|
Backup
|
| 1145 |
|
|
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
| 1146 |
|
|
|
| 1147 |
|
|
//----- flip_flop_registers
|
| 1148 |
|
|
//ir1,ir2:
|
| 1149 |
|
|
// required by: ANDI,EORI,ORI,ANDI to CCR,EORI to CCR,ORI to CCR,ANDI to SR,EORI to SR,ORI to SR,ADDI,SUBI
|
| 1150 |
|
|
|
| 1151 |
|
|
</pre></div> </div>
|
| 1152 |
16 |
alfik |
<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 22:20:15 for ao68000 by 
|
| 1153 |
12 |
alfik |
<a href="http://www.doxygen.org/index.html">
|
| 1154 |
|
|
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
|
| 1155 |
|
|
</body>
|
| 1156 |
|
|
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|
