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<title>ao68000: Operation</title>
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<li><a href="index.html"><span>Main Page</span></a></li>
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<div class="header">
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<div class="headertitle">
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<h1>Operation </h1> </div>
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</div>
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<div class="contents">
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core is designed to operate in a similar way as the original MC68000. The most import differences are:</p>
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<ul>
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<li>the core IO ports are compatible with the WISHBONE specification,</li>
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<li>the execution of instructions in the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> core is not cycle-exact with the original MC68000 and usually takes a few cycles longer.</li>
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</ul>
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<h3>Setting up the core</h3>
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core has an WISHBONE MASTER interface. All standard memory access bus cycles conform to the WISHBONE specification. These cycles include:</p>
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<ul>
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<li>instruction fetch,</li>
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<li>data read,</li>
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<li>data write.</li>
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</ul>
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<p>The cycles are either Single, Block or Read-Modify-Write (for the TAS instruction). When waiting to finish a bus cycle the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> reacts on the following input signals:</p>
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<ul>
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<li>ACK_I: the cycle is completed successfully,</li>
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<li>RTY_I: the cycle is immediately repeated, the processor does not continue its operation before the current bus cycle is finished. In case of the Read-Modify-Write cycle - only the current bus cycle is repeated: either the read or write.</li>
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<li>ERR_I: the cycle is terminated and a bus error is processed. In case of double bus error the processor enters the blocked state.</li>
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</ul>
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<p>There is also a special bus cycle: the interrupt acknowledge cycle. This cycle is a reaction on receiving a external interrupt from the ipl_i inputs. The processor only samples the ipl_i lines after processing an instruction, so the interrupt lines have to be asserted for some time before the core reacts. The interrupt acknowledge cycle is performed in the following way:</p>
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<ul>
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<li>ADR_O is set to { 27'b111_1111_1111_1111_1111_1111_1111, 3 bits indicating the interrupt priority level for this cycle },</li>
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<li>SEL_O is set to 4'b1111,</li>
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<li>fc_o is set to 3'b111 to indicate a CPU Cycle as in the original MC68000.</li>
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</ul>
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> reacts on the following signals when waiting to finish a interrupt acknowledge bus cycle:</p>
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<ul>
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<li>ACK_I: the cycle is completed successfully and the interrupt vector is read from DAT_I[7:0],</li>
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<li>RTY_I: the cycle is completed successfully and the processor generates a auto-vector internally,</li>
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<li>ERR_I: the cycle is terminated and the processor starts processing a spurious interrupt exception.</li>
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</ul>
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<p>Every bus cycle is supplemented with output tags:</p>
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<ul>
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<li>WISHBONE standard tags: SGL_O, BLK_O, RMW_O, CTI_O, BTE_O,</li>
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<li><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> custom tag: fc_o that operates like the Function Code of the original MC68000.</li>
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</ul>
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> core has two additional outputs that are used to indicate the state of the processor:</p>
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<ul>
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<li>reset_o is a external device reset signal. It is asserted when processing the RESET instruction. It is asserted for 124 bus cycles. After that the processor returns to normal instruction processing.</li>
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<li>blocked_o is an output that indicates that the processor is blocked after a double bus error. When this output line is asserted the processor is blocked and does not process any instructions. The only way to continue processing instructions is to reset the core.</li>
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</ul>
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<h3>Resetting the core</h3>
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> core is reset with a asynchronous reset_n input. After deasserting the signal, the core starts its standard startup sequence, which is similar to the one performed by the original MC68000:</p>
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<ul>
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<li>the value of the SSP register is read from address 0,</li>
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<li>the value of the PC is read from address 1.</li>
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</ul>
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<p>An identical sequence is performed when powering up the core for the first time.</p>
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<h3>Processor modes</h3>
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> core has two modes of operation - exactly like the original MC68000:</p>
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<ul>
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<li>Supervisor mode</li>
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<li>User mode.</li>
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</ul>
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<p>Performing a privileged instruction when running in user mode results in a privilege exception, just like in MC68000.</p>
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<h3>Processor states</h3>
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> core can be in one of the following states:</p>
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<ul>
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<li>instruction processing, which includes group 2 exception processing,</li>
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<li>group 0 and group 1 exception processing,</li>
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<li>external device reset state when processing the RESET instruction,</li>
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<li>blocked state after a double bus error. </li>
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</ul>
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</div>
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