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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<title>ao68000: IO Ports</title>
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<!-- Generated by Doxygen 1.7.2 -->
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    <ul class="tablist">
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      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
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      <li><a href="modules.html"><span>Modules</span></a></li>
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      <li><a href="annotated.html"><span>Design&#160;Unit&#160;List</span></a></li>
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  </div>
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</div>
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<div class="header">
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  <div class="headertitle">
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<h1>IO Ports </h1>  </div>
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</div>
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<div class="contents">
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<h3>WISHBONE IO Ports</h3>
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<table  width="100%">
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<caption align="bottom"><b>Table 1:</b> List of WISHBONE IO ports.</caption>
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<tr style="background: #CCCCCC; font-weight: bold;">
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<td>Port </td><td>Width </td><td>Direction </td><td>Description  </td></tr>
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<tr>
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<td>CLK_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Clock Input </p>
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  </td></tr>
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<tr>
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<td>reset_n </td><td>1 </td><td>Input </td><td><p>Asynchronous Reset Input </p>
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  </td></tr>
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<tr>
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<td>CYC_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Master Cycle Output </p>
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  </td></tr>
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<tr>
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<td>ADR_O </td><td>30 </td><td>Output </td><td><p>WISHBONE Master Address Output </p>
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  </td></tr>
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<tr>
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<td>DAT_O </td><td>32 </td><td>Output </td><td><p>WISHBONE Master Data Output </p>
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  </td></tr>
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<tr>
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<td>DAT_I </td><td>32 </td><td>Input </td><td><p>WISHBONE Master Data Input </p>
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  </td></tr>
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<tr>
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<td>SEL_O </td><td>4 </td><td>Output </td><td><p>WISHBONE Master Byte Select </p>
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  </td></tr>
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<tr>
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<td>STB_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Master Strobe Output </p>
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  </td></tr>
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<tr>
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<td>WE_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Master Write Enable Output </p>
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  </td></tr>
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<tr>
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<td>ACK_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Master Acknowledge Input:</p>
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<ul>
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<li>on normal cycle: acknowledge,</li>
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<li>on interrupt acknowledge cycle: external vector provided on DAT_I[7:0]. </li>
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</ul>
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  </td></tr>
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<tr>
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<td>ERR_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Master Error Input</p>
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<ul>
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<li>on normal cycle: bus error,</li>
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<li>on interrupt acknowledge cycle: spurious interrupt. </li>
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</ul>
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  </td></tr>
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<tr>
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<td>RTY_I </td><td>1 </td><td>Input </td><td><p>WISHBONE Master Retry Input</p>
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<ul>
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<li>on normal cycle: retry bus cycle,</li>
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<li>on interrupt acknowledge: use auto-vector. </li>
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</ul>
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  </td></tr>
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<tr>
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<td>SGL_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Single Bus Cycle. </p>
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  </td></tr>
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<tr>
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<td>BLK_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Block Bus Cycle. </p>
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  </td></tr>
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<tr>
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<td>RMW_O </td><td>1 </td><td>Output </td><td><p>WISHBONE Cycle Tag, TAG_TYPE: TGC_O, Read-Modify-Write Cycle. </p>
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  </td></tr>
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<tr>
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<td>CTI_O </td><td>3 </td><td>Output </td><td><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Cycle Type Identifier, Incrementing Bus Cycle or End-of-Burst Cycle. </p>
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  </td></tr>
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<tr>
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<td>BTE_O </td><td>2 </td><td>Output </td><td><p>WISHBONE Address Tag, TAG_TYPE: TGA_O, Burst Type Extension, always Linear Burst. </p>
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  </td></tr>
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<tr>
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<td>fc_o </td><td>3 </td><td>Output </td><td><p>Custom TAG_TYPE: TGC_O, Cycle Tag, Processor Function Code:</p>
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<ul>
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<li>1 - user data,</li>
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<li>2 - user program,</li>
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<li>5 - supervisor data : all exception vector entries except reset,</li>
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<li>6 - supervisor program : exception vector for reset,</li>
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<li>7 - cpu space: interrupt acknowledge. </li>
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</ul>
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  </td></tr>
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</table>
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<h3>Other IO Ports</h3>
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<table  width="100%">
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<caption align="bottom"><b>Table 2:</b> List of Other IO ports.</caption>
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<tr style="background: #CCCCCC; font-weight: bold;">
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<td>Port </td><td>Width </td><td>Direction </td><td>Description  </td></tr>
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<tr>
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<td>ipl_i </td><td>3 </td><td>Input </td><td><p>Interrupt Priority Level Interrupt acknowledge cycle:</p>
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<ul>
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<li>ACK_I: interrupt vector on DAT_I[7:0],</li>
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<li>ERR_I: spurious interrupt,</li>
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<li>RTY_I: auto-vector. </li>
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</ul>
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  </td></tr>
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<tr>
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<td>reset_o </td><td>1 </td><td>Output </td><td><p>External device reset. Output high when processing the RESET instruction. </p>
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  </td></tr>
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<tr>
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<td>blocked_o</td><td>1 </td><td>Output </td><td><p>Processor blocked indicator. The processor is blocked after a double bus error. </p>
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  </td></tr>
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</table>
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</div>
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