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<title>ao68000: Processor verification</title>
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<h1>Processor verification </h1> </div>
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<p>The <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> IP Core is verified with the WinUAE MC68000 software emulator. The verification is based on the idea that given the same contents of:</p>
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<ul>
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<li>every register in the processor,</li>
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<li>all memory locations that are read during execution,</li>
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</ul>
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<p>the result of execution, that is the contents of:</p>
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<ul>
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<li>every register in the processor,</li>
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<li>all memory locations written during execution,</li>
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</ul>
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<p>should be the same for the IP Core and the software emulator.</p>
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<h3>Verification procedure</h3>
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<p>The verification is performed in the following way:</p>
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<ul>
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<li>the WinUAE MC68000 software emulator is compiled. The sources of the emulator are located at: <code>./tests/compare_with_winuae/winuae/</code>. The compiled binary is located at: <code>./tmp/compare_with_winuae/winuae/ao</code>.</li>
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<li>the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> testbench is compiled. The sources of the testbench are located at: <code>./tests/compare_with_winuae/verilog/</code>. The compiled Icarus Verilog script is located at: <code>./tmp/compare_with_winuae/verilog/tb_ao68000</code>.</li>
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<li>Both of the above executable programs accept arguments that specify the values of:<ul>
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<li>memory locations that are read during execution,</li>
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<li>the contents of every register in the processor.</li>
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</ul>
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</li>
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<li>The result of executing both of the programs is the contents of:<ul>
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<li>memory locations written during execution,</li>
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<li>the contents of every register in the processor after execution.</li>
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</ul>
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</li>
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<li>The tool <code>./sw/ao68000_tool/</code> (<a class="el" href="page_tool.html">ao68000_tool documentation</a>) is used to run both of the executable programs and compare the result of execution. The tool is capable of executing multiple concurrent simulations in order to utilize current multicore processors.</li>
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</ul>
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<p>The makefile with instructions to perform the above operations is located at: <code>./Makefile</code>.</p>
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<h3>Requirements</h3>
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<ul>
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<li>Icarus Verilog simulator (<a href="http://www.icarus.com/eda/verilog/">http://www.icarus.com/eda/verilog/</a>) is required to compile the <code>tb_ao68000</code> testbench/wrapper,</li>
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<li>Access to Altera Quartus II instalation (directory eda/sim_lib/) is required to compile the <code>tb_ao68000</code> testbench/wrapper,</li>
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<li>GCC (<a href="http://gcc.gnu.org">http://gcc.gnu.org</a>) is required to compile the WinUAE MC68000 software emulator,</li>
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<li>Java SDK (<a href="http://java.sun.com">http://java.sun.com</a>) is required to compile the <code>ao68000_tool</code> (<a class="el" href="page_tool.html">ao68000_tool documentation</a>),</li>
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<li>Java runtime (<a href="http://java.sun.com">http://java.sun.com</a>) is required to run the <code>ao68000_tool</code> (<a class="el" href="page_tool.html">ao68000_tool documentation</a>). </li>
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</ul>
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</div>
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