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1 12 alfik
Registers:
2
D0,D1,D2,D3,D4,D5,D6,D7                     32-bit
3
A0,A1,A2,A3,A4,A5,A6                        32-bit
4
A7                               USP        32-bit
5
A7'                              SSP        32-bit
6
PC                                          32-bit
7
CCR condition code reg, SR status register  8-bit User, 16-bit Supervisor
8
 
9
Address registers:
10
base address registers, word and long-word operations,
11
operations always affect 32-bits, word operations sign-extended
12
All 16: index registers
13
 
14
SR
15
Condition Code Register:
16
0:      C Carry
17
1:      V Overflow
18
2:      Z Zero
19
3:      N Negative
20
4:      X Extend
21
Status register:
22
8-10:   I Interrupt mask
23
13:     S Supervisor
24
15:     T Trace mode
25
 
26
MC68000 Addressing modes
27
                                                                                        Number of extension words
28
Register Direct Addressing
29
     Data Register Direct                   = Dn                                    0
30
     Address Register Direct                = An                                    0
31
Absolute Data Addressing
32
     Absolute Short                         = (Next Word)                           1
33
     Absolute Long                          = (Next Two Words)                      2
34
Program Counter Relative Addressing
35
     Relative with Offset                   = (PC + d16)                            1
36
     Relative with Index and Offset         = (PC + Rn + d8)                        1*
37
Register Indirect Addressing
38
     Register Indirect                      = (An)                                  0
39
     Postincrement Register Indirect        = (An), An <- An + N                    0
40
     Predecrement Register Indirect        An <- An–N,  = (An)                      0
41
     Register Indirect with Offset          = (An + d16)                            1
42
     Indexed Register Indirect with Offset  = (An + Rn + d8)                        1*
43
Immediate Data Addressing
44
     Immediate                             DATA = Next Word(s)                          1 or 2
45
     Quick Immediate                       Inherent Data                                0
46
Implied Addressing
47
     Implied Register                       = SR, USP, SSP, PC                      0
48
 
49
N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and
50
   the operand size is byte, N = 2 to keep the stack pointer on a word
51
   boundary.
52
 
53
1*: format of brief extension word
54
Data/Address(1 bit) Rn(3 bits) word/long(1 bit) 000 d8(8 bits)
55
word/long: size of sign-extended index register
56
 
57
Exceptions
58
 
59
1       Reset: Initial PC               (Supervisor Program Space)
60
 
61
2       Bus Error                       From external logic
62
3       Address Error                   Odd address fetch
63
4       Illegal Instruction             $4AFA, $4AFB, $4AFC
64
5       Zero Divide
65
6       CHK Instruction                 Trap check bounds
66
7       TRAPV Instruction               Trap overflow
67
8       Privilege Violation
68
9       Trace
69
10      Line 1010 Emulator              Illegal instruction
70
11      Line 1111 Emulator              Illegal instruction
71
12-14   RESERVED
72
15      Uninitialized Interrupt Vector  Default for uninitialized ext hw
73
16-23   RESERVED
74
24      Spurious Interrupt              Bus error while int ack cycle
75
25      Level 1 Interrupt Autovector
76
26      Level 2 Interrupt Autovector
77
27      Level 3 Interrupt Autovector
78
28      Level 4 Interrupt Autovector
79
29      Level 5 Interrupt Autovector
80
30      Level 6 Interrupt Autovector
81
31      Level 7 Interrupt Autovector
82
32-47   Trap Instruction Vectors        Trap instruction
83
48-63   RESERVED
84
64-255  User Interrupt Vectors
85
 
86
Ack cycle: DACK + vector number, VPA, AVEC, BERR
87
 
88
Privilege violations:                   PC address current
89
AND Immediate to SR
90
EOR Immediate to SR
91
OR Immediate to SR
92
MOVE to SR?
93
MOVE USP
94
RESET
95
RTE
96
STOP
97
 
98
Tracing
99
Not: when interrupt, illegal, privileged, reset, bus error, address error
100
Before: pending interrupt
101
After: instruction generated exception
102
 
103
Stack Frame
104
Reset:
105
None
106
 
107
Bus/Address error:
108
00. reset, 01. address error, 02. bus error: immediate reaction: abort current bus cycle, abort instruction or exception processing
109
if bus error/address error while address error,bus error or reset: block processor
110
address error: access word or long operand or instruction from odd address
111
bus error: BERR
112
processing an instruction: normal state or in group 2 exception
113
not processing an instruction: group 0 or 1 exception
114
Stack frame:
115
Undefined 11 bits, Read/Write bit 4, Instruction/Not bit 3, Function code bits 2-0,
116
Access address 32 bits,
117
Instruction register 16 bits,
118
Status register 16 bits,
119
Program counter 32 bits
120
 
121
Rest:
122
Status register, Program counter
123
 
124
Processing sequence
125
From TRAP: 1 -> S-bit of SR; SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
126
From ILLEGAL: SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
127
Copy status register
128
Enter Supervisor mode
129
Turn off tracing
130
Reset, interrupt exceptions: update interrupt priority mask
131
Determine vector number
132
Save on stack using SSP
133
 
134
PC value in exceptions:
135
    usualy: trap: trace: interrupt: with address of next instruction,
136
    address and bus errors: advanced 2-10 bytes after first word of current instruction
137
    privilege violation: illegal: address of first word of current instruction
138
 
139
 
140
Without:
141
- Function Codes
142
- Bus arbitration
143
- Synchronous 6800 bus cycles
144
 
145
 
146
Operation code map:
147
0000 Bit Manipulation/MOVEP/Immediate
148
0001 Move Byte
149
0010 Move Long
150
0011 Move Word
151
0100 Miscellaneous
152
0101 ADDQ/SUBQ/Scc/DBcc/TRAPc
153
0110 Bcc/BSR/BRA
154
0111 MOVEQ
155
1000 OR/DIV/SBCD
156
1001 SUB/SUBX
157
1010 (Unassigned, Reserved)
158
1011 CMP/EOR
159
1100 AND/MUL/ABCD/EXG
160
1101 ADD/ADDX
161
1110 Shift/Rotate/Bit Field
162
1111 Coprocessor Interface/MC68040 and CPU32 Extensions
163
 
164
 
165
*******************************************************************************************************************************************
166
*******************************************************************************************************************************************
167
*******************************************************************************************************************************************
168
 
169
 
170
*******************************************************************************************************************************************
171
* add, sub
172
*******************************************************************************************************************************************
173
*
174
ABCD        Add Decimal with Extend
175
[SBCD        Subtract Decimal with Extend]
176
    Destination10 +[-] Source10 +[-] X -> Destination
177
    Byte operation, packed BCD
178
    CC: X=C set if decimal carry [borrow] else cleared; Z cleared if result nonzero else unchanged; N,V undefined
179
    1100[1000] Ry dest(3 bits) 1 0000 R/M Rx source(3 bits)
180
        R/M = 0 data registers, 1 = address registers predecrement: -(An)
181
*
182
ADD         Add
183
[SUB          Subtract]
184
    Destination +[-] Source -> Destination
185
    Byte, Word, Long
186
    CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
187
        N set if result negative else cleared
188
    1101[1001] register(3 bits) opmode(3 bits) ea mode register (3,3 bits)
189
        register: data reg
190
        opmode: 000,001,010 byte,word,long: ea +[-] Dn -> Dn; 100, 101, 110 byte,word,long: Dn +[-] ea -> ea
191
        ea source, all modes:     Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
192
                                  (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
193
        ea dest, memory alter:                                    (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
194
                                  (xxx).W 111 000, (xxx).L 111 001
195
*
196
ADDA        Add Address
197
[SUBA         Subtract Address]
198
    Destination +[-] Source -> Destination
199
    Word, Long
200
    CC: not affected
201
    1101[1001] register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
202
        register: destination An
203
        opmode: 011 word operation sign extended to 32 bits; 111 long operation
204
        ea source, all modes.
205
*
206
ADDI        Add Immediate
207
[SUBI         Subtract Immediate]
208
    Destination +[-] Immediate data -> Destination
209
    Byte, Word, Long
210
    CC: same as ADD
211
    0000 0110[0100] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
212
        size: 00,01,10 byte,word,long
213
        ea dest, data alter:    Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
214
                                (xxx).W 111 000, (xxx).L 111 001,
215
*
216
ADDQ        Add Quick
217
[SUBQ         Subtract Quick]
218
    Destination +[-] Immediate data -> Destination
219
    Byte, Word, Long
220
    CC: same as ADD,ADDA; not affected when destiantion is An
221
    0101 data(3 bits) 0[1] size(2 bits) ea mode register (3,3 bits)
222
        data: immediate data: 0=8, 1=1, ..., 7=7
223
        size: 00,01,10 byte,word,long
224
        ea dest, alter:            Dn 000, An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
225
                                (xxx).W 111 000, (xxx).L 111 001,
226
*
227
ADDX        Add with Extend
228
[SUBX         Subtract with Extend]
229
    Destination +[-] Source +[-] X -> Destination
230
    Byte, Word, Long
231
    CC: X=C set if carry[borrow] else cleared; V set if overflow else cleared; Z cleared if nonzero else unchanged; N set if negative else cleared
232
    1101[1001] Ry dest(3 bits) 1 size(2 bits) 00 R/M Rx source(3 bits)
233
        R/M = 0 data registers, 1 = address registers predecrement: -(An)
234
        size: 00,01,10 byte,word,long
235
 
236
*******************************************************************************************************************************************
237
* cmp
238
*******************************************************************************************************************************************
239
*
240
CMP         Compare
241
    Destination - Source -> CC
242
    Byte, Word, Long
243
    CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
244
    1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
245
        register: destination Dn
246
        opmode: 000,001,010 byte,word,long: Dn - ea
247
        ea source, all modes.
248
*
249
CMPA        Compare Address
250
    Destination - Source -> CC
251
    CC: same as CMP
252
    1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
253
        register: destination An
254
        opmode: 011 word operation sign extended to 32 bits; 111 long operation
255
        ea source, all modes.
256
*
257
CMPI        Compare Immediate
258
    Destination - Immediate Data -> CC
259
    Byte, Word, Long
260
    CC: same as CMP
261
    0000 1100 size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
262
        size: 00,01,10 byte,word,long
263
        ea dest, data alter.
264
*
265
CMPM        Compare Memory to Memory
266
    Destination - Source -> CC
267
    Byte, Word, Long
268
    CC: same as CMP
269
    1011 Ax dest(3 bits) 1 size(2 bits) 00 1 Ay source(3 bits)
270
        Ax dest, Ay source: postincrement: +(An)
271
        size: 00,01,10 byte,word,long
272
 
273
*******************************************************************************************************************************************
274
* mul, div
275
*******************************************************************************************************************************************
276
*
277
MULS         Signed Multiply
278
[MULU         Unsigned Multiply]
279
    Source x Destination -> Destination
280
    Word operation: source and dest 16 bit lower order -> destination 32 bit
281
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
282
    1100 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits)
283
        ea source, data:        Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
284
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
285
 
286
*
287
DIVS        Signed Divide
288
[DIVU        Unsigned Divide]
289
    Destination / Source -> Destination
290
    Word operation: dest 32 bits, source 16 bits -> 16 bit MSB remainder, 16 bit LSB quotient, sign of remainder = sign of dividend
291
    CC: X not affected; C cleared; V set if overflow else if trap undefined else cleared;
292
        Z set if quotient zero else if trap or overflow undefined else cleared;
293
        Z set if quotient negative else if trap or overflow undefined else cleared;
294
    1000 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits)
295
        ea source, data.
296
 
297
    Overflow: if quotient larger than a 16-bit signed integer.
298
    Division by 0: trap.
299
    If overflow detected: operands unaffected.
300
 
301
*******************************************************************************************************************************************
302
* ext, neg
303
*******************************************************************************************************************************************
304
*
305
EXT         Sign Extend
306
    Destination sign-extended -> Destination
307
    Word, Long
308
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
309
    0100 100 opmode(3 bits) 00 0 Dn dest(3 bits)
310
        opmode: 010,011 byte to word, word to long
311
*
312
NEGX        Negate with Extend
313
 
314
    Byte, Word, Long
315
    CC: X=C set if borrow else clear; V set if overflow else clear; Z set if nonzero else unchanged; N set if negative else clear
316
    0100 0000 size(2 bits) ea mode register(3,3 bits)
317
        size: 00,01,10 byte,word,long
318
        ea dest, data alter.
319
*
320
NBCD        Negate Decimal with Extend
321
 
322
    Byte operation
323
    CC: X=C set if decimal borrow else cleared; Z cleared if nonzero else unchanged; N,V undefined
324
    0100 1000 00 ea mode register(3,3 bits)
325
        ea dest, data alter.
326
*
327
NEG         Negate
328
 
329
    Byte, Word, Long
330
    CC: X=C clear if zero else set; V set if overflow else clear; Z set if zero else clear; N set if negative else clear
331
    0100 0100 size(2 bits) ea mode register(3,3 bits)
332
        size: 00,01,10 byte,word,long
333
        ea dest, data alter.
334
 
335
*******************************************************************************************************************************************
336
* and,eor,or,not
337
*******************************************************************************************************************************************
338
*
339
AND         Logical AND
340
[OR           Logical Inclusive-OR]
341
    Source &[|] Destination -> Destination
342
    Byte, Word, Long: not on An
343
    CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
344
    1100[1000] Dn register(3 bits) opmode(3 bits) ea mode register(3,3 bits)
345
        opmode: 000,001,010 byte,word,long: ea & Dn -> Dn; 100,101,110 byte,word,long: Dn & ea -> ea
346
        ea source, data.
347
        ea dest, memory alter.
348
*
349
ANDI        Logical AND Immediate
350
[EORI        Logical Exclusive-OR Immediate]
351
[ORI          Logical Inclusive-OR Immediate]
352
    Immediate data &[^][|] Destination -> Destination
353
    Byte, Word, Long
354
    CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
355
    0000 0010[1010][0000] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
356
        size: 00,01,10 byte,word,long
357
        ea dest, data alter.
358
*
359
ANDI to CCR AND Immediate to Condition Code Register
360
[EORI to CCR Exclusive-OR Immediate to Condition Code Register]
361
[ORI to CCR   Inclusive-OR Immediate to Condition Code Register]
362
    Source &[^][|] CCR -> CCR
363
    Byte operation
364
    CC: result
365
    0000 0010[1010][0000] 00 111 100; 0000 0000 data(8 bit)
366
*
367
ANDI to SR  AND Immediate to Status Register/Privilege/
368
[EORI to SR  Exclusive-OR Immediate to Status Register/Privilege/]
369
[ORI to SR   Inclusive-OR Immediate to Status Register/Privilege/]
370
    Source &[^][|] SR -> SR
371
    Word operation
372
    CC: result
373
    0000 0010[1010][0000] 01 111 100; data(16 bit)
374
*
375
EOR         Logical Exclusive-OR
376
    Source ^ Destination -> Destination
377
    Byte, Word, Long
378
    CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
379
    1011 Dn source(3 bits) opmode(3 bits) ea mode register(3,3 bits)
380
        opmode: 100,101,110 byte,word,long: ea ^ Dn -> ea
381
        ea dest, data alter.
382
*
383
NOT          Logical Complement
384
    ~ Destination -> Destination
385
    Byte, Word, Long
386
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
387
    0100 0110 size(2 bits) ea mode register(3,3 bits)
388
        size: 00,01,10 byte,word,long
389
        ea dest, data alter.
390
 
391
*******************************************************************************************************************************************
392
* shift,rotate
393
*******************************************************************************************************************************************
394
*
395
ASL, ASR    Arithmetic Shift Left and Right
396
[LSL, LSR     Logical Shift Left and Right]
397
[ROL, ROR     Rotate Left and Right]
398
[ROXL, ROXR   Rotate with Extend Left and Right]
399
    Destination shifted[shifted][rotated][rotated with X] by count -> Destination
400
    Byte, Word, Long, in memory: 1 bit shift[shift][rotate][rotate] and word
401
    CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared;
402
        Z set if zero else cleared; V set if MSB bit changed during shift else cleared[cleared][cleared][cleared];
403
        C set to last bit, cleared if zero shift[same][same][set to X]
404
    1110 count/register(3 bits) dr(1 bit) size(2 bits) i/r(1 bit) 00[01][11][10] Dn dest(3 bit)
405
        i/r = 0 count/register=count: 0=8, 1=1, ..., 7=7; i/r = 0 count/register=register: modulo 64
406
        dr = 0 right shift; dr = 1 left shift
407
        size: 00,01,10 byte,word,long
408
    1110 000[001][011][010] dr(1 bit) 11 ea mode register(3,3 bits)
409
        dr = 0 right shift; dr = 1 left shift
410
        ea dest: memory alter.
411
 
412
*******************************************************************************************************************************************
413
* move,clr,exg,swap
414
*******************************************************************************************************************************************
415
*
416
MOVE         Move
417
    Source -> Destination
418
    Byte, Word, Long
419
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
420
    00 size(2 bits) ea dest register mode(3,3 bits) ea source mode register(3,3 bits)
421
        size: 01,11,10 byte,word,long
422
         ea dest, data alter.
423
         ea source, all modes.
424
*
425
MOVEA        Move Address
426
    Source -> Destination
427
    Word, Long
428
    CC: not affected
429
    00 size(2 bits) An dest(3 bits) 0 01 ea source mode register(3,3 bits)
430
        size: 11,10 word,long: word operands are sign extended
431
        ea source, all modes.
432
*
433
MOVE to CCR  Move to Condition Code Register
434
    Source -> CC
435
    Word operation: upper byte ignored
436
    0100 0100 11 ea source mode register(3,3 bits)
437
    ea source, data.
438
*
439
MOVE from SR Move from Status Register
440
    SR -> Destination
441
    Word operation
442
    CC: not affected
443
    0100 0000 11 ea dest mode register(3,3 bits)
444
        ea dest, data alter.
445
*
446
MOVE to SR   Move to Status Register/Privileged/
447
    Source -> SR
448
    Word operation
449
    CC: result
450
    0100 0110 11 ea source mode register(3,3 bits)
451
        ea source, data.
452
*
453
MOVE USP     Move User Stack Pointer/Privileged/
454
    USP -> An; An -> USP
455
    Long operation
456
    CC: not affected
457
    0100 1110 0110 dr(1 bit) An reg(3 bits)
458
        dr: 0 An -> USP; 1 USP -> An
459
*
460
MOVEM        Move Multiple Registers
461
    Registers -> Destination; Source -> Registers
462
    Word, Long: word operations to An or Dn are sign extended
463
    CC: not affected
464
    0100 1 dr(1 bit) 00 1 size(1 bit) ea mode register(3,3 bits); register list mask
465
        dr: 0 register to memory; 1 memory to register
466
        size: 0,1 word,long operation
467
        ea dest: register to memory, control alter or predecrement available:
468
                                                    (An) 010,            -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
469
                                (xxx).W 111 000, (xxx).L 111 001,
470
        ea source: memory to register, control or postincrement available:
471
                                                            (An) 010, (An)+ 011,            (d16, An) 101, (d8, An, Xn) 110,
472
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
473
        list mask: control or postincrement: A7-A0, D7-D0; predecrement: D0-D7; A0-A7
474
*
475
MOVEP        Move Peripheral
476
    Source -> Destination
477
    Word, Long
478
    CC: not affected
479
    0000 data reg(3 bits) opmode(3 bits) 00 1 address reg(3 bits); 16 bit displacement
480
        opmode: 100,101 word,long: memory -> register; 110,111 word,long: register -> memory
481
        address reg: (An, d16)
482
*
483
MOVEQ        Move Quick
484
    Immediate data -> Destination
485
    Long operation; 8 bit data is sign extended to 32 bits
486
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
487
    0111 Dn dest(3 bits) 0 data(8 bits)
488
*
489
CLR         Clear
490
 
491
    Byte, Word, Long
492
    CC: X not affected; C cleared; V cleared; Z set; N cleared
493
    0100 0010 size(2 bits) ea dest mode register(3,3 bits)
494
        size: 00,01,10 byte,word,long
495
        ea dest, data alter.
496
*
497
EXG         Exchange Registers
498
    Rx <-> Ry
499
    Long operation
500
    CC: not affected
501
    1100 Rx reg(3 bits) 1 opmode(5 bits) Ry reg(3 bits)
502
        Rx reg: if Dn <-> An always Dn
503
        Ry reg: if Dn <-> An always An
504
        opmode: 01000 data regs; 01001 address regs; 10001 mix regs
505
*
506
SWAP        Swap Register Words
507
    Reg 31-16 <-> Reg 15-0
508
    Word operation
509
    CC: X not affected; C cleared; V cleared; Z set if 32 bits are zero else cleared; N set if result MSB set else cleared
510
    0100 1000 0100 0 reg(3 bits)
511
 
512
*******************************************************************************************************************************************
513
* branch,jump
514
*******************************************************************************************************************************************
515
*
516
Bcc         Branch Conditionally
517
    if condition PC + d8/d16 -> PC
518
    Byte, Word
519
    CC: not affected
520
    0110 condition(4 bits) disp8(8 bit); 16 bit displacement if disp8 == 0
521
        condition:                               high(!C & !Z) 0010, low or same(C | V) 0011,
522
                    carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
523
                    overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
524
                    greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V) 1101,
525
                    greater than(N & V & !Z | !N & !V & !Z) 1110, less or equal(Z | N & !V | !N & V) 1111
526
*
527
BRA         Branch
528
    if condition PC + d8/d16 -> PC
529
    Byte, Word
530
    CC: not affected
531
    0110 0000 disp8(8 bit); 16 bit displacement if disp8 == 0
532
*
533
BSR         Branch to Subroutine
534
    SP -= 4; PC -> (SP); PC + d8/d16 -> PC
535
    Byte, Word
536
    CC: not affected
537
    0110 0001 disp8(8 bit); 16 bit displacement if disp8 == 0
538
*
539
DBcc        Test Condition, Decrement, and Branch
540
    if !condition { Dn(lower order 16 bits) -= 1; if Dn != -1 then PC + d16 -> PC }
541
    Word operation
542
    CC: not affected
543
    0101 condition(4 bits) 1100 1 Dn register(3 bits); 16 bit displacement
544
        condition:    true(1) 0000, false(0) 0001, high(!C & !Z) 0010, low or same(C | V) 0011,
545
                    carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
546
                    overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
547
                    greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V),
548
                    greater than(N & V & !Z | !N & !V & !Z), less or equal(Z | N & !V | !N & V) 1111
549
*
550
JMP         Jump
551
    Destination address -> PC
552
    Unsized
553
    CC: not affected
554
    0100 1110 11 ea mode register(3,3 bits)
555
        ea, control:                                          (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
556
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
557
*
558
JSR         Jump to Subroutine
559
    SP -= 4; PC -> (SP); Destination address -> PC
560
    Unsized
561
    CC: not affected
562
    0100 1110 10 ea mode register(3,3 bits)
563
        ea, control.
564
*
565
RTR          Return and Restore
566
    (SP) -> CC; SP += 2; (SP) -> PC; SP += 4
567
    Unsized
568
    CC: set from stack; supervisor bits unaffected
569
    0100 1110 0111 0111
570
*
571
RTS          Return from Subroutine
572
    (SP) -> PC; SP += 4
573
    Unsized
574
    CC: not affected
575
    0100 1110 0111 0101
576
 
577
*******************************************************************************************************************************************
578
* test bit,test,check
579
*******************************************************************************************************************************************
580
*
581
BCHG        Test Bit and Change
582
[BCLR        Test Bit and Clear]
583
[BSET        Test Bit and Set]
584
[BTST        Test Bit]
585
    test(  of Destination ) -> Z; test(  of Destination )[0][1][nothing] ->  of Destination
586
    Byte, Long
587
    CC: X,N,V,C not affected; Z set if bit tested is zero else cleared
588
    0000 Dn reg(3 bits) 101[110][111][100] ea mode register(3,3 bits)
589
        Dn reg: bit number
590
        ea dest, data alter.[same][same][data address]; Dn is long operation else byte operation
591
    0000 1000 01[10][11][00] ea mode register(3,3 bits); 0000 0000 bit number(8 bits)
592
        ea dest, data alter[same][same][data address]; Dn is long operation else byte operation
593
 
594
        ea data address            Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
595
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
596
*
597
Scc         Set Conditionally
598
    if condition 1s -> Destination else 0s -> Destination
599
    Byte operation
600
    CC: not affected
601
    0101 condition(4 bits) 11 ea mode register(3,3 bits)
602
        condition: same as in DBcc
603
        ea dest, data alter.
604
*
605
TAS         Test Operand and Set/Read-modify-write bus operation/
606
    Destination tested -> CC; 1 -> bit 7 of destination
607
    Byte operation
608
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
609
    0100 1010 11 ea mode register(3,3 bits)
610
        ea operand, data alter.
611
*
612
TST         Test Operand
613
    Destination tested -> CC
614
    Byte, Word, Long
615
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
616
    0100 1010 size(2 bits) ea mode register(3,3 bits)
617
        size: 00,01,10 byte,word,long
618
        ea operand, data alter.
619
*
620
CHK         Check Register Against Bound
621
    if Dn < 0 or Dn > Source then TRAP
622
    Word operation
623
    CC: X not affected; N set if Dn < 0; cleared if Dn > Source else undefined; C,V,Z udefined
624
    0100 Dn reg(3 bits) size(2 bits) 0 ea mode register(3,3 bits)
625
        size: 11 word
626
        ea source, data.
627
 
628
*******************************************************************************************************************************************
629
* address,stack
630
*******************************************************************************************************************************************
631
*
632
LEA          Load Effective Address
633
    ea -> An
634
    Long operation
635
    CC: not affected
636
    0100 An reg(3 bits) 1 11 ea mode register(3,3 bits)
637
        ea, control.
638
*
639
PEA          Push Effective Address
640
    SP -= 4; ea -> (SP)
641
    Long operation
642
    CC: not affected
643
    0100 1000 01 ea mode register(3,3 bits)
644
        ea, control.
645
*
646
LINK         Link and Allocate
647
    SP -= 4; An -> (SP); SP -> An; SP + d16 -> SP
648
    Word operation
649
    CC: not affected
650
    0100 1110 0101 0 An reg(3 bits); 16 bit displacement
651
*
652
UNLK         Unlink
653
    An -> SP; (SP) -> An; Sp += 4
654
    Unsized
655
    CC: not affected
656
    0100 1110 0101 1 An reg(3 bits)
657
 
658
*******************************************************************************************************************************************
659
* exceptions
660
*******************************************************************************************************************************************
661
*
662
ILLEGAL     Take Illegal Instruction Trap
663
    SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
664
    Unsized
665
    CC: not affected
666
    0100 1010 1111 1100
667
*
668
TRAP        Trap
669
    1 -> S-bit of SR; SSP -= 4; PC -> (SSP); SSP -= 2; SR -> (SSP)
670
    Unsized
671
    CC: not affected
672
    0100 1110 0100 vector(4 bits)
673
*
674
TRAPV       Trap on Overflow
675
    if V then TRAP
676
    Unsized
677
    CC: not affected
678
    0100 1110 0111 0110
679
*
680
RTE         Return from Exception/Privileged/
681
    if S-bit set in SR then { (SP) -> SR; SP += 2; (SP) -> PC; SP += 4; restore state and dealocate rest of stack according to (SP) } else TRAP
682
    Unsized
683
    CC: set from stack
684
    0100 1110 0111 0011
685
 
686
*******************************************************************************************************************************************
687
* control
688
*******************************************************************************************************************************************
689
*
690
NOP          No Operation
691
    None
692
    Unsized
693
    CC: not affected
694
    0100 1110 0111 0001
695
*
696
RESET        Reset External Devices/Privileged/
697
    if S-bit set in SR then { assert !RESET line for 124 clock cycles } else TRAP
698
    Unsized
699
    CC: not affected
700
    0100 1110 0111 0000
701
*
702
STOP         Stop/Privileged/
703
    if S-bit set in SR then { immediate data -> SR; STOP } else TRAP
704
    Unsized
705
    CC: set according to immediate data
706
    0100 1110 0111 0010; 16 bit immediate data
707
 
708
    Resume when trace, interrupt or rest.
709
 
710
*******************************************************************************************************************************************
711
*******************************************************************************************************************************************
712
*******************************************************************************************************************************************
713
 
714
0000 0010[1010][0000] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
715
                                                                                                    ANDI,EORI,ORI
716
 
717
0000 0010[1010][0000] 00 111 100; 0000 0000 data(8 bit)                                             ANDI to CCR,EORI to CCR,ORI to CCR
718
0000 0010[1010][0000] 01 111 100; data(16 bit)                                                      ANDI to SR,EORI to SR,ORI to SR
719
 
720
0000 0110[0100] size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
721
                                                                                                    ADDI,SUBI
722
 
723
0000 1000 01[10][11][00] ea mode register(3,3 bits); 0000 0000 bit number(8 bits)                   BCHG,BCLR,BSET,BTST
724
 
725
0000 1100 size(2 bits) ea mode register(3,3 bits); imm16 next word, imm8 lower order byte of next word, imm32 two next words
726
                                                                                                    CMPI
727
 
728
0000 Dn reg(3 bits) 101[110][111][100] ea mode register(3,3 bits)                                   BCHG,BCLR,BSET,BTST
729
 
730
0000 Dn reg(3 bits) opmode(3 bits) 001 address reg(3 bits); 16 bit displacement                     MOVEP
731
 
732
00 size(2 bits) ea dest register mode(3,3 bits) ea source mode register(3,3 bits)                   MOVE
733
00 size(2 bits) An dest(3 bits) 001 ea source mode register(3,3 bits)                               MOVEA
734
 
735
if( 0000 000 0 ** !111100 )        ORI
736
if( 0000 000 0 00 111100 )        ORI to CCR
737
if( 0000 000 0 01 111100 )         ORI to SR
738
if( 0000 001 0 ** !111100 )        ANDI
739
if( 0000 001 0 00 111100 )        ANDI to CCR
740
if( 0000 001 0 01 111100 )         ANDI to SR
741
if( 0000 010 0 )                SUBI
742
if( 0000 011 0 )                ADDI
743
if( 0000 100 0 )                BCHG,BCLR,BSET,BTST
744
if( 0000 101 0 ** !111100 )        EORI
745
if( 0000 101 0 00 111100 )        EORI to CCR
746
if( 0000 101 0 01 111100 )         EORI to SR
747
if( 0000 110 0 )                CMPI
748
if( 0000 *** 1** !001 )            BCHG,BCLR,BSET,BTST
749
if( 0000 *** 1** 001 )            MOVEP
750
if( 00 !00 *** !001 )            MOVE
751
if( 00 !00 *** 001 )            MOVEA
752
 
753
*******************************************************************************************************************************************
754
 
755
0100     0000                 size(2 bits)     ea mode register(3,3 bits)                           NEGX
756
0100     0000                 11                 ea dest mode register(3,3 bits)                    MOVE FROM SR
757
 
758
0100     Dn reg(3 bits) 1     10                 ea mode register(3,3 bits)                         CHK
759
0100     An reg(3 bits) 1     11                 ea mode register(3,3 bits)                         LEA
760
 
761
0100 0010 size(2 bits) ea dest mode register(3,3 bits)                                              CLR
762
 
763
0100 0100 size(2 bits) ea mode register(3,3 bits)                                                   NEG
764
0100 0100 11 ea source mode register(3,3 bits)                                                      MOVE TO CCR
765
 
766
0100 0110 size(2 bits) ea mode register(3,3 bits)                                                   NOT
767
0100 0110 11 ea source mode register(3,3 bits)                                                      MOVE TO SR
768
 
769
0100     1000     00     ea mode register(3,3 bits)                                                 NBCD
770
0100     1000     01    000 reg(3 bits)                                                             SWAP
771
0100     1000     01     ea mode register(3,3 bits)                                                 PEA
772
0100     100     opmode(3 bits) 000 Dn dest(3 bits)                                                 EXT
773
 
774
0100     1 dr(1 bit) 00 1 size(1 bit) ea mode register(3,3 bits); register list mask                MOVEM
775
 
776
0100     1010     size(2 bits) ea mode register(3,3 bits)                                           TST
777
0100     1010     11 ea mode register(3,3 bits)                                                     TAS
778
0100     1010     1111     1100                                                                     ILLEGAL
779
 
780
0100     1110    0100    vector(4 bits)                                                             TRAP
781
 
782
0100     1110     0101      0 An reg(3 bits); 16 bit displacement                                   LNK
783
0100     1110     0101    1 An reg(3 bits)                                                          UNLK
784
 
785
0100     1110    0110     dr(1 bit) An reg(3 bits)                                                  MOVE USP
786
 
787
0100     1110     0111     0000                                                                     RESET
788
0100     1110     0111      0001                                                                    NOP
789
0100     1110     0111    0010                                                                      STOP
790
0100     1110     0111     0011                                                                     RTE
791
0100     1110     0111     0101                                                                     RTS
792
0100     1110     0111    0110                                                                      TRAPV
793
0100     1110     0111     0111                                                                     RTR
794
 
795
0100     1110     10     ea mode register(3,3 bits)                                                 JSR
796
0100     1110     11     ea mode register(3,3 bits)                                                 JMP
797
 
798
if( 0100 0000 00|01|10 )         NEGX
799
if( 0100 0000 11 )                 MOVE FROM SR
800
if( 0100 ***1 10 )                 CHK
801
if( 0100 ***1 11 )                LEA
802
if( 0100 0010 )                    CLR
803
if( 0100 0100 00|01|10 )         NEG
804
if( 0100 0100 11 )                MOVE TO CCR
805
if( 0100 0110 00|01|10 )         NOT
806
if( 0100 0110 11 )                MOVE TO SR
807
if( 0100 1000 00 )                NBCD
808
if( 0100 1000 01 000 )            SWAP
809
if( 0100 1000 01 !000 )            PEA
810
if( 0100 1000 1* 000 )             EXT
811
if( 0100 1*00 1* !000 )            MOVEM
812
if( 0100 1010 00|01|10 )         TST
813
if( 0100 1010 11 !111100 )        TAS
814
if( 0100 1010 11 111100 )        ILLEGAL
815
if( 0100 1110 0100 )            TRAP
816
if( 0100 1110 0101 0 )            LNK
817
if( 0100 1110 0101 1 )             ULNK
818
if( 0100 1110 0110 )            MOVE USP
819
if( 0100 1110 0111 0000 )         RESET
820
if( 0100 1110 0111 0001 )         NOP
821
if( 0100 1110 0111 0010 )         STOP
822
if( 0100 1110 0111 0011 )         RTE
823
if( 0100 1110 0111 0101 )         RTS
824
if( 0100 1110 0111 0110 )         TRAPV
825
if( 0100 1110 0111 0111 )         RTR
826
if( 0100 1110 10 )                 JSR
827
if( 0100 1110 11 )                 JMP
828
 
829
*******************************************************************************************************************************************
830
 
831
0101 data(3 bits) 0[1] size(2 bits) ea mode register (3,3 bits)                                     ADDQ,SUBQ
832
0101 condition(4 bits) 11 ea mode register(3,3 bits)                                                Scc
833
0101 condition(4 bits) 11 001 Dn register(3 bits); 16 bit displacement                              DBcc
834
 
835
if( 0101 *** 0 !11 )            ADDQ
836
if( 0101 *** 1 !11 )            SUBQ
837
if( 0101 *** * 11 !001 )        Scc
838
if( 0101 *** * 11 001 )            DBcc
839
 
840
*******************************************************************************************************************************************
841
 
842
0110 0000 disp8(8 bit); 16 bit displacement if disp8 == 0                                           BRA
843
0110 0001 disp8(8 bit); 16 bit displacement if disp8 == 0                                           BSR
844
0110 condition(4 bits) disp8(8 bit); 16 bit displacement if disp8 == 0                              Bcc
845
 
846
if( 0110 0000 )                 BRA
847
if( 0110 0001 )                    BSR
848
if( 0110 !000 )                    Bcc
849
 
850
*******************************************************************************************************************************************
851
 
852
0111 Dn dest(3 bits) 0 data(8 bits)                                                                 MOVEQ
853
 
854
*******************************************************************************************************************************************
855
 
856
1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits)                                     CMP
857
 
858
1011 Dn source(3 bits) opmode(3 bits) ea mode register(3,3 bits)                                    EOR
859
1011 Ax dest(3 bits) 1 size(2 bits) 001 Ay source(3 bits)                                           CMPM
860
 
861
1011 register(3 bits) opmode(3 bits) ea mode register(3,3 bits)                                     CMPA
862
 
863
if( 1011 *** 000|001|010 )        CMP
864
if( 1011 *** 100|101|110 001 )    CMPM
865
if( 1011 *** 100|101|110 !001 )    EOR
866
if( 1011 *** 011|111 )            CMPA
867
 
868
*******************************************************************************************************************************************
869
 
870
1000 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits)                                             DIVS,DIVU
871
 
872
1100[1000] Ry dest(3 bits) 1 0000 R/M Rx source(3 bits)                                             ABCD,SBCD
873
1100[1000] Dn register(3 bits) opmode(3 bits) ea mode register(3,3 bits)                            AND,OR
874
 
875
1100 Rx reg(3 bits) 1 opmode(5 bits) Ry reg(3 bits)                                                 EXG
876
1100 Dn dest(3 bits) 1[0] 11 ea mode register(3,3 bits)                                             MULS,MULU
877
 
878
if( 1000 *** 011 )                DIVU
879
if( 1000 *** 111 )                DIVS
880
if( 1000 *** 10000 )            SBCD
881
if( 1000 *** 000**|001**|010**|10001|10010|10011|101**|110** )                                      OR
882
 
883
if( 1100 *** 011 )                MULU
884
if( 1100 *** 111 )                MULS
885
if( 1100 *** 10000 )            ABCD
886
if( 1100 *** 000**|001**|010**|10001|10010|10011|10101|10110|10111|11001|11010|11011 )              AND
887
if( 1100 *** 10100|11000 )         EXG
888
 
889
*******************************************************************************************************************************************
890
 
891
1101[1001] register(3 bits) opmode(3 bits) ea mode register (3,3 bits)                              ADD,SUB
892
1101[1001] register(3 bits) opmode(3 bits) ea mode register(3,3 bits)                               ADDA,SUBA
893
1101[1001] Ry dest(3 bits) 1 size(2 bits) 00 R/M Rx source(3 bits)                                  ADDX,SUBX
894
 
895
if( 1001 *** 000|001|010|10001|10010|10011|10101|10110|10111|11001|11010|11011 )    SUB
896
if( 1001 *** 011|111 )                    SUBA
897
if( 1001 *** 10000|10100|11000 )        SUBX
898
if( 1101 *** 000|001|010|10001|10010|10011|10101|10110|10111|11001|11010|11011 )    ADD
899
if( 1101 *** 011|111 )                    ADDA
900
if( 1101 *** 10000|10100|11000)            ADDX
901
 
902
*******************************************************************************************************************************************
903
 
904
1110 count/register(3 bits) dr(1 bit) size(2 bits) i/r(1 bit) 00[01][11][10] Dn dest(3 bit)         ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
905
1110 000[001][011][010] dr(1 bit) 11 ea mode register(3,3 bits)                                     ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
906
 
907
if( 1110 *** * !11 )             ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
908
if( 1110 *** * 11 )             ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR
909
 
910
*******************************************************************************************************************************************
911
 
912
microcode
913
instruction: XXXX *** XXX
914
 
915
0000 *** 000                ORI,ORI to CCR,ANDI,ANDI to CCR,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,EORI to CCR,CMPI
916
0000 *** 001                ORI,ORI to SR,ANDI,ANDI to SR,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,EORI to SR,CMPI
917
0000 *** 010                ORI,ANDI,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,CMPI
918
0000 *** 011                ORI,ANDI,SUBI,ADDI,BCHG,BCLR,BSET,BTST,EORI,CMPI
919
0000 *** 100                BCHG,BCLR,BSET,BTST,MOVEP
920
0000 *** 101                BCHG,BCLR,BSET,BTST,MOVEP
921
0000 *** 110                BCHG,BCLR,BSET,BTST,MOVEP
922
0000 *** 111                BCHG,BCLR,BSET,BTST,MOVEP
923
 
924
0001 *** 000                MOVE
925
0001 *** 001                MOVEA
926
0001 *** 010                MOVE
927
0001 *** 011                MOVE
928
0001 *** 100                MOVE
929
0001 *** 101                MOVE
930
0001 *** 110                MOVE
931
0001 *** 111                MOVE
932
 
933
0010 *** 000                MOVE
934
0010 *** 001                MOVEA
935
0010 *** 010                MOVE
936
0010 *** 011                MOVE
937
0010 *** 100                MOVE
938
0010 *** 101                MOVE
939
0010 *** 110                MOVE
940
0010 *** 111                MOVE
941
 
942
0011 *** 000                MOVE
943
0011 *** 001                MOVEA
944
0011 *** 010                MOVE
945
0011 *** 011                MOVE
946
0011 *** 100                MOVE
947
0011 *** 101                MOVE
948
0011 *** 110                MOVE
949
0011 *** 111                MOVE
950
 
951
0100 *** 000                NEGX,CLR,NEG,NOT,NBCD,TST
952
0100 *** 001                NEGX,CLR,NEG,NOT,SWAP,PEA,TST,TRAP,LNK,ULNK,MOVE USP,RESET,NOP,STOP,RTE,RTS,TRAPV,RTR
953
0100 *** 010                NEGX,CLR,NEG,NOT,EXT,MOVEM,TST,JSR
954
0100 *** 011                MOVE FROM SR,CLR,MOVE TO CCR,MOVE TO SR,EXT,MOVEM,TAS,ILLEGAL,JMP
955
0100 *** 100                invalid
956
0100 *** 101                invalid
957
0100 *** 110                CHK
958
0100 *** 111                LEA
959
 
960
0101 *** 000                ADDQ
961
0101 *** 001                ADDQ
962
0101 *** 010                ADDQ
963
0101 *** 011                Scc,DBcc
964
0101 *** 100                SUBQ
965
0101 *** 101                SUBQ
966
0101 *** 110                SUBQ
967
0101 *** 111                Scc,DBcc
968
 
969
0110 *** 000                BRA,Bcc
970
0110 *** 001                BRA,Bcc
971
0110 *** 010                BRA,Bcc
972
0110 *** 011                BRA,Bcc
973
0110 *** 100                BSR,Bcc
974
0110 *** 101                BSR,Bcc
975
0110 *** 110                BSR,Bcc
976
0110 *** 111                BSR,Bcc
977
 
978
0111 *** 000                MOVEQ
979
0111 *** 001                MOVEQ
980
0111 *** 010                MOVEQ
981
0111 *** 011                MOVEQ
982
0111 *** 100                invalid
983
0111 *** 101                invalid
984
0111 *** 110                invalid
985
0111 *** 111                invalid
986
 
987
1000 *** 000                OR
988
1000 *** 001                OR
989
1000 *** 010                OR
990
1000 *** 011                DIVU
991
1000 *** 100                SBCD,OR
992
1000 *** 101                OR
993
1000 *** 110                OR
994
1000 *** 111                DIVS
995
 
996
1001 *** 000                SUB
997
1001 *** 001                SUB
998
1001 *** 010                SUB
999
1001 *** 011                SUBA
1000
1001 *** 100                SUB,SUBX
1001
1001 *** 101                SUB,SUBX
1002
1001 *** 110                SUB,SUBX
1003
1001 *** 111                SUBA
1004
 
1005
1010 *** 000                invalid
1006
1010 *** 001                invalid
1007
1010 *** 010                invalid
1008
1010 *** 011                invalid
1009
1010 *** 100                invalid
1010
1010 *** 101                invalid
1011
1010 *** 110                invalid
1012
1010 *** 111                invalid
1013
 
1014
1011 *** 000                CMP
1015
1011 *** 001                CMP
1016
1011 *** 010                CMP
1017
1011 *** 011                CMPA
1018
1011 *** 100                CMPM,EOR
1019
1011 *** 101                CMPM,EOR
1020
1011 *** 110                CMPM,EOR
1021
1011 *** 111                CMPA
1022
 
1023
1100 *** 000                AND
1024
1100 *** 001                AND
1025
1100 *** 010                AND
1026
1100 *** 011                MULU
1027
1100 *** 100                ABCD,AND
1028
1100 *** 101                EXG,AND
1029
1100 *** 110                EXG,AND
1030
1100 *** 111                MULS
1031
 
1032
1101 *** 000                ADD
1033
1101 *** 001                ADD
1034
1101 *** 010                ADD
1035
1101 *** 011                ADDA
1036
1101 *** 100                ADD,ADDX
1037
1101 *** 101                ADD,ADDX
1038
1101 *** 110                ADD,ADDX
1039
1101 *** 111                ADDA
1040
 
1041
1110 *** 000                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
1042
1110 *** 001                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
1043
1110 *** 010                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
1044
1110 *** 011                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR ea
1045
1110 *** 100                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
1046
1110 *** 101                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
1047
1110 *** 110                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR reg
1048
1110 *** 111                ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR ea
1049
 
1050
1111 *** 000                invalid
1051
1111 *** 001                invalid
1052
1111 *** 010                invalid
1053
1111 *** 011                invalid
1054
1111 *** 100                invalid
1055
1111 *** 101                invalid
1056
1111 *** 110                invalid
1057
1111 *** 111                invalid
1058
 
1059
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
1060
Original MC68000 Ports:
1061
 
1062
Address bus: A23-A1, output
1063
Data bus: D15-D0, bidirectional
1064
 
1065
Address Strobe: output
1066
Read/Write: 0 - write, 1 - read
1067
Upper and Lower data strobes: output
1068
 
1069
Data transfer acknowlege: input
1070
 
1071
A,D,AS,R/W,UDS,LDS: all tri-state
1072
 
1073
BERR: input
1074
BERR: perform exception handling, while BERR asserted wait in Hi-Z
1075
BERR + HALT: retry bus cycle, HALT longer than BERR for at least 1 clock cycle, while HALT asserted wait in Hi-Z,
1076
    not for read-modify-write, retry count not limited
1077
 
1078
 
1079
FC[2:0]: valid with Address Strobe
1080
 
1081
    1 - user data
1082
    2 - user program
1083
    3 - undefined
1084
    4 - undefined
1085
    5 - supervisor data             : all exception vector entries except reset
1086
    6 - supervisor program          : exception vector for reset
1087
    7 - cpu space                   : interrupt acknowlege bus cycle
1088
 
1089
interrupt IPL[2:0]:
1090
    assert IPL until processor signals interrupt acknowlege
1091
interrupt acknowlege bus cycle:
1092
    FC: 7
1093
    A23-A4: high, A3-A1: interrupt number output
1094
        D15-D8 ignored, D7-D0 + DACK: vector number
1095
        input VPA: autovector, complete 6800 read cycle: assert VMA
1096
        input BERR: spurious interrupt
1097
 
1098
HALT, RESET: inout
1099
input HALT + RESET: processor reset
1100
output RESET: RESET opcode: reset external devices
1101
output HALT: processor blocked
1102
input HALT: stop bus activity after current bus cycle, Hi-Z all three-state lines, bus arbitration as usual
1103
 
1104
 
1105
bus request: input, at any time
1106
bus grant: output, bus is to be released after current cycle
1107
bus grant acknowlege: input, bus in use by external device
1108
 
1109
E: clock: output, 6 clocks low, 4 clocks high
1110
Valid Peripheral Address: input, use autovector in interrupt acknowlege cycle, device is 6800 type: synchronize data on E
1111
Valid Memory Address: output, memory address valid and processor synchronized on E
1112
 
1113
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
1114
Backup
1115
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
1116
 
1117
//----- flip_flop_registers
1118
//ir1,ir2:
1119
//    required by: ANDI,EORI,ORI,ANDI to CCR,EORI to CCR,ORI to CCR,ANDI to SR,EORI to SR,ORI to SR,ADDI,SUBI
1120
 

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