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<h1>bus_ssram.v</h1> </div>
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<a href="bus__ssram_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">/* </span>
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<a name="l00002"></a>00002 <span class="keyword"> Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.</span>
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<a name="l00003"></a>00003 <span class="keyword"> </span>
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<a name="l00004"></a>00004 <span class="keyword"> Redistribution and use in source and binary forms, with or without modification, are</span>
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<a name="l00005"></a>00005 <span class="keyword"> permitted provided that the following conditions are met:</span>
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<a name="l00006"></a>00006 <span class="keyword"> </span>
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| 36 |
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<a name="l00007"></a>00007 <span class="keyword"> 1. Redistributions of source code must retain the above copyright notice, this list of</span>
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<a name="l00008"></a>00008 <span class="keyword"> conditions and the following disclaimer.</span>
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<a name="l00009"></a>00009 <span class="keyword"> </span>
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| 39 |
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<a name="l00010"></a>00010 <span class="keyword"> 2. Redistributions in binary form must reproduce the above copyright notice, this list</span>
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| 40 |
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<a name="l00011"></a>00011 <span class="keyword"> of conditions and the following disclaimer in the documentation and/or other materials</span>
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| 41 |
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<a name="l00012"></a>00012 <span class="keyword"> provided with the distribution.</span>
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<a name="l00013"></a>00013 <span class="keyword"> </span>
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| 43 |
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<a name="l00014"></a>00014 <span class="keyword"> THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED</span>
|
| 44 |
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<a name="l00015"></a>00015 <span class="keyword"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND</span>
|
| 45 |
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<a name="l00016"></a>00016 <span class="keyword"> FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR</span>
|
| 46 |
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<a name="l00017"></a>00017 <span class="keyword"> CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span>
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| 47 |
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<a name="l00018"></a>00018 <span class="keyword"> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
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| 48 |
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<a name="l00019"></a>00019 <span class="keyword"> SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span>
|
| 49 |
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<a name="l00020"></a>00020 <span class="keyword"> ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
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| 50 |
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<a name="l00021"></a>00021 <span class="keyword"> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF</span>
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| 51 |
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<a name="l00022"></a>00022 <span class="keyword"> ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
|
| 52 |
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<a name="l00023"></a>00023 <span class="keyword"> */</span>
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| 53 |
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<a name="l00024"></a>00024
|
| 54 |
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<a name="l00025"></a>00025 <span class="keyword">/*! \file</span>
|
| 55 |
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<a name="l00026"></a>00026 <span class="keyword"> \brief IS61LPS51236A pipelined SSRAM driver with WISHBONE slave interface.</span>
|
| 56 |
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<a name="l00027"></a>00027 <span class="keyword"> */</span>
|
| 57 |
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<a name="l00028"></a>00028
|
| 58 |
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<a name="l00029"></a>00029 <span class="keyword">/*! \brief \copybrief bus_ssram.v</span>
|
| 59 |
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<a name="l00030"></a>00030 <span class="keyword">*/</span>
|
| 60 |
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<a name="l00031"></a><a class="code" href="classbus__ssram.html">00031</a> <span class="vhdlkeyword">module</span> <a class="code" href="classbus__ssram.html">bus_ssram</a>(
|
| 61 |
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<a name="l00032"></a>00032 <span class="keyword">//% \name Clock and reset
|
| 62 |
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</span>
|
| 63 |
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<a name="l00033"></a>00033 <span class="keyword">//% @{</span>
|
| 64 |
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<a name="l00034"></a><a class="code" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">00034</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">clk_30</a>,
|
| 65 |
|
|
<a name="l00035"></a><a class="code" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">00035</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">reset_n</a>,
|
| 66 |
|
|
<a name="l00036"></a>00036 <span class="keyword">//% @}</span>
|
| 67 |
|
|
<a name="l00037"></a>00037
|
| 68 |
|
|
<a name="l00038"></a>00038 <span class="keyword">//% \name WISHBONE slave
|
| 69 |
|
|
</span>
|
| 70 |
|
|
<a name="l00039"></a>00039 <span class="keyword">//% @{</span>
|
| 71 |
|
|
<a name="l00040"></a><a class="code" href="classbus__ssram.html#a56b6627a4fb74424900848ab0d094141">00040</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">20</span>:<span class="vhdllogic">2</span>] <a class="code" href="classbus__ssram.html#a56b6627a4fb74424900848ab0d094141">ADR_I</a>,
|
| 72 |
|
|
<a name="l00041"></a><a class="code" href="classbus__ssram.html#a8ec0e74cb4fdeeff97eb86626b94e3af">00041</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#a8ec0e74cb4fdeeff97eb86626b94e3af">CYC_I</a>,
|
| 73 |
|
|
<a name="l00042"></a><a class="code" href="classbus__ssram.html#a88849a8c056fffdad33d71b2abaa0f03">00042</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#a88849a8c056fffdad33d71b2abaa0f03">WE_I</a>,
|
| 74 |
|
|
<a name="l00043"></a><a class="code" href="classbus__ssram.html#ae4f1b8a90123ceac3fded15df24e3bd3">00043</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#ae4f1b8a90123ceac3fded15df24e3bd3">SEL_I</a>,
|
| 75 |
|
|
<a name="l00044"></a><a class="code" href="classbus__ssram.html#adae0a05e495069a4351965372c3634c8">00044</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#adae0a05e495069a4351965372c3634c8">STB_I</a>,
|
| 76 |
|
|
<a name="l00045"></a><a class="code" href="classbus__ssram.html#ad83abd19cd21950a7e5abcd0068463a5">00045</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#ad83abd19cd21950a7e5abcd0068463a5">DAT_I</a>,
|
| 77 |
|
|
<a name="l00046"></a><a class="code" href="classbus__ssram.html#a78163aefbe6bb0d6f809c7e01b93967b">00046</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#a78163aefbe6bb0d6f809c7e01b93967b">DAT_O</a>,
|
| 78 |
|
|
<a name="l00047"></a><a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">00047</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a>,
|
| 79 |
|
|
<a name="l00048"></a>00048 <span class="keyword">//% @}</span>
|
| 80 |
|
|
<a name="l00049"></a>00049
|
| 81 |
|
|
<a name="l00050"></a>00050 <span class="keyword">//% \name Direct drv_ssram read/write burst DMA for ocs_video and drv_vga
|
| 82 |
|
|
</span>
|
| 83 |
|
|
<a name="l00051"></a>00051 <span class="keyword">//% @{</span>
|
| 84 |
|
|
<a name="l00052"></a>00052 <span class="keyword">// drv_vga read burst</span>
|
| 85 |
|
|
<a name="l00053"></a><a class="code" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">00053</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">burst_read_vga_request</a>,
|
| 86 |
|
|
<a name="l00054"></a><a class="code" href="classbus__ssram.html#ae9ae32b3d42fa1482fa788059b4b65df">00054</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classbus__ssram.html#ae9ae32b3d42fa1482fa788059b4b65df">burst_read_vga_address</a>,
|
| 87 |
|
|
<a name="l00055"></a><a class="code" href="classbus__ssram.html#ae9dc8c4cc4309b39f5d1aebaeded912a">00055</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#ae9dc8c4cc4309b39f5d1aebaeded912a">burst_read_vga_ready</a>,
|
| 88 |
|
|
<a name="l00056"></a>00056 <span class="keyword">// ocs_video bitplain read burst</span>
|
| 89 |
|
|
<a name="l00057"></a><a class="code" href="classbus__ssram.html#a2cc4e33e7bd7ee3d0ad1ac0a743bead3">00057</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#a2cc4e33e7bd7ee3d0ad1ac0a743bead3">burst_read_video_request</a>,
|
| 90 |
|
|
<a name="l00058"></a><a class="code" href="classbus__ssram.html#ab4c5fe3d23c0df0ab43247a1639d8fef">00058</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classbus__ssram.html#ab4c5fe3d23c0df0ab43247a1639d8fef">burst_read_video_address</a>,
|
| 91 |
|
|
<a name="l00059"></a><a class="code" href="classbus__ssram.html#a838aea80fed0e9a079d844ffd8ce3d12">00059</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#a838aea80fed0e9a079d844ffd8ce3d12">burst_read_video_ready</a>,
|
| 92 |
|
|
<a name="l00060"></a>00060 <span class="keyword">// common read burst data signal</span>
|
| 93 |
|
|
<a name="l00061"></a><a class="code" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">00061</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">35</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a>,
|
| 94 |
|
|
<a name="l00062"></a>00062 <span class="keyword">//% @}</span>
|
| 95 |
|
|
<a name="l00063"></a>00063
|
| 96 |
|
|
<a name="l00064"></a>00064 <span class="keyword">// ocs_video video output write burst</span>
|
| 97 |
|
|
<a name="l00065"></a><a class="code" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">00065</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a>,
|
| 98 |
|
|
<a name="l00066"></a><a class="code" href="classbus__ssram.html#a2c671a3dc4da1d00f8a48ae8ed545934">00066</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classbus__ssram.html#a2c671a3dc4da1d00f8a48ae8ed545934">burst_write_address</a>,
|
| 99 |
|
|
<a name="l00067"></a><a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">00067</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a>,
|
| 100 |
|
|
<a name="l00068"></a><a class="code" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">00068</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">35</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">burst_write_data</a>,
|
| 101 |
|
|
<a name="l00069"></a>00069 <span class="keyword">//% @}</span>
|
| 102 |
|
|
<a name="l00070"></a>00070
|
| 103 |
|
|
<a name="l00071"></a>00071 <span class="keyword">//% \name IS61LPS51236A pipelined SSRAM hardware interface
|
| 104 |
|
|
</span>
|
| 105 |
|
|
<a name="l00072"></a>00072 <span class="keyword">//% @{</span>
|
| 106 |
|
|
<a name="l00073"></a><a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">00073</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">18</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a>,
|
| 107 |
|
|
<a name="l00074"></a><a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">00074</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a>,
|
| 108 |
|
|
<a name="l00075"></a><a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">00075</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a>,
|
| 109 |
|
|
<a name="l00076"></a><a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">00076</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a>,
|
| 110 |
|
|
<a name="l00077"></a><a class="code" href="classbus__ssram.html#a1e624978ad4e4f2149e7980d65b0612d">00077</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#a1e624978ad4e4f2149e7980d65b0612d">ssram_adsp_n</a>,
|
| 111 |
|
|
<a name="l00078"></a><a class="code" href="classbus__ssram.html#a6e1a75c4a8c1c0a94bd2ec20430a56d3">00078</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#a6e1a75c4a8c1c0a94bd2ec20430a56d3">ssram_clk</a>,
|
| 112 |
|
|
<a name="l00079"></a><a class="code" href="classbus__ssram.html#a71ea972c05cab98195ec72ed2bce3b7f">00079</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#a71ea972c05cab98195ec72ed2bce3b7f">ssram_globalw_n</a>,
|
| 113 |
|
|
<a name="l00080"></a><a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">00080</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a>,
|
| 114 |
|
|
<a name="l00081"></a><a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">00081</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a>,
|
| 115 |
|
|
<a name="l00082"></a><a class="code" href="classbus__ssram.html#a908103f5f1aafa62a9fdcebc83094ebc">00082</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#a908103f5f1aafa62a9fdcebc83094ebc">ssram_ce1_n</a>,
|
| 116 |
|
|
<a name="l00083"></a><a class="code" href="classbus__ssram.html#abc78633b174512e8f12168c05d6484b4">00083</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#abc78633b174512e8f12168c05d6484b4">ssram_ce2</a>,
|
| 117 |
|
|
<a name="l00084"></a><a class="code" href="classbus__ssram.html#a926a811b6e4121644e869fe13899b4c5">00084</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__ssram.html#a926a811b6e4121644e869fe13899b4c5">ssram_ce3_n</a>,
|
| 118 |
|
|
<a name="l00085"></a><a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">00085</a> <span class="vhdlkeyword">inout</span> [<span class="vhdllogic">35</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a>
|
| 119 |
|
|
<a name="l00086"></a>00086 <span class="keyword">//% @}</span>
|
| 120 |
|
|
<a name="l00087"></a>00087 );
|
| 121 |
|
|
<a name="l00088"></a>00088
|
| 122 |
|
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<a name="l00089"></a>00089 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#a6e1a75c4a8c1c0a94bd2ec20430a56d3">ssram_clk</a> = <a class="code" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">clk_30</a>;
|
| 123 |
|
|
<a name="l00090"></a>00090 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#a71ea972c05cab98195ec72ed2bce3b7f">ssram_globalw_n</a> = <span class="vhdllogic">1'b1</span>;
|
| 124 |
|
|
<a name="l00091"></a>00091 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#a1e624978ad4e4f2149e7980d65b0612d">ssram_adsp_n</a> = <span class="vhdllogic">1'b1</span>;
|
| 125 |
|
|
<a name="l00092"></a>00092 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#a908103f5f1aafa62a9fdcebc83094ebc">ssram_ce1_n</a> = <span class="vhdllogic">1'b0</span>;
|
| 126 |
|
|
<a name="l00093"></a>00093 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#abc78633b174512e8f12168c05d6484b4">ssram_ce2</a> = <span class="vhdllogic">1'b1</span>;
|
| 127 |
|
|
<a name="l00094"></a>00094 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#a926a811b6e4121644e869fe13899b4c5">ssram_ce3_n</a> = <span class="vhdllogic">1'b0</span>;
|
| 128 |
|
|
<a name="l00095"></a>00095
|
| 129 |
|
|
<a name="l00096"></a><a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">00096</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a>;
|
| 130 |
|
|
<a name="l00097"></a><a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">00097</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">35</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a>;
|
| 131 |
|
|
<a name="l00098"></a>00098 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a> = (<a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> : <span class="vhdllogic">36'bZ</span>;
|
| 132 |
|
|
<a name="l00099"></a>00099
|
| 133 |
|
|
<a name="l00100"></a><a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">00100</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">18</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a>;
|
| 134 |
|
|
<a name="l00101"></a>00101
|
| 135 |
|
|
<a name="l00102"></a><a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">00102</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a>;
|
| 136 |
|
|
<a name="l00103"></a><a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">00103</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a>;
|
| 137 |
|
|
<a name="l00104"></a>00104
|
| 138 |
|
|
<a name="l00105"></a>00105 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#ae9dc8c4cc4309b39f5d1aebaeded912a">burst_read_vga_ready</a> = (<a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a> == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> : <span class="vhdllogic">1'b0</span>;
|
| 139 |
|
|
<a name="l00106"></a>00106 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#a838aea80fed0e9a079d844ffd8ce3d12">burst_read_video_ready</a> = (<a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a> == <span class="vhdllogic">1'b0</span>)? <span class="vhdllogic">1'b0</span> : <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a>;
|
| 140 |
|
|
<a name="l00107"></a>00107
|
| 141 |
|
|
<a name="l00108"></a><a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">00108</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>] <a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a>;
|
| 142 |
|
|
<a name="l00109"></a><a class="code" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">00109</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a>;
|
| 143 |
|
|
<a name="l00110"></a><a class="code" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">00110</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a>;
|
| 144 |
|
|
<a name="l00111"></a>00111 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a> = (<a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a> == <span class="vhdllogic">1'b0</span>)? <a class="code" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">burst_read_vga_request</a> : <a class="code" href="classbus__ssram.html#a2cc4e33e7bd7ee3d0ad1ac0a743bead3">burst_read_video_request</a>;
|
| 145 |
|
|
<a name="l00112"></a>00112
|
| 146 |
|
|
<a name="l00113"></a><a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">00113</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a>;
|
| 147 |
|
|
<a name="l00114"></a><a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">00114</a> <span class="vhdlkeyword">parameter</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]
|
| 148 |
|
|
<a name="l00115"></a>00115 <a class="code" href="classbus__ssram.html#a858c46d836e9106fd17cfcae0529039e">S_IDLE</a> = <span class="vhdllogic">4'd0</span>,
|
| 149 |
|
|
<a name="l00116"></a>00116 <a class="code" href="classbus__ssram.html#ae3aad805c7623cf48b1dc1b34dd51dbd">S_VW0</a> = <span class="vhdllogic">4'd1</span>,
|
| 150 |
|
|
<a name="l00117"></a>00117 <a class="code" href="classbus__ssram.html#ade6dc31a79364db517a437bd49aca37a">S_VW1</a> = <span class="vhdllogic">4'd2</span>,
|
| 151 |
|
|
<a name="l00118"></a>00118 <a class="code" href="classbus__ssram.html#aae5c7e4b75f892c0a2ef5ef414122afd">S_VW2</a> = <span class="vhdllogic">4'd3</span>,
|
| 152 |
|
|
<a name="l00119"></a>00119 <a class="code" href="classbus__ssram.html#a0f8b50cc59bc0120ac7813e85d4d0ca0">S_VW3</a> = <span class="vhdllogic">4'd4</span>,
|
| 153 |
|
|
<a name="l00120"></a>00120 <a class="code" href="classbus__ssram.html#a11872fcb25d808ba613e41904ff6e066">S_VW4</a> = <span class="vhdllogic">4'd5</span>,
|
| 154 |
|
|
<a name="l00121"></a>00121 <a class="code" href="classbus__ssram.html#a28d6f7425ce6a8a65e69440ea64a4c29">S_VR1</a> = <span class="vhdllogic">4'd6</span>,
|
| 155 |
|
|
<a name="l00122"></a>00122 <a class="code" href="classbus__ssram.html#affffa409ed1f21ffe63f23c683eba531">S_VR2</a> = <span class="vhdllogic">4'd7</span>,
|
| 156 |
|
|
<a name="l00123"></a>00123 <a class="code" href="classbus__ssram.html#a087aee8fa77cb6c2f662118321e09871">S_VR3</a> = <span class="vhdllogic">4'd8</span>,
|
| 157 |
|
|
<a name="l00124"></a>00124 <a class="code" href="classbus__ssram.html#a007e4900fdab9ae822d87670bdebfb0a">S_VR4</a> = <span class="vhdllogic">4'd9</span>,
|
| 158 |
|
|
<a name="l00125"></a>00125 <a class="code" href="classbus__ssram.html#a90be4e0d49e4873179cfef106dfca57b">S_R1</a> = <span class="vhdllogic">4'd10</span>,
|
| 159 |
|
|
<a name="l00126"></a>00126 <a class="code" href="classbus__ssram.html#ae6ed87aa25e02712ed883f69c55a5c08">S_R2</a> = <span class="vhdllogic">4'd11</span>,
|
| 160 |
|
|
<a name="l00127"></a>00127 <a class="code" href="classbus__ssram.html#aa5e59d0bad76d805d61cfcd307af35f8">S_R3</a> = <span class="vhdllogic">4'd12</span>,
|
| 161 |
|
|
<a name="l00128"></a>00128 <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a> = <span class="vhdllogic">4'd13</span>;
|
| 162 |
|
|
<a name="l00129"></a>00129
|
| 163 |
|
|
<a name="l00130"></a><a class="code" href="classbus__ssram.html#a6f9c73deb7569c415de5ce9593a44a79">00130</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classbus__ssram.html#adf48cd47cdb3d0ab37c4f679d47b3ece">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 164 |
|
|
<a name="l00131"></a>00131 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#af7d17848e6f2da5ae9db4a6072dfb9a9">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 165 |
|
|
<a name="l00132"></a>00132 <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= <span class="vhdllogic">19'd0</span>;
|
| 166 |
|
|
<a name="l00133"></a>00133 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 167 |
|
|
<a name="l00134"></a>00134 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 168 |
|
|
<a name="l00135"></a>00135 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <span class="vhdllogic">36'd0</span>;
|
| 169 |
|
|
<a name="l00136"></a>00136 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 170 |
|
|
<a name="l00137"></a>00137 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 171 |
|
|
<a name="l00138"></a>00138 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 172 |
|
|
<a name="l00139"></a>00139 <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 173 |
|
|
<a name="l00140"></a>00140
|
| 174 |
|
|
<a name="l00141"></a>00141 <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> <= <span class="vhdllogic">19'd0</span>;
|
| 175 |
|
|
<a name="l00142"></a>00142
|
| 176 |
|
|
<a name="l00143"></a>00143 <a class="code" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a> <= <span class="vhdllogic">36'd0</span>;
|
| 177 |
|
|
<a name="l00144"></a>00144 <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 178 |
|
|
<a name="l00145"></a>00145 <a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a> <= <span class="vhdllogic">1'b0</span>;
|
| 179 |
|
|
<a name="l00146"></a>00146 <a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a> <= <span class="vhdllogic">2'd0</span>;
|
| 180 |
|
|
<a name="l00147"></a>00147 <a class="code" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a> <= <span class="vhdllogic">1'b0</span>;
|
| 181 |
|
|
<a name="l00148"></a>00148
|
| 182 |
|
|
<a name="l00149"></a>00149 <a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 183 |
|
|
<a name="l00150"></a>00150
|
| 184 |
|
|
<a name="l00151"></a>00151 <a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 185 |
|
|
<a name="l00152"></a>00152 <a class="code" href="classbus__ssram.html#a78163aefbe6bb0d6f809c7e01b93967b">DAT_O</a> <= <span class="vhdllogic">32'd0</span>;
|
| 186 |
|
|
<a name="l00153"></a>00153
|
| 187 |
|
|
<a name="l00154"></a>00154 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a858c46d836e9106fd17cfcae0529039e">S_IDLE</a>;
|
| 188 |
|
|
<a name="l00155"></a>00155 <span class="vhdlkeyword">end</span>
|
| 189 |
|
|
<a name="l00156"></a>00156 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a858c46d836e9106fd17cfcae0529039e">S_IDLE</a>) <span class="vhdlkeyword">begin</span>
|
| 190 |
|
|
<a name="l00157"></a>00157 <a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 191 |
|
|
<a name="l00158"></a>00158
|
| 192 |
|
|
<a name="l00159"></a>00159 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">burst_read_vga_request</a> == <span class="vhdllogic">1'b1</span> || <a class="code" href="classbus__ssram.html#a2cc4e33e7bd7ee3d0ad1ac0a743bead3">burst_read_video_request</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 193 |
|
|
<a name="l00160"></a>00160 <span class="keyword">// address and byte enables output</span>
|
| 194 |
|
|
<a name="l00161"></a>00161 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">burst_read_vga_request</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= { <a class="code" href="classbus__ssram.html#ae9ae32b3d42fa1482fa788059b4b65df">burst_read_vga_address</a>[<span class="vhdllogic">20</span>:<span class="vhdllogic">4</span>], <span class="vhdllogic">2'b0</span> };
|
| 195 |
|
|
<a name="l00162"></a>00162 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a2cc4e33e7bd7ee3d0ad1ac0a743bead3">burst_read_video_request</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= { <a class="code" href="classbus__ssram.html#ab4c5fe3d23c0df0ab43247a1639d8fef">burst_read_video_address</a>[<span class="vhdllogic">20</span>:<span class="vhdllogic">4</span>], <span class="vhdllogic">2'b0</span> };
|
| 196 |
|
|
<a name="l00163"></a>00163 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 197 |
|
|
<a name="l00164"></a>00164 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 198 |
|
|
<a name="l00165"></a>00165 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <span class="vhdllogic">32'd0</span>;
|
| 199 |
|
|
<a name="l00166"></a>00166 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 200 |
|
|
<a name="l00167"></a>00167 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 201 |
|
|
<a name="l00168"></a>00168 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 202 |
|
|
<a name="l00169"></a>00169 <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> <= <span class="vhdllogic">4'b0000</span>;
|
| 203 |
|
|
<a name="l00170"></a>00170
|
| 204 |
|
|
<a name="l00171"></a>00171 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#ad29520a0905218b5c01253c99b6791a3">burst_read_vga_request</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 205 |
|
|
<a name="l00172"></a>00172 <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> <= { <a class="code" href="classbus__ssram.html#ae9ae32b3d42fa1482fa788059b4b65df">burst_read_vga_address</a>[<span class="vhdllogic">20</span>:<span class="vhdllogic">4</span>], <span class="vhdllogic">2'b0</span> } + <span class="vhdllogic">19'd4</span>;
|
| 206 |
|
|
<a name="l00173"></a>00173 <a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a> <= <a class="code" href="classbus__ssram.html#ae9ae32b3d42fa1482fa788059b4b65df">burst_read_vga_address</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>];
|
| 207 |
|
|
<a name="l00174"></a>00174 <a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a> <= <span class="vhdllogic">1'b0</span>;
|
| 208 |
|
|
<a name="l00175"></a>00175 <span class="vhdlkeyword">end</span>
|
| 209 |
|
|
<a name="l00176"></a>00176 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a2cc4e33e7bd7ee3d0ad1ac0a743bead3">burst_read_video_request</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 210 |
|
|
<a name="l00177"></a>00177 <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> <= { <a class="code" href="classbus__ssram.html#ab4c5fe3d23c0df0ab43247a1639d8fef">burst_read_video_address</a>[<span class="vhdllogic">20</span>:<span class="vhdllogic">4</span>], <span class="vhdllogic">2'b0</span> } + <span class="vhdllogic">19'd4</span>;
|
| 211 |
|
|
<a name="l00178"></a>00178 <a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a> <= <a class="code" href="classbus__ssram.html#ab4c5fe3d23c0df0ab43247a1639d8fef">burst_read_video_address</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>];
|
| 212 |
|
|
<a name="l00179"></a>00179 <a class="code" href="classbus__ssram.html#a63750a3306096cd8e7076802d4eb57dd">burst_read_select</a> <= <span class="vhdllogic">1'b1</span>;
|
| 213 |
|
|
<a name="l00180"></a>00180 <span class="vhdlkeyword">end</span>
|
| 214 |
|
|
<a name="l00181"></a>00181 <a class="code" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a> <= <span class="vhdllogic">1'b0</span>;
|
| 215 |
|
|
<a name="l00182"></a>00182 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a28d6f7425ce6a8a65e69440ea64a4c29">S_VR1</a>;
|
| 216 |
|
|
<a name="l00183"></a>00183 <span class="vhdlkeyword">end</span>
|
| 217 |
|
|
<a name="l00184"></a>00184 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 218 |
|
|
<a name="l00185"></a>00185 <a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a> <= <span class="vhdllogic">1'b1</span>;
|
| 219 |
|
|
<a name="l00186"></a>00186 <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> <= <a class="code" href="classbus__ssram.html#a2c671a3dc4da1d00f8a48ae8ed545934">burst_write_address</a>[<span class="vhdllogic">20</span>:<span class="vhdllogic">2</span>];
|
| 220 |
|
|
<a name="l00187"></a>00187 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#ae3aad805c7623cf48b1dc1b34dd51dbd">S_VW0</a>;
|
| 221 |
|
|
<a name="l00188"></a>00188 <span class="vhdlkeyword">end</span>
|
| 222 |
|
|
<a name="l00189"></a>00189 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classbus__ssram.html#a8ec0e74cb4fdeeff97eb86626b94e3af">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__ssram.html#adae0a05e495069a4351965372c3634c8">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__ssram.html#a88849a8c056fffdad33d71b2abaa0f03">WE_I</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 223 |
|
|
<a name="l00190"></a>00190 <span class="keyword">// address and byte enables output</span>
|
| 224 |
|
|
<a name="l00191"></a>00191 <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= <a class="code" href="classbus__ssram.html#a56b6627a4fb74424900848ab0d094141">ADR_I</a>[<span class="vhdllogic">20</span>:<span class="vhdllogic">2</span>];
|
| 225 |
|
|
<a name="l00192"></a>00192 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 226 |
|
|
<a name="l00193"></a>00193 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 227 |
|
|
<a name="l00194"></a>00194 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <span class="vhdllogic">32'd0</span>;
|
| 228 |
|
|
<a name="l00195"></a>00195 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 229 |
|
|
<a name="l00196"></a>00196 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 230 |
|
|
<a name="l00197"></a>00197 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 231 |
|
|
<a name="l00198"></a>00198 <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> <= <span class="vhdllogic">4'b0000</span>;
|
| 232 |
|
|
<a name="l00199"></a>00199
|
| 233 |
|
|
<a name="l00200"></a>00200 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a90be4e0d49e4873179cfef106dfca57b">S_R1</a>;
|
| 234 |
|
|
<a name="l00201"></a>00201 <span class="vhdlkeyword">end</span>
|
| 235 |
|
|
<a name="l00202"></a>00202 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> == <span class="vhdllogic">1'b0</span> && <a class="code" href="classbus__ssram.html#a8ec0e74cb4fdeeff97eb86626b94e3af">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__ssram.html#adae0a05e495069a4351965372c3634c8">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__ssram.html#a88849a8c056fffdad33d71b2abaa0f03">WE_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 236 |
|
|
<a name="l00203"></a>00203 <span class="keyword">// address, byte enables and write enables output</span>
|
| 237 |
|
|
<a name="l00204"></a>00204 <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= <a class="code" href="classbus__ssram.html#a56b6627a4fb74424900848ab0d094141">ADR_I</a>[<span class="vhdllogic">20</span>:<span class="vhdllogic">2</span>];
|
| 238 |
|
|
<a name="l00205"></a>00205 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 239 |
|
|
<a name="l00206"></a>00206 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 240 |
|
|
<a name="l00207"></a>00207 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= { <span class="vhdllogic">4'b0</span>, <a class="code" href="classbus__ssram.html#ad83abd19cd21950a7e5abcd0068463a5">DAT_I</a> };
|
| 241 |
|
|
<a name="l00208"></a>00208 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b1</span>;
|
| 242 |
|
|
<a name="l00209"></a>00209 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 243 |
|
|
<a name="l00210"></a>00210 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 244 |
|
|
<a name="l00211"></a>00211 <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> <= ~<a class="code" href="classbus__ssram.html#ae4f1b8a90123ceac3fded15df24e3bd3">SEL_I</a>;
|
| 245 |
|
|
<a name="l00212"></a>00212
|
| 246 |
|
|
<a name="l00213"></a>00213 <a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 247 |
|
|
<a name="l00214"></a>00214 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 248 |
|
|
<a name="l00215"></a>00215 <span class="vhdlkeyword">end</span>
|
| 249 |
|
|
<a name="l00216"></a>00216 <span class="vhdlkeyword">end</span>
|
| 250 |
|
|
<a name="l00217"></a>00217 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#ae3aad805c7623cf48b1dc1b34dd51dbd">S_VW0</a>) <span class="vhdlkeyword">begin</span>
|
| 251 |
|
|
<a name="l00218"></a>00218 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#ade6dc31a79364db517a437bd49aca37a">S_VW1</a>;
|
| 252 |
|
|
<a name="l00219"></a>00219 <span class="vhdlkeyword">end</span>
|
| 253 |
|
|
<a name="l00220"></a>00220 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#ade6dc31a79364db517a437bd49aca37a">S_VW1</a>) <span class="vhdlkeyword">begin</span>
|
| 254 |
|
|
<a name="l00221"></a>00221 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 255 |
|
|
<a name="l00222"></a>00222 <a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 256 |
|
|
<a name="l00223"></a>00223 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 257 |
|
|
<a name="l00224"></a>00224 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 258 |
|
|
<a name="l00225"></a>00225 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 259 |
|
|
<a name="l00226"></a>00226 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 260 |
|
|
<a name="l00227"></a>00227 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 261 |
|
|
<a name="l00228"></a>00228 <span class="vhdlkeyword">end</span>
|
| 262 |
|
|
<a name="l00229"></a>00229 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 263 |
|
|
<a name="l00230"></a>00230 <span class="keyword">// address, byte enables and write enables output</span>
|
| 264 |
|
|
<a name="l00231"></a>00231 <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a>;
|
| 265 |
|
|
<a name="l00232"></a>00232 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 266 |
|
|
<a name="l00233"></a>00233 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 267 |
|
|
<a name="l00234"></a>00234 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <a class="code" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">burst_write_data</a>;
|
| 268 |
|
|
<a name="l00235"></a>00235 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b1</span>;
|
| 269 |
|
|
<a name="l00236"></a>00236 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 270 |
|
|
<a name="l00237"></a>00237 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 271 |
|
|
<a name="l00238"></a>00238 <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> <= <span class="vhdllogic">4'b0000</span>;
|
| 272 |
|
|
<a name="l00239"></a>00239
|
| 273 |
|
|
<a name="l00240"></a>00240 <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> <= <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> + <span class="vhdllogic">19'd4</span>;
|
| 274 |
|
|
<a name="l00241"></a>00241 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#aae5c7e4b75f892c0a2ef5ef414122afd">S_VW2</a>;
|
| 275 |
|
|
<a name="l00242"></a>00242 <span class="vhdlkeyword">end</span>
|
| 276 |
|
|
<a name="l00243"></a>00243 <span class="vhdlkeyword">end</span>
|
| 277 |
|
|
<a name="l00244"></a>00244 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#aae5c7e4b75f892c0a2ef5ef414122afd">S_VW2</a>) <span class="vhdlkeyword">begin</span>
|
| 278 |
|
|
<a name="l00245"></a>00245 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 279 |
|
|
<a name="l00246"></a>00246 <a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 280 |
|
|
<a name="l00247"></a>00247 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 281 |
|
|
<a name="l00248"></a>00248 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 282 |
|
|
<a name="l00249"></a>00249 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 283 |
|
|
<a name="l00250"></a>00250 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 284 |
|
|
<a name="l00251"></a>00251 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 285 |
|
|
<a name="l00252"></a>00252 <span class="vhdlkeyword">end</span>
|
| 286 |
|
|
<a name="l00253"></a>00253 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 287 |
|
|
<a name="l00254"></a>00254 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 288 |
|
|
<a name="l00255"></a>00255 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 289 |
|
|
<a name="l00256"></a>00256 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <a class="code" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">burst_write_data</a>;
|
| 290 |
|
|
<a name="l00257"></a>00257
|
| 291 |
|
|
<a name="l00258"></a>00258 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a0f8b50cc59bc0120ac7813e85d4d0ca0">S_VW3</a>;
|
| 292 |
|
|
<a name="l00259"></a>00259 <span class="vhdlkeyword">end</span>
|
| 293 |
|
|
<a name="l00260"></a>00260 <span class="vhdlkeyword">end</span>
|
| 294 |
|
|
<a name="l00261"></a>00261 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a0f8b50cc59bc0120ac7813e85d4d0ca0">S_VW3</a>) <span class="vhdlkeyword">begin</span>
|
| 295 |
|
|
<a name="l00262"></a>00262 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 296 |
|
|
<a name="l00263"></a>00263 <a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 297 |
|
|
<a name="l00264"></a>00264 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 298 |
|
|
<a name="l00265"></a>00265 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 299 |
|
|
<a name="l00266"></a>00266 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 300 |
|
|
<a name="l00267"></a>00267 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 301 |
|
|
<a name="l00268"></a>00268 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 302 |
|
|
<a name="l00269"></a>00269 <span class="vhdlkeyword">end</span>
|
| 303 |
|
|
<a name="l00270"></a>00270 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 304 |
|
|
<a name="l00271"></a>00271 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <a class="code" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">burst_write_data</a>;
|
| 305 |
|
|
<a name="l00272"></a>00272
|
| 306 |
|
|
<a name="l00273"></a>00273 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a11872fcb25d808ba613e41904ff6e066">S_VW4</a>;
|
| 307 |
|
|
<a name="l00274"></a>00274 <span class="vhdlkeyword">end</span>
|
| 308 |
|
|
<a name="l00275"></a>00275 <span class="vhdlkeyword">end</span>
|
| 309 |
|
|
<a name="l00276"></a>00276 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a11872fcb25d808ba613e41904ff6e066">S_VW4</a>) <span class="vhdlkeyword">begin</span>
|
| 310 |
|
|
<a name="l00277"></a>00277 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a41716375d8a472181176cfe136044168">burst_write_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 311 |
|
|
<a name="l00278"></a>00278 <a class="code" href="classbus__ssram.html#a871283df0cea2c85cbe78c9a3f0b0e7f">burst_write_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 312 |
|
|
<a name="l00279"></a>00279 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 313 |
|
|
<a name="l00280"></a>00280 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 314 |
|
|
<a name="l00281"></a>00281 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 315 |
|
|
<a name="l00282"></a>00282 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 316 |
|
|
<a name="l00283"></a>00283 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 317 |
|
|
<a name="l00284"></a>00284 <span class="vhdlkeyword">end</span>
|
| 318 |
|
|
<a name="l00285"></a>00285 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 319 |
|
|
<a name="l00286"></a>00286 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <a class="code" href="classbus__ssram.html#a6a47c16f84aa2e8aafcf02afbc52b57b">burst_write_data</a>;
|
| 320 |
|
|
<a name="l00287"></a>00287
|
| 321 |
|
|
<a name="l00288"></a>00288 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#ade6dc31a79364db517a437bd49aca37a">S_VW1</a>;
|
| 322 |
|
|
<a name="l00289"></a>00289 <span class="vhdlkeyword">end</span>
|
| 323 |
|
|
<a name="l00290"></a>00290 <span class="vhdlkeyword">end</span>
|
| 324 |
|
|
<a name="l00291"></a>00291 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a28d6f7425ce6a8a65e69440ea64a4c29">S_VR1</a>) <span class="vhdlkeyword">begin</span>
|
| 325 |
|
|
<a name="l00292"></a>00292 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 326 |
|
|
<a name="l00293"></a>00293 <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 327 |
|
|
<a name="l00294"></a>00294 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 328 |
|
|
<a name="l00295"></a>00295 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 329 |
|
|
<a name="l00296"></a>00296 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 330 |
|
|
<a name="l00297"></a>00297 <span class="vhdlkeyword">end</span>
|
| 331 |
|
|
<a name="l00298"></a>00298 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 332 |
|
|
<a name="l00299"></a>00299 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>] == <span class="vhdllogic">2'b10</span> && <a class="code" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b1</span>;
|
| 333 |
|
|
<a name="l00300"></a>00300
|
| 334 |
|
|
<a name="l00301"></a>00301 <span class="keyword">// address and byte enables latched</span>
|
| 335 |
|
|
<a name="l00302"></a>00302 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 336 |
|
|
<a name="l00303"></a>00303 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 337 |
|
|
<a name="l00304"></a>00304
|
| 338 |
|
|
<a name="l00305"></a>00305 <a class="code" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a> <= <a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a>;
|
| 339 |
|
|
<a name="l00306"></a>00306 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#affffa409ed1f21ffe63f23c683eba531">S_VR2</a>;
|
| 340 |
|
|
<a name="l00307"></a>00307 <span class="vhdlkeyword">end</span>
|
| 341 |
|
|
<a name="l00308"></a>00308 <span class="vhdlkeyword">end</span>
|
| 342 |
|
|
<a name="l00309"></a>00309 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#affffa409ed1f21ffe63f23c683eba531">S_VR2</a>) <span class="vhdlkeyword">begin</span>
|
| 343 |
|
|
<a name="l00310"></a>00310 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 344 |
|
|
<a name="l00311"></a>00311 <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 345 |
|
|
<a name="l00312"></a>00312 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 346 |
|
|
<a name="l00313"></a>00313 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 347 |
|
|
<a name="l00314"></a>00314 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 348 |
|
|
<a name="l00315"></a>00315 <span class="vhdlkeyword">end</span>
|
| 349 |
|
|
<a name="l00316"></a>00316 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 350 |
|
|
<a name="l00317"></a>00317 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b1</span>;
|
| 351 |
|
|
<a name="l00318"></a>00318
|
| 352 |
|
|
<a name="l00319"></a>00319 <span class="keyword">// output enable output</span>
|
| 353 |
|
|
<a name="l00320"></a>00320 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 354 |
|
|
<a name="l00321"></a>00321
|
| 355 |
|
|
<a name="l00322"></a>00322 <a class="code" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a> <= <a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a>;
|
| 356 |
|
|
<a name="l00323"></a>00323 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a087aee8fa77cb6c2f662118321e09871">S_VR3</a>;
|
| 357 |
|
|
<a name="l00324"></a>00324 <span class="vhdlkeyword">end</span>
|
| 358 |
|
|
<a name="l00325"></a>00325 <span class="vhdlkeyword">end</span>
|
| 359 |
|
|
<a name="l00326"></a>00326 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a087aee8fa77cb6c2f662118321e09871">S_VR3</a>) <span class="vhdlkeyword">begin</span>
|
| 360 |
|
|
<a name="l00327"></a>00327 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 361 |
|
|
<a name="l00328"></a>00328 <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 362 |
|
|
<a name="l00329"></a>00329 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 363 |
|
|
<a name="l00330"></a>00330 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 364 |
|
|
<a name="l00331"></a>00331 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 365 |
|
|
<a name="l00332"></a>00332 <span class="vhdlkeyword">end</span>
|
| 366 |
|
|
<a name="l00333"></a>00333 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 367 |
|
|
<a name="l00334"></a>00334 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>] == <span class="vhdllogic">2'b00</span>) <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b1</span>;
|
| 368 |
|
|
<a name="l00335"></a>00335
|
| 369 |
|
|
<a name="l00336"></a>00336 <a class="code" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a> <= <a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a>;
|
| 370 |
|
|
<a name="l00337"></a>00337 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a007e4900fdab9ae822d87670bdebfb0a">S_VR4</a>;
|
| 371 |
|
|
<a name="l00338"></a>00338 <span class="vhdlkeyword">end</span>
|
| 372 |
|
|
<a name="l00339"></a>00339 <span class="vhdlkeyword">end</span>
|
| 373 |
|
|
<a name="l00340"></a>00340 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a007e4900fdab9ae822d87670bdebfb0a">S_VR4</a>) <span class="vhdlkeyword">begin</span>
|
| 374 |
|
|
<a name="l00341"></a>00341 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a4ec3a06c44c4a4bd8f83b27bce22cc6a">burst_read_request</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 375 |
|
|
<a name="l00342"></a>00342 <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b0</span>;
|
| 376 |
|
|
<a name="l00343"></a>00343 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 377 |
|
|
<a name="l00344"></a>00344 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 378 |
|
|
<a name="l00345"></a>00345 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>;
|
| 379 |
|
|
<a name="l00346"></a>00346 <span class="vhdlkeyword">end</span>
|
| 380 |
|
|
<a name="l00347"></a>00347 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 381 |
|
|
<a name="l00348"></a>00348 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#ac5e689c9e42fe9b1335117fd5df37775">burst_read_low_address</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">2</span>] == <span class="vhdllogic">2'b01</span>) <a class="code" href="classbus__ssram.html#a129b5bd32f618b59b3e59264de9726e5">burst_read_ready</a> <= <span class="vhdllogic">1'b1</span>;
|
| 382 |
|
|
<a name="l00349"></a>00349 <a class="code" href="classbus__ssram.html#a4bb8b3742d85ee88a72833d1facf6d4f">burst_read_one_loop</a> <= <span class="vhdllogic">1'b1</span>;
|
| 383 |
|
|
<a name="l00350"></a>00350
|
| 384 |
|
|
<a name="l00351"></a>00351 <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a>;
|
| 385 |
|
|
<a name="l00352"></a>00352 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 386 |
|
|
<a name="l00353"></a>00353 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 387 |
|
|
<a name="l00354"></a>00354
|
| 388 |
|
|
<a name="l00355"></a>00355 <a class="code" href="classbus__ssram.html#ae09f95f879e5dbaeaf569cd7b7949acd">burst_read_data</a> <= <a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a>;
|
| 389 |
|
|
<a name="l00356"></a>00356 <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> <= <a class="code" href="classbus__ssram.html#a535aefa25808f58b42ac5a1654d56610">burst_address</a> + <span class="vhdllogic">19'd4</span>;
|
| 390 |
|
|
<a name="l00357"></a>00357 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a28d6f7425ce6a8a65e69440ea64a4c29">S_VR1</a>;
|
| 391 |
|
|
<a name="l00358"></a>00358 <span class="vhdlkeyword">end</span>
|
| 392 |
|
|
<a name="l00359"></a>00359 <span class="vhdlkeyword">end</span>
|
| 393 |
|
|
<a name="l00360"></a>00360 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a90be4e0d49e4873179cfef106dfca57b">S_R1</a>) <span class="vhdlkeyword">begin</span>
|
| 394 |
|
|
<a name="l00361"></a>00361 <span class="keyword">// address and byte enables latched</span>
|
| 395 |
|
|
<a name="l00362"></a>00362 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 396 |
|
|
<a name="l00363"></a>00363 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 397 |
|
|
<a name="l00364"></a>00364
|
| 398 |
|
|
<a name="l00365"></a>00365 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#ae6ed87aa25e02712ed883f69c55a5c08">S_R2</a>;
|
| 399 |
|
|
<a name="l00366"></a>00366 <span class="vhdlkeyword">end</span>
|
| 400 |
|
|
<a name="l00367"></a>00367 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#ae6ed87aa25e02712ed883f69c55a5c08">S_R2</a>) <span class="vhdlkeyword">begin</span>
|
| 401 |
|
|
<a name="l00368"></a>00368 <span class="keyword">// output enable output</span>
|
| 402 |
|
|
<a name="l00369"></a>00369 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b0</span>;
|
| 403 |
|
|
<a name="l00370"></a>00370
|
| 404 |
|
|
<a name="l00371"></a>00371 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#aa5e59d0bad76d805d61cfcd307af35f8">S_R3</a>;
|
| 405 |
|
|
<a name="l00372"></a>00372 <span class="vhdlkeyword">end</span>
|
| 406 |
|
|
<a name="l00373"></a>00373 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#aa5e59d0bad76d805d61cfcd307af35f8">S_R3</a>) <span class="vhdlkeyword">begin</span>
|
| 407 |
|
|
<a name="l00374"></a>00374 <a class="code" href="classbus__ssram.html#a78163aefbe6bb0d6f809c7e01b93967b">DAT_O</a> <= <a class="code" href="classbus__ssram.html#ad69f5f977e8c5fb7875d1a69fee22d72">ssram_data</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 408 |
|
|
<a name="l00375"></a>00375 <a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 409 |
|
|
<a name="l00376"></a>00376
|
| 410 |
|
|
<a name="l00377"></a>00377 <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= <span class="vhdllogic">19'd0</span>;
|
| 411 |
|
|
<a name="l00378"></a>00378 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 412 |
|
|
<a name="l00379"></a>00379 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 413 |
|
|
<a name="l00380"></a>00380 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <span class="vhdllogic">36'd0</span>;
|
| 414 |
|
|
<a name="l00381"></a>00381 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 415 |
|
|
<a name="l00382"></a>00382 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 416 |
|
|
<a name="l00383"></a>00383 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 417 |
|
|
<a name="l00384"></a>00384 <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 418 |
|
|
<a name="l00385"></a>00385
|
| 419 |
|
|
<a name="l00386"></a>00386 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a858c46d836e9106fd17cfcae0529039e">S_IDLE</a>;
|
| 420 |
|
|
<a name="l00387"></a>00387 <span class="vhdlkeyword">end</span>
|
| 421 |
|
|
<a name="l00388"></a>00388 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> == <a class="code" href="classbus__ssram.html#a70126e90d300698baa7aac32dbb7bdc0">S_PRE_IDLE</a>) <span class="vhdlkeyword">begin</span>
|
| 422 |
|
|
<a name="l00389"></a>00389 <a class="code" href="classbus__ssram.html#af87a2d46e88cd2ccf90487f261366aba">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 423 |
|
|
<a name="l00390"></a>00390
|
| 424 |
|
|
<a name="l00391"></a>00391 <a class="code" href="classbus__ssram.html#a28c27b19916c54b3e868369aac6f6b9a">ssram_address</a> <= <span class="vhdllogic">19'd0</span>;
|
| 425 |
|
|
<a name="l00392"></a>00392 <a class="code" href="classbus__ssram.html#a21d0bd68b7b790eb45a03c6992c92a9f">ssram_adsc_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 426 |
|
|
<a name="l00393"></a>00393 <a class="code" href="classbus__ssram.html#acea0b5e48c266c75112e372048947204">ssram_advance_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 427 |
|
|
<a name="l00394"></a>00394 <a class="code" href="classbus__ssram.html#a3493866f2c0fa328bc914ee77192bf2e">ssram_data_reg</a> <= <span class="vhdllogic">36'd0</span>;
|
| 428 |
|
|
<a name="l00395"></a>00395 <a class="code" href="classbus__ssram.html#af1d128d90eced18c7e7f2789ac9046a9">ssram_data_oe</a> <= <span class="vhdllogic">1'b0</span>;
|
| 429 |
|
|
<a name="l00396"></a>00396 <a class="code" href="classbus__ssram.html#ac105e20d6da178b2822b3e87238ae6dc">ssram_oe_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 430 |
|
|
<a name="l00397"></a>00397 <a class="code" href="classbus__ssram.html#a99f42b3013302ad54129da325e2c0410">ssram_writeen_n</a> <= <span class="vhdllogic">1'b1</span>;
|
| 431 |
|
|
<a name="l00398"></a>00398 <a class="code" href="classbus__ssram.html#a66f9e3c03173432f2950e141e42e47ee">ssram_byteen_n</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 432 |
|
|
<a name="l00399"></a>00399
|
| 433 |
|
|
<a name="l00400"></a>00400 <a class="code" href="classbus__ssram.html#a07ff3477e013ed4dfa2439589c118202">state</a> <= <a class="code" href="classbus__ssram.html#a858c46d836e9106fd17cfcae0529039e">S_IDLE</a>;
|
| 434 |
|
|
<a name="l00401"></a>00401 <span class="vhdlkeyword">end</span>
|
| 435 |
|
|
<a name="l00402"></a>00402 <span class="vhdlkeyword">end</span>
|
| 436 |
|
|
<a name="l00403"></a>00403
|
| 437 |
|
|
<a name="l00404"></a>00404 <span class="vhdlkeyword">endmodule</span>
|
| 438 |
|
|
</pre></div></div>
|
| 439 |
|
|
</div>
|
| 440 |
|
|
<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:18 for aoOCS by 
|
| 441 |
|
|
<a href="http://www.doxygen.org/index.html">
|
| 442 |
|
|
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
|
| 443 |
|
|
</body>
|
| 444 |
|
|
</html>
|
