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<h1>bus_terminator.v</h1> </div>
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<div class="contents">
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<a href="bus__terminator_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">/*</span>
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<a name="l00002"></a>00002 <span class="keyword"> Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.</span>
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<a name="l00003"></a>00003 <span class="keyword"> </span>
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<a name="l00004"></a>00004 <span class="keyword"> Redistribution and use in source and binary forms, with or without modification, are</span>
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<a name="l00005"></a>00005 <span class="keyword"> permitted provided that the following conditions are met:</span>
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<a name="l00006"></a>00006 <span class="keyword"> </span>
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36 |
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<a name="l00007"></a>00007 <span class="keyword"> 1. Redistributions of source code must retain the above copyright notice, this list of</span>
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37 |
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<a name="l00008"></a>00008 <span class="keyword"> conditions and the following disclaimer.</span>
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38 |
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<a name="l00009"></a>00009 <span class="keyword"> </span>
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<a name="l00010"></a>00010 <span class="keyword"> 2. Redistributions in binary form must reproduce the above copyright notice, this list</span>
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<a name="l00011"></a>00011 <span class="keyword"> of conditions and the following disclaimer in the documentation and/or other materials</span>
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41 |
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<a name="l00012"></a>00012 <span class="keyword"> provided with the distribution.</span>
|
42 |
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<a name="l00013"></a>00013 <span class="keyword"> </span>
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<a name="l00014"></a>00014 <span class="keyword"> THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED</span>
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44 |
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<a name="l00015"></a>00015 <span class="keyword"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND</span>
|
45 |
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<a name="l00016"></a>00016 <span class="keyword"> FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR</span>
|
46 |
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<a name="l00017"></a>00017 <span class="keyword"> CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span>
|
47 |
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<a name="l00018"></a>00018 <span class="keyword"> CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR</span>
|
48 |
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<a name="l00019"></a>00019 <span class="keyword"> SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON</span>
|
49 |
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<a name="l00020"></a>00020 <span class="keyword"> ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING</span>
|
50 |
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<a name="l00021"></a>00021 <span class="keyword"> NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF</span>
|
51 |
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<a name="l00022"></a>00022 <span class="keyword"> ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span>
|
52 |
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<a name="l00023"></a>00023 <span class="keyword"> */</span>
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53 |
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<a name="l00024"></a>00024
|
54 |
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<a name="l00025"></a>00025 <span class="keyword">/*! \file</span>
|
55 |
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<a name="l00026"></a>00026 <span class="keyword"> \brief Terminator for not handled WISHBONE bus cycles.</span>
|
56 |
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<a name="l00027"></a>00027 <span class="keyword"> */</span>
|
57 |
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<a name="l00028"></a>00028
|
58 |
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<a name="l00029"></a>00029 <span class="keyword">/*! \brief \copybrief bus_terminator.v</span>
|
59 |
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<a name="l00030"></a>00030 <span class="keyword">*/</span>
|
60 |
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<a name="l00031"></a><a class="code" href="classbus__terminator.html">00031</a> <span class="vhdlkeyword">module</span> <a class="code" href="classbus__terminator.html">bus_terminator</a>(
|
61 |
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<a name="l00032"></a>00032 <span class="keyword">//% \name Clock and reset
|
62 |
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</span>
|
63 |
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<a name="l00033"></a>00033 <span class="keyword">//% @{</span>
|
64 |
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<a name="l00034"></a><a class="code" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">00034</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a>,
|
65 |
|
|
<a name="l00035"></a><a class="code" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">00035</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a>,
|
66 |
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|
<a name="l00036"></a>00036 <span class="keyword">//% @}</span>
|
67 |
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<a name="l00037"></a>00037
|
68 |
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<a name="l00038"></a>00038 <span class="keyword">//% \name WISHBONE slave
|
69 |
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</span>
|
70 |
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<a name="l00039"></a>00039 <span class="keyword">//% @{</span>
|
71 |
|
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<a name="l00040"></a><a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">00040</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>,
|
72 |
|
|
<a name="l00041"></a><a class="code" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">00041</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">CYC_I</a>,
|
73 |
|
|
<a name="l00042"></a><a class="code" href="classbus__terminator.html#a31e187f84a3ea1a4e4cd377141a3f19e">00042</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__terminator.html#a31e187f84a3ea1a4e4cd377141a3f19e">WE_I</a>,
|
74 |
|
|
<a name="l00043"></a><a class="code" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">00043</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">STB_I</a>,
|
75 |
|
|
<a name="l00044"></a><a class="code" href="classbus__terminator.html#a994f936ec3b678f3e4bff3cfa2256390">00044</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__terminator.html#a994f936ec3b678f3e4bff3cfa2256390">SEL_I</a>,
|
76 |
|
|
<a name="l00045"></a><a class="code" href="classbus__terminator.html#a00620d44f29f18431e1b9e2a889f72a9">00045</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__terminator.html#a00620d44f29f18431e1b9e2a889f72a9">slave_DAT_I</a>,
|
77 |
|
|
<a name="l00046"></a><a class="code" href="classbus__terminator.html#a398652206e0fb61250ca64834cc4c825">00046</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classbus__terminator.html#a398652206e0fb61250ca64834cc4c825">slave_DAT_O</a>,
|
78 |
|
|
<a name="l00047"></a><a class="code" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">00047</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a>,
|
79 |
|
|
<a name="l00048"></a><a class="code" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">00048</a> <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a>,
|
80 |
|
|
<a name="l00049"></a><a class="code" href="classbus__terminator.html#a9b755e92f028d4f9a9534124fbc73913">00049</a> <span class="vhdlkeyword">output</span> <a class="code" href="classbus__terminator.html#a9b755e92f028d4f9a9534124fbc73913">ERR_O</a>,
|
81 |
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<a name="l00050"></a>00050 <span class="keyword">//% @}</span>
|
82 |
|
|
<a name="l00051"></a>00051
|
83 |
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<a name="l00052"></a>00052 <span class="keyword">//% \name ao68000 interrupt cycle indicator
|
84 |
|
|
</span>
|
85 |
|
|
<a name="l00053"></a>00053 <span class="keyword">//% @{</span>
|
86 |
|
|
<a name="l00054"></a><a class="code" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">00054</a> <span class="vhdlkeyword">input</span> <a class="code" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">cpu_space_cycle</a>
|
87 |
|
|
<a name="l00055"></a>00055 <span class="keyword">//% @}</span>
|
88 |
|
|
<a name="l00056"></a>00056 );
|
89 |
|
|
<a name="l00057"></a>00057
|
90 |
|
|
<a name="l00058"></a>00058 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__terminator.html#a9b755e92f028d4f9a9534124fbc73913">ERR_O</a> = <span class="vhdllogic">1'b0</span>;
|
91 |
|
|
<a name="l00059"></a>00059 <span class="vhdlkeyword">assign</span> <a class="code" href="classbus__terminator.html#a398652206e0fb61250ca64834cc4c825">slave_DAT_O</a> = <span class="vhdllogic">32'd0</span>;
|
92 |
|
|
<a name="l00060"></a>00060
|
93 |
|
|
<a name="l00061"></a><a class="code" href="classbus__terminator.html#aefdadc25d9b399769ec9b68788ce1aab">00061</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classbus__terminator.html#aefdadc25d9b399769ec9b68788ce1aab">accepted_addresses</a> =
|
94 |
|
|
<a name="l00062"></a>00062 ({<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} >= <span class="vhdllogic">32'h00F00000</span> && {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} <= <span class="vhdllogic">32'h00F7FFFC</span>) ||
|
95 |
|
|
<a name="l00063"></a>00063 ({<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} >= <span class="vhdllogic">32'h00E80000</span> && {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} <= <span class="vhdllogic">32'h00EFFFFC</span>) ||
|
96 |
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|
<a name="l00064"></a>00064 <span class="keyword">// Lotus2</span>
|
97 |
|
|
<a name="l00065"></a>00065 ({<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} >= <span class="vhdllogic">32'h00200000</span> && {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} <= <span class="vhdllogic">32'h009FFFFF</span>) ||
|
98 |
|
|
<a name="l00066"></a>00066 <span class="keyword">// Pinball Dreams</span>
|
99 |
|
|
<a name="l00067"></a>00067 {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} == <span class="vhdllogic">32'h00DFF11C</span> ||
|
100 |
|
|
<a name="l00068"></a>00068
|
101 |
|
|
<a name="l00069"></a>00069 {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} == <span class="vhdllogic">32'h00DFF1FC</span> ||
|
102 |
|
|
<a name="l00070"></a>00070 {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} == <span class="vhdllogic">32'h00DFF0FC</span> ||
|
103 |
|
|
<a name="l00071"></a>00071 {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} == <span class="vhdllogic">32'h00DC003C</span> ||
|
104 |
|
|
<a name="l00072"></a>00072 {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} == <span class="vhdllogic">32'h00D8003C</span> ||
|
105 |
|
|
<a name="l00073"></a>00073 {<a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>, <span class="vhdllogic">2'b00</span>} == <span class="vhdllogic">32'hFFFFFFFC</span>;
|
106 |
|
|
<a name="l00074"></a>00074
|
107 |
|
|
<a name="l00075"></a><a class="code" href="classbus__terminator.html#a0c661acb3f7be5a11a46134c7fb9d7b2">00075</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
108 |
|
|
<a name="l00076"></a>00076 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
109 |
|
|
<a name="l00077"></a>00077 <a class="code" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
110 |
|
|
<a name="l00078"></a>00078 <a class="code" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a> <= <span class="vhdllogic">1'b0</span>;
|
111 |
|
|
<a name="l00079"></a>00079 <span class="vhdlkeyword">end</span>
|
112 |
|
|
<a name="l00080"></a>00080 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
113 |
|
|
<a name="l00081"></a>00081 <span class="vhdlkeyword">if</span>( <a class="code" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">cpu_space_cycle</a> == <span class="vhdllogic">1'b0</span> &&
|
114 |
|
|
<a name="l00082"></a>00082 <a class="code" href="classbus__terminator.html#aefdadc25d9b399769ec9b68788ce1aab">accepted_addresses</a> == <span class="vhdllogic">1'b1</span> &&
|
115 |
|
|
<a name="l00083"></a>00083 <a class="code" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
116 |
|
|
<a name="l00084"></a>00084 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
117 |
|
|
<a name="l00085"></a>00085
|
118 |
|
|
<a name="l00086"></a>00086 <span class="vhdlkeyword">if</span>( <a class="code" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">cpu_space_cycle</a> == <span class="vhdllogic">1'b1</span> &&
|
119 |
|
|
<a name="l00087"></a>00087 <a class="code" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">5</span>] == <span class="vhdllogic">27'b111_1111_1111_1111_1111_1111_1111</span> &&
|
120 |
|
|
<a name="l00088"></a>00088 <a class="code" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">CYC_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">STB_I</a> == <span class="vhdllogic">1'b1</span> && <a class="code" href="classbus__terminator.html#a31e187f84a3ea1a4e4cd377141a3f19e">WE_I</a> == <span class="vhdllogic">1'b0</span>)
|
121 |
|
|
<a name="l00089"></a>00089 <span class="vhdlkeyword">begin</span>
|
122 |
|
|
<a name="l00090"></a>00090 <a class="code" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a> <= <span class="vhdllogic">1'b1</span>;
|
123 |
|
|
<a name="l00091"></a>00091 <span class="vhdlkeyword">end</span>
|
124 |
|
|
<a name="l00092"></a>00092 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
125 |
|
|
<a name="l00093"></a>00093 <a class="code" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a> <= <span class="vhdllogic">1'b0</span>;
|
126 |
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<a name="l00094"></a>00094 <span class="vhdlkeyword">end</span>
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<a name="l00095"></a>00095 <span class="vhdlkeyword">end</span>
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<a name="l00096"></a>00096 <span class="vhdlkeyword">end</span>
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<a name="l00097"></a>00097
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<a name="l00098"></a>00098 <span class="vhdlkeyword">endmodule</span>
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</pre></div></div>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:18 for aoOCS by 
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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