OpenCores
URL https://opencores.org/ocsvn/aoocs/aoocs/trunk

Subversion Repositories aoocs

[/] [aoocs/] [trunk/] [doc/] [doxygen/] [html/] [classbus__terminator.html] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik 
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
2 
<html xmlns="http://www.w3.org/1999/xhtml">
3 
<head>
4 
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
5 
<title>aoOCS: bus_terminator Module Reference</title>
6 
<link href="tabs.css" rel="stylesheet" type="text/css"/>
7 
<link href="doxygen.css" rel="stylesheet" type="text/css"/>
8 
</head>
9 
<body>
10 
<!-- Generated by Doxygen 1.7.2 -->
11 
<div class="navigation" id="top">
12 
  <div class="tabs">
13 
    <ul class="tablist">
14 
      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
15 
      <li class="current"><a href="annotated.html"><span>Design&#160;Unit&#160;List</span></a></li>
16 
      <li><a href="files.html"><span>Files</span></a></li>
17 
    </ul>
18 
  </div>
19 
  <div class="tabs2">
20 
    <ul class="tablist">
21 
      <li><a href="annotated.html"><span>Class&#160;List</span></a></li>
22 
      <li><a href="hierarchy.html"><span>Design&#160;Unit&#160;Hierarchy</span></a></li>
23 
      <li><a href="functions.html"><span>Design&#160;Unit&#160;Members</span></a></li>
24 
    </ul>
25 
  </div>
26 
</div>
27 
<div class="header">
28 
  <div class="summary">
29 
<a href="#Inputs">Inputs</a> &#124;
30 
<a href="#Outputs">Outputs</a> &#124;
31 
<a href="#Signals">Signals</a> &#124;
32 
<a href="#Always Constructs">Always Constructs</a>  </div>
33 
  <div class="headertitle">
34 
<h1>bus_terminator Module Reference</h1>  </div>
35 
</div>
36 
<div class="contents">
37 
<!-- doxytag: class="bus_terminator" -->
38 
<p><p>Terminator for not handled WISHBONE bus cycles. </p>
39 
 
40 
<a href="#_details">More...</a></p>
41 
<!-- startSectionHeader --><div class="dynheader">
42 
Inheritance diagram for bus_terminator:<!-- endSectionHeader --></div>
43 
<!-- startSectionSummary --><!-- endSectionSummary --><!-- startSectionContent --><div class="dyncontent">
44 
 <div class="center">
45 
  <img src="classbus__terminator.png" usemap="#bus_terminator_map" alt=""/>
46 
  <map id="bus_terminator_map" name="bus_terminator_map">
47 
<area href="classaoOCS.html" alt="aoOCS" shape="rect" coords="0,56,95,80"/>
48 
</map>
49 
 </div><!-- endSectionContent --></div>
50 
 
51 
<p><a href="classbus__terminator-members.html">List of all members.</a></p>
52 
<table class="memberdecls">
53 
<tr><td colspan="2"><h2><a name="Always Constructs"></a>
54 
Always Constructs</h2></td></tr>
55 
 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a0c661acb3f7be5a11a46134c7fb9d7b2">ALWAYS_34</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
56 
<tr><td colspan="2"><h2><a name="Inputs"></a>
57 
Inputs</h2></td></tr>
58 
 <tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
59 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
60 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
61 
<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
62 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
63 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">CYC_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
64 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a31e187f84a3ea1a4e4cd377141a3f19e">WE_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
65 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">STB_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
66 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a994f936ec3b678f3e4bff3cfa2256390">SEL_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
67 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a00620d44f29f18431e1b9e2a889f72a9">slave_DAT_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
68 
<tr><td colspan="2"><div class="groupHeader">ao68000 interrupt cycle indicator</div></td></tr>
69 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">cpu_space_cycle</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
70 
<tr><td colspan="2"><h2><a name="Outputs"></a>
71 
Outputs</h2></td></tr>
72 
 <tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
73 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a398652206e0fb61250ca64834cc4c825">slave_DAT_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
74 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
75 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
76 
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__terminator.html#a9b755e92f028d4f9a9534124fbc73913">ERR_O</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
77 
<tr><td colspan="2"><h2><a name="Signals"></a>
78 
Signals</h2></td></tr>
79 
 <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__terminator.html#aefdadc25d9b399769ec9b68788ce1aab">accepted_addresses</a> </td></tr>
80 
</table>
81 
<hr/><a name="_details"></a><h2>Detailed Description</h2>
82 
<p>Terminator for not handled WISHBONE bus cycles. </p>
83 
 
84 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00031">31</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
85 
<hr/><h2>Member Function Documentation</h2>
86 
<a class="anchor" id="a0c661acb3f7be5a11a46134c7fb9d7b2"></a><!-- doxytag: member="bus_terminator::ALWAYS_34" ref="a0c661acb3f7be5a11a46134c7fb9d7b2" args="CLK_I, reset_n" -->
87 
<div class="memitem">
88 
<div class="memproto">
89 
      <table class="memname">
90 
        <tr>
91 
          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_34          <td></td>
92 
          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
93 
        </tr>
94 
        <tr>
95 
          <td class="paramkey"></td>
96 
          <td></td>
97 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
98 
        </tr>
99 
<code> [Always Construct]</code></td>
100 
        </tr>
101 
      </table>
102 
</div>
103 
<div class="memdoc">
104 
 
105 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00075">75</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
106 
 
107 
</div>
108 
</div>
109 
<hr/><h2>Member Data Documentation</h2>
110 
<a class="anchor" id="a504389b095a9baf2f88945340e64c4ab"></a><!-- doxytag: member="bus_terminator::CLK_I" ref="a504389b095a9baf2f88945340e64c4ab" args="" -->
111 
<div class="memitem">
112 
<div class="memproto">
113 
      <table class="memname">
114 
        <tr>
115 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a504389b095a9baf2f88945340e64c4ab">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
116 
        </tr>
117 
      </table>
118 
</div>
119 
<div class="memdoc">
120 
 
121 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00034">34</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
122 
 
123 
</div>
124 
</div>
125 
<a class="anchor" id="a0e510f9c4f5e9af32ea1636b00cfb952"></a><!-- doxytag: member="bus_terminator::reset_n" ref="a0e510f9c4f5e9af32ea1636b00cfb952" args="" -->
126 
<div class="memitem">
127 
<div class="memproto">
128 
      <table class="memname">
129 
        <tr>
130 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a0e510f9c4f5e9af32ea1636b00cfb952">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
131 
        </tr>
132 
      </table>
133 
</div>
134 
<div class="memdoc">
135 
 
136 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00035">35</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
137 
 
138 
</div>
139 
</div>
140 
<a class="anchor" id="ae78ac8eb886aa627384f63905a5e29e5"></a><!-- doxytag: member="bus_terminator::ADR_I" ref="ae78ac8eb886aa627384f63905a5e29e5" args="" -->
141 
<div class="memitem">
142 
<div class="memproto">
143 
      <table class="memname">
144 
        <tr>
145 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#ae78ac8eb886aa627384f63905a5e29e5">ADR_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
146 
        </tr>
147 
      </table>
148 
</div>
149 
<div class="memdoc">
150 
 
151 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00040">40</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
152 
 
153 
</div>
154 
</div>
155 
<a class="anchor" id="a596ac126fa1168b2d59936d3c9778deb"></a><!-- doxytag: member="bus_terminator::CYC_I" ref="a596ac126fa1168b2d59936d3c9778deb" args="" -->
156 
<div class="memitem">
157 
<div class="memproto">
158 
      <table class="memname">
159 
        <tr>
160 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a596ac126fa1168b2d59936d3c9778deb">CYC_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
161 
        </tr>
162 
      </table>
163 
</div>
164 
<div class="memdoc">
165 
 
166 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00041">41</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
167 
 
168 
</div>
169 
</div>
170 
<a class="anchor" id="a31e187f84a3ea1a4e4cd377141a3f19e"></a><!-- doxytag: member="bus_terminator::WE_I" ref="a31e187f84a3ea1a4e4cd377141a3f19e" args="" -->
171 
<div class="memitem">
172 
<div class="memproto">
173 
      <table class="memname">
174 
        <tr>
175 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a31e187f84a3ea1a4e4cd377141a3f19e">WE_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
176 
        </tr>
177 
      </table>
178 
</div>
179 
<div class="memdoc">
180 
 
181 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00042">42</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
182 
 
183 
</div>
184 
</div>
185 
<a class="anchor" id="ae3ce51f791c566e098e7d558290e7366"></a><!-- doxytag: member="bus_terminator::STB_I" ref="ae3ce51f791c566e098e7d558290e7366" args="" -->
186 
<div class="memitem">
187 
<div class="memproto">
188 
      <table class="memname">
189 
        <tr>
190 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#ae3ce51f791c566e098e7d558290e7366">STB_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
191 
        </tr>
192 
      </table>
193 
</div>
194 
<div class="memdoc">
195 
 
196 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00043">43</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
197 
 
198 
</div>
199 
</div>
200 
<a class="anchor" id="a994f936ec3b678f3e4bff3cfa2256390"></a><!-- doxytag: member="bus_terminator::SEL_I" ref="a994f936ec3b678f3e4bff3cfa2256390" args="" -->
201 
<div class="memitem">
202 
<div class="memproto">
203 
      <table class="memname">
204 
        <tr>
205 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a994f936ec3b678f3e4bff3cfa2256390">SEL_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
206 
        </tr>
207 
      </table>
208 
</div>
209 
<div class="memdoc">
210 
 
211 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00044">44</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
212 
 
213 
</div>
214 
</div>
215 
<a class="anchor" id="a00620d44f29f18431e1b9e2a889f72a9"></a><!-- doxytag: member="bus_terminator::slave_DAT_I" ref="a00620d44f29f18431e1b9e2a889f72a9" args="" -->
216 
<div class="memitem">
217 
<div class="memproto">
218 
      <table class="memname">
219 
        <tr>
220 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a00620d44f29f18431e1b9e2a889f72a9">slave_DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
221 
        </tr>
222 
      </table>
223 
</div>
224 
<div class="memdoc">
225 
 
226 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00045">45</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
227 
 
228 
</div>
229 
</div>
230 
<a class="anchor" id="a398652206e0fb61250ca64834cc4c825"></a><!-- doxytag: member="bus_terminator::slave_DAT_O" ref="a398652206e0fb61250ca64834cc4c825" args="" -->
231 
<div class="memitem">
232 
<div class="memproto">
233 
      <table class="memname">
234 
        <tr>
235 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a398652206e0fb61250ca64834cc4c825">slave_DAT_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
236 
        </tr>
237 
      </table>
238 
</div>
239 
<div class="memdoc">
240 
 
241 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00046">46</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
242 
 
243 
</div>
244 
</div>
245 
<a class="anchor" id="aa6bce0ee76b21cf32566499eb19c2861"></a><!-- doxytag: member="bus_terminator::ACK_O" ref="aa6bce0ee76b21cf32566499eb19c2861" args="" -->
246 
<div class="memitem">
247 
<div class="memproto">
248 
      <table class="memname">
249 
        <tr>
250 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#aa6bce0ee76b21cf32566499eb19c2861">ACK_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
251 
        </tr>
252 
      </table>
253 
</div>
254 
<div class="memdoc">
255 
 
256 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00047">47</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
257 
 
258 
</div>
259 
</div>
260 
<a class="anchor" id="af69c7a0cbf74d76a0736a758ee74c7f1"></a><!-- doxytag: member="bus_terminator::RTY_O" ref="af69c7a0cbf74d76a0736a758ee74c7f1" args="" -->
261 
<div class="memitem">
262 
<div class="memproto">
263 
      <table class="memname">
264 
        <tr>
265 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#af69c7a0cbf74d76a0736a758ee74c7f1">RTY_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
266 
        </tr>
267 
      </table>
268 
</div>
269 
<div class="memdoc">
270 
 
271 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00048">48</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
272 
 
273 
</div>
274 
</div>
275 
<a class="anchor" id="a9b755e92f028d4f9a9534124fbc73913"></a><!-- doxytag: member="bus_terminator::ERR_O" ref="a9b755e92f028d4f9a9534124fbc73913" args="" -->
276 
<div class="memitem">
277 
<div class="memproto">
278 
      <table class="memname">
279 
        <tr>
280 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#a9b755e92f028d4f9a9534124fbc73913">ERR_O</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
281 
        </tr>
282 
      </table>
283 
</div>
284 
<div class="memdoc">
285 
 
286 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00049">49</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
287 
 
288 
</div>
289 
</div>
290 
<a class="anchor" id="ab33b4e390a6cca8ffc2af080d219b48a"></a><!-- doxytag: member="bus_terminator::cpu_space_cycle" ref="ab33b4e390a6cca8ffc2af080d219b48a" args="" -->
291 
<div class="memitem">
292 
<div class="memproto">
293 
      <table class="memname">
294 
        <tr>
295 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#ab33b4e390a6cca8ffc2af080d219b48a">cpu_space_cycle</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
296 
        </tr>
297 
      </table>
298 
</div>
299 
<div class="memdoc">
300 
 
301 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00054">54</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
302 
 
303 
</div>
304 
</div>
305 
<a class="anchor" id="aefdadc25d9b399769ec9b68788ce1aab"></a><!-- doxytag: member="bus_terminator::accepted_addresses" ref="aefdadc25d9b399769ec9b68788ce1aab" args="wire" -->
306 
<div class="memitem">
307 
<div class="memproto">
308 
      <table class="memname">
309 
        <tr>
310 
          <td class="memname"><span class="stringliteral"><a class="el" href="classbus__terminator.html#aefdadc25d9b399769ec9b68788ce1aab">accepted_addresses</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
311 
        </tr>
312 
      </table>
313 
</div>
314 
<div class="memdoc">
315 
 
316 
<p>Definition at line <a class="el" href="bus__terminator_8v_source.html#l00061">61</a> of file <a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a>.</p>
317 
 
318 
</div>
319 
</div>
320 
<hr/>The documentation for this class was generated from the following file:<ul>
321 
<li><a class="el" href="bus__terminator_8v_source.html">bus_terminator.v</a></li>
322 
</ul>
323 
</div>
324 
<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by&#160;
325 
<a href="http://www.doxygen.org/index.html">
326 
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
327 
</body>
328 
</html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.