OpenCores
URL https://opencores.org/ocsvn/aoocs/aoocs/trunk

Subversion Repositories aoocs

[/] [aoocs/] [trunk/] [doc/] [doxygen/] [html/] [classdrv__eth__vga__capture-members.html] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
2
<html xmlns="http://www.w3.org/1999/xhtml">
3
<head>
4
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
5
<title>aoOCS: Member List</title>
6
<link href="tabs.css" rel="stylesheet" type="text/css"/>
7
<link href="doxygen.css" rel="stylesheet" type="text/css"/>
8
</head>
9
<body>
10
<!-- Generated by Doxygen 1.7.2 -->
11
<div class="navigation" id="top">
12
  <div class="tabs">
13
    <ul class="tablist">
14
      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
15
      <li class="current"><a href="annotated.html"><span>Design&#160;Unit&#160;List</span></a></li>
16
      <li><a href="files.html"><span>Files</span></a></li>
17
    </ul>
18
  </div>
19
  <div class="tabs2">
20
    <ul class="tablist">
21
      <li><a href="annotated.html"><span>Class&#160;List</span></a></li>
22
      <li><a href="hierarchy.html"><span>Design&#160;Unit&#160;Hierarchy</span></a></li>
23
      <li><a href="functions.html"><span>Design&#160;Unit&#160;Members</span></a></li>
24
    </ul>
25
  </div>
26
</div>
27
<div class="header">
28
  <div class="headertitle">
29
<h1>drv_eth_vga_capture Member List</h1>  </div>
30
</div>
31
<div class="contents">
32
This is the complete list of members for <a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a>, including all inherited members.<table>
33
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a26c09de4c12b15a080f22caec2384eee">clk_30</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
34
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a4be6e1a59f945fb87af42e8d7336216a">clk_25</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
35
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a7b4e1c4a172b419f95f9874295abca61">reset_n</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
36
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a8acf659337bff5e5bf6b7ab95da464a4">display_valid</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
37
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a1b7bef5ae7965541b6829e0582237a53">vga_r</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
38
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a3002998608bbca4b043ef32814a0e90c">vga_g</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
39
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a5c46fd036c0ceb4ca62ee992f3a3f8cd">vga_b</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
40
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a84472d11a61abbc3b23a0e969dbf7034">enet_clk_25</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Output]</code></td></tr>
41
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#ad0ebcebdfa40bfad1f0e1cf767c5f948">enet_reset_n</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Output]</code></td></tr>
42
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#acafc6c0c8dba9dc4e5b35d68f9ec30f7">enet_cs_n</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Output]</code></td></tr>
43
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a21b872000f4cc3cc38086275e5031edb">enet_irq</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Input]</code></td></tr>
44
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#acc5370f78bef4d859ab318c252e0d4d3">enet_ior_n</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Output]</code></td></tr>
45
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a101095dd45e6bf8d75d2eb42779185a3">enet_iow_n</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Output]</code></td></tr>
46
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#ac4e7f4f3150f9b367ba373fe2d093a1c">enet_cmd</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Output]</code></td></tr>
47
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a01507d79c6d97494ec37aa2d1816c0dc">enet_data</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Inout]</code></td></tr>
48
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a6a9445d546ab0169a9fe4cb3704aa543">tx_active</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
49
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#aca885a3a5491cc14142eda9310673ed8">enet_data_oe</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
50
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#aaf032c46a012fcc50baedece317e4418">enet_data_out</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
51
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#aeade28ddee5ed1bb78359678e1ab0cf7">ram_addr</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
52
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#aa7984493bef70d30c53190e4c148de89">ram_q</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
53
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#ad99bee321744d2060f563e0e9fec7621">vga_line_number</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
54
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#abd391f89b94948281873e66dc755e8a5">last_display_valid</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
55
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#af66c55790fa554df4a256532b05f4a8c">select_line</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
56
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a6bf05ed0f0c28e625508269a958497ae">block_wrreq</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
57
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a38a0ce51d1dfba739092251226e2c642">fifo_wrreq</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
58
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a246788022ac009e7a0ed501c4368fa8d">start_load</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
59
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a23e64f8509cd5130837d5589d6144d0b">fifo_empty</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
60
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a4718b8c841f8694e680df02aae2b33a4">fifo_q</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
61
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#ad4ef489b0816e0c8849b5c3a588e1d11">fifo_rdreq</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
62
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a6ef0f10045357015c38f6fd3bc181d78">fifo_rd_cnt</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
63
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a762873b5a64a5eecb15b8721a83ef6f8">last_fifo_q</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
64
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a7349e4e8b9da301884c10edaf7642c49">state_counter</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Signal]</code></td></tr>
65
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a3305dae46003d5c68ca0e917b94aaf4c">altsyncram</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Module Instance]</code></td></tr>
66
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#aba39015d08a3c10b35fba8eb4414d008">ALWAYS_68</a>clk_30, reset_n</td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Always Construct]</code></td></tr>
67
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#afdf02062e063a6e1eb35038084a33d12">ALWAYS_69</a>clk_30, reset_n</td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Always Construct]</code></td></tr>
68
  <tr class="memlist"><td><a class="el" href="classdrv__eth__vga__capture.html#a59768c08add982f9d20148482217c411">scfifo</a></td><td><a class="el" href="classdrv__eth__vga__capture.html">drv_eth_vga_capture</a></td><td><code> [Module Instance]</code></td></tr>
69
</table></div>
70
<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by&#160;
71
<a href="http://www.doxygen.org/index.html">
72
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
73
</body>
74
</html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.