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<title>aoOCS: Member List</title>
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<li><a href="index.html"><span>Main Page</span></a></li>
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<li class="current"><a href="annotated.html"><span>Design Unit List</span></a></li>
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<h1>memory_registers Member List</h1> </div>
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<div class="contents">
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This is the complete list of members for <a class="el" href="classmemory__registers.html">memory_registers</a>, including all inherited members.<table>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#af3fdc1a826e2d4992fc50550160eed52">An_address</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a05d2b0cd0706cfcb62674e59ed049b22">An_input</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#abfa12b67b2dfb6da21584304919f0a15">An_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#afe969a18dcdd487deeedc9f9146ef8c9">An_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a3380b9a07ee51a05b97308d5a7257972">usp</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a55db549a365e2da7b32c589888f22c1f">Dn_address</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a70e26deed20065da35879d3ce4a7f06e">Dn_input</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a515d2e4fc82f04802e46d5eae5d0f0f5">Dn_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a7e475d550020f2ef86841dd171ddf94e">Dn_size</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a224aca31f9e8189294f9072ee0fc015a">Dn_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a242c22630fbc44df8a129350db77b3d0">micro_pc</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Input]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a9f8c0a5b5adedad8f2f3f503cb5510f6">micro_data</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Output]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#acfe7cd131da7ea586dcb50bea9457678">An_ram_write_enable</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a162864c7253e9c74e47b2822eacde9d4">An_ram_output</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a3ab032d1bc007200d49892a2ab390732">dn_byteena</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Signal]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Module Instance]</code></td></tr>
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<tr class="memlist"><td><a class="el" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">ALWAYS_29</a>clock, reset_n</td><td><a class="el" href="classmemory__registers.html">memory_registers</a></td><td><code> [Always Construct]</code></td></tr>
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</table></div>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by 
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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