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<h1>ocs_control Module Reference</h1>  </div>
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<p><p>OCS system control implementation with WISHBONE slave interface. </p>
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
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Always Constructs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a457e5455cd5940e951513a66fcb55270">ALWAYS_41</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a896ae4138df87842bae2e3beddb07953">ALWAYS_42</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a42a3550bb1bca3965ecb62d3653ed6b6">ALWAYS_43</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
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 <tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">STB_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">SEL_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a0dcd453ed628f5b00f790f2ab89803db">na_int_ena_write</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ab60aa15fd32a27bc713a6e03259b8b9c">na_int_ena_sel</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a8672e719439586f796599c61a9edf765">na_dma_con_write</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">na_dma_con</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#abf6f4b5c6a572ec5a8a35f4d20485566">na_dma_con_sel</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#aa0f199c211813332f0988a4b8a6a3a02">na_pot0dat</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: global registers and blitter signals</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a02b5f619bee718ffca6c320ab96bda12">blitter_busy</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#aa7ea7fc799ab33140366bd1015496a8d">blitter_zero</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: interrupts</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ae645835ecd291e80d3f61ec700e0ef83">blitter_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a0c63e4bdbce5abb540b08a7e92f212a6">cia_a_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#afe3687249cafab6be582a087418a3398">cia_b_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a16bb90760ecef8bb189641ef3966630d">floppy_syn_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a09d4c03109cf00edd231085ce18ab92c">floppy_blk_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a5ec8650f5638dbfa0f0672a36fad69db">serial_rbf_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a6ed777016a820616ed38f063c8578317">serial_tbe_irq</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#aec4f636beb542cf2eba96883a664a736">audio_irq</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
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Outputs</h2></td></tr>
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 <tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a8f9ec718b2729125a55d8befe1f27435">ACK_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a0e6ee6c6aa45013963dd74c65dc37bc6">na_pot0dat_read</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: beam counters</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">line_pre_start</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: clock pulses for CIA and audio</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">pulse_color</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: global registers and blitter signals</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">10</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Internal OCS ports: interrupts</div></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
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Signals</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">10</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a> </td></tr>
122 
</table>
123 
<hr/><a name="_details"></a><h2>Detailed Description</h2>
124 
<p>OCS system control implementation with WISHBONE slave interface. </p>
125 
 <p>List of system control registers: </p>
126 
<div class="fragment"><pre class="fragment">
127 
Implemented:
128 
     [DDFSTOP      094  W   A     Display bitplane data fetch stop
129 
                                  (horiz. position)                             write not implemented here]
130 
    DMACON       096  W   ADP     DMA control write (clear or set)              write not implemented here
131 
 
132 
    DMACONR     *002  R   AP      DMA control (and blitter status) read
133 
    VPOSR       *004  R   A( E )  Read vert most signif. bit (and frame flop)
134 
    VHPOSR      *006  R   A       Read vert and horiz. position of beam
135 
 
136 
    ADKCON       09E  W   P       Audio, disk, UART control
137 
 
138 
    ADKCONR     *010  R   P       Audio, disk control register read
139 
     [POT0DAT   *012  R   P( E )  Pot counter pair 0 data (vert,horiz)          read implemented here]
140 
 
141 
    INTENAR     *01C  R   P       Interrupt enable bits read
142 
    INTREQR     *01E  R   P       Interrupt request bits read
143 
 
144 
     [CLXCON     098  W   D       Collision control                             write not implemented here]
145 
    INTENA       09A  W   P       Interrupt enable bits (clear or set bits)     write not implemented here
146 
    INTREQ       09C  W   P       Interrupt request bits (clear or set bits)
147 
 
148 
Not implemented:
149 
    REFPTR    &amp; *028  W   A       Refresh pointer
150 
    VPOSW       *02A  W   A       Write vert most signif. bit (and frame flop)
151 
    VHPOSW      *02C  W   A       Write vert and horiz position of beam
152 
 
153 
    STREQU    &amp; *038  S   D       Strobe for horiz sync with VB and EQU
154 
    STRVBL    &amp; *03A  S   D       Strobe for horiz sync with VB (vert. blank)
155 
    STRHOR    &amp; *03C  S   DP      Strobe for horiz sync
156 
    STRLONG   &amp; *03E  S   D( E )  Strobe for identification of long horiz. line.
157 
 
158 
    RESERVED     1110X
159 
    RESERVED     1111X
160 
    NO-OP(NULL)  1FE
161 
</pre></div>
162 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00069">69</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
163 
<hr/><h2>Member Function Documentation</h2>
164 
<a class="anchor" id="a941900ef0da9240ac0c4925bcc5c72b0"></a><!-- doxytag: member="ocs_control::ALWAYS_40" ref="a941900ef0da9240ac0c4925bcc5c72b0" args="clk_30, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_40          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
171 
        </tr>
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        <tr>
173 
          <td class="paramkey"></td>
174 
          <td></td>
175 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
176 
        </tr>
177 
<code> [Always Construct]</code></td>
178 
        </tr>
179 
      </table>
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</div>
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<div class="memdoc">
182 
 
183 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00182">182</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="a457e5455cd5940e951513a66fcb55270"></a><!-- doxytag: member="ocs_control::ALWAYS_41" ref="a457e5455cd5940e951513a66fcb55270" args="clk_30, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_41          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
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        <tr>
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          <td class="paramkey"></td>
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          <td></td>
198 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
199 
        </tr>
200 
<code> [Always Construct]</code></td>
201 
        </tr>
202 
      </table>
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</div>
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<div class="memdoc">
205 
 
206 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00272">272</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="a896ae4138df87842bae2e3beddb07953"></a><!-- doxytag: member="ocs_control::ALWAYS_42" ref="a896ae4138df87842bae2e3beddb07953" args="clk_30, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_42          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
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        <tr>
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          <td class="paramkey"></td>
220 
          <td></td>
221 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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        </tr>
223 
<code> [Always Construct]</code></td>
224 
        </tr>
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      </table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00297">297</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="a42a3550bb1bca3965ecb62d3653ed6b6"></a><!-- doxytag: member="ocs_control::ALWAYS_43" ref="a42a3550bb1bca3965ecb62d3653ed6b6" args="clk_30, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_43          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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        </tr>
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        <tr>
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          <td class="paramkey"></td>
243 
          <td></td>
244 
          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
247 
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      </table>
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</div>
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<div class="memdoc">
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252 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00306">306</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
253 
 
254 
</div>
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</div>
256 
<hr/><h2>Member Data Documentation</h2>
257 
<a class="anchor" id="a78eebaf1d7122debfc56eebb02678f7c"></a><!-- doxytag: member="ocs_control::clk_30" ref="a78eebaf1d7122debfc56eebb02678f7c" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a78eebaf1d7122debfc56eebb02678f7c">clk_30</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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      </table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00072">72</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="a246ab8bc07755c51fdd905891ec461e7"></a><!-- doxytag: member="ocs_control::reset_n" ref="a246ab8bc07755c51fdd905891ec461e7" args="" -->
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<div class="memitem">
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a246ab8bc07755c51fdd905891ec461e7">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00073">73</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a2b96a7c9eef58084d7c25b4cda2c4ed8"></a><!-- doxytag: member="ocs_control::CYC_I" ref="a2b96a7c9eef58084d7c25b4cda2c4ed8" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a2b96a7c9eef58084d7c25b4cda2c4ed8">CYC_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00078">78</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a26071b95b282cb6ff3aac96128f0737a"></a><!-- doxytag: member="ocs_control::STB_I" ref="a26071b95b282cb6ff3aac96128f0737a" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a26071b95b282cb6ff3aac96128f0737a">STB_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00079">79</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="ac7648944e0726e364b9509f1a0b81c12"></a><!-- doxytag: member="ocs_control::WE_I" ref="ac7648944e0726e364b9509f1a0b81c12" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ac7648944e0726e364b9509f1a0b81c12">WE_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00080">80</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a5287d0f0371bd2793e15feb3e1871bbd"></a><!-- doxytag: member="ocs_control::ADR_I" ref="a5287d0f0371bd2793e15feb3e1871bbd" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a5287d0f0371bd2793e15feb3e1871bbd">ADR_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00081">81</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a6eb7afa02ef30b83f4553c2710cb219d"></a><!-- doxytag: member="ocs_control::SEL_I" ref="a6eb7afa02ef30b83f4553c2710cb219d" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a6eb7afa02ef30b83f4553c2710cb219d">SEL_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00082">82</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a8a577d05f486a2b93a18f90ae5a08646"></a><!-- doxytag: member="ocs_control::slave_DAT_I" ref="a8a577d05f486a2b93a18f90ae5a08646" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a8a577d05f486a2b93a18f90ae5a08646">slave_DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00083">83</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a4c36d95eefa6d567b8b4e8d476cd3a96"></a><!-- doxytag: member="ocs_control::slave_DAT_O" ref="a4c36d95eefa6d567b8b4e8d476cd3a96" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a4c36d95eefa6d567b8b4e8d476cd3a96">slave_DAT_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00084">84</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a8f9ec718b2729125a55d8befe1f27435"></a><!-- doxytag: member="ocs_control::ACK_O" ref="a8f9ec718b2729125a55d8befe1f27435" args="" -->
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00085">85</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a0dcd453ed628f5b00f790f2ab89803db"></a><!-- doxytag: member="ocs_control::na_int_ena_write" ref="a0dcd453ed628f5b00f790f2ab89803db" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0dcd453ed628f5b00f790f2ab89803db">na_int_ena_write</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00091">91</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="aa45b061fb9026b2d2ea62770ba1516af"></a><!-- doxytag: member="ocs_control::na_int_ena" ref="aa45b061fb9026b2d2ea62770ba1516af" args="" -->
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00092">92</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<div class="memitem">
439 
<div class="memproto">
440 
      <table class="memname">
441 
        <tr>
442 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ab60aa15fd32a27bc713a6e03259b8b9c">na_int_ena_sel</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
443 
        </tr>
444 
      </table>
445 
</div>
446 
<div class="memdoc">
447 
 
448 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00093">93</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
449 
 
450 
</div>
451 
</div>
452 
<a class="anchor" id="a8672e719439586f796599c61a9edf765"></a><!-- doxytag: member="ocs_control::na_dma_con_write" ref="a8672e719439586f796599c61a9edf765" args="" -->
453 
<div class="memitem">
454 
<div class="memproto">
455 
      <table class="memname">
456 
        <tr>
457 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a8672e719439586f796599c61a9edf765">na_dma_con_write</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
458 
        </tr>
459 
      </table>
460 
</div>
461 
<div class="memdoc">
462 
 
463 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00095">95</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
464 
 
465 
</div>
466 
</div>
467 
<a class="anchor" id="a253a44d8f5bba8b2a5a1988e73059626"></a><!-- doxytag: member="ocs_control::na_dma_con" ref="a253a44d8f5bba8b2a5a1988e73059626" args="" -->
468 
<div class="memitem">
469 
<div class="memproto">
470 
      <table class="memname">
471 
        <tr>
472 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a253a44d8f5bba8b2a5a1988e73059626">na_dma_con</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
473 
        </tr>
474 
      </table>
475 
</div>
476 
<div class="memdoc">
477 
 
478 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00096">96</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
479 
 
480 
</div>
481 
</div>
482 
<a class="anchor" id="abf6f4b5c6a572ec5a8a35f4d20485566"></a><!-- doxytag: member="ocs_control::na_dma_con_sel" ref="abf6f4b5c6a572ec5a8a35f4d20485566" args="" -->
483 
<div class="memitem">
484 
<div class="memproto">
485 
      <table class="memname">
486 
        <tr>
487 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#abf6f4b5c6a572ec5a8a35f4d20485566">na_dma_con_sel</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
488 
        </tr>
489 
      </table>
490 
</div>
491 
<div class="memdoc">
492 
 
493 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00097">97</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
494 
 
495 
</div>
496 
</div>
497 
<a class="anchor" id="a0e6ee6c6aa45013963dd74c65dc37bc6"></a><!-- doxytag: member="ocs_control::na_pot0dat_read" ref="a0e6ee6c6aa45013963dd74c65dc37bc6" args="" -->
498 
<div class="memitem">
499 
<div class="memproto">
500 
      <table class="memname">
501 
        <tr>
502 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0e6ee6c6aa45013963dd74c65dc37bc6">na_pot0dat_read</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
503 
        </tr>
504 
      </table>
505 
</div>
506 
<div class="memdoc">
507 
 
508 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00099">99</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
509 
 
510 
</div>
511 
</div>
512 
<a class="anchor" id="aa0f199c211813332f0988a4b8a6a3a02"></a><!-- doxytag: member="ocs_control::na_pot0dat" ref="aa0f199c211813332f0988a4b8a6a3a02" args="" -->
513 
<div class="memitem">
514 
<div class="memproto">
515 
      <table class="memname">
516 
        <tr>
517 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa0f199c211813332f0988a4b8a6a3a02">na_pot0dat</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
518 
        </tr>
519 
      </table>
520 
</div>
521 
<div class="memdoc">
522 
 
523 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00100">100</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
524 
 
525 
</div>
526 
</div>
527 
<a class="anchor" id="af98b6d9d326d8dd116b3b7969a720247"></a><!-- doxytag: member="ocs_control::line_start" ref="af98b6d9d326d8dd116b3b7969a720247" args="" -->
528 
<div class="memitem">
529 
<div class="memproto">
530 
      <table class="memname">
531 
        <tr>
532 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#af98b6d9d326d8dd116b3b7969a720247">line_start</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
533 
        </tr>
534 
      </table>
535 
</div>
536 
<div class="memdoc">
537 
 
538 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00105">105</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
539 
 
540 
</div>
541 
</div>
542 
<a class="anchor" id="ada98b4d5917ec047013fdc76570c6a8e"></a><!-- doxytag: member="ocs_control::line_pre_start" ref="ada98b4d5917ec047013fdc76570c6a8e" args="" -->
543 
<div class="memitem">
544 
<div class="memproto">
545 
      <table class="memname">
546 
        <tr>
547 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ada98b4d5917ec047013fdc76570c6a8e">line_pre_start</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
548 
        </tr>
549 
      </table>
550 
</div>
551 
<div class="memdoc">
552 
 
553 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00106">106</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
554 
 
555 
</div>
556 
</div>
557 
<a class="anchor" id="a4550e00911796d007466de7625bd0b2a"></a><!-- doxytag: member="ocs_control::line_number" ref="a4550e00911796d007466de7625bd0b2a" args="" -->
558 
<div class="memitem">
559 
<div class="memproto">
560 
      <table class="memname">
561 
        <tr>
562 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a4550e00911796d007466de7625bd0b2a">line_number</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
563 
        </tr>
564 
      </table>
565 
</div>
566 
<div class="memdoc">
567 
 
568 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00107">107</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
569 
 
570 
</div>
571 
</div>
572 
<a class="anchor" id="a91b282041c78283ad2fd1a333cf3fdc4"></a><!-- doxytag: member="ocs_control::column_number" ref="a91b282041c78283ad2fd1a333cf3fdc4" args="" -->
573 
<div class="memitem">
574 
<div class="memproto">
575 
      <table class="memname">
576 
        <tr>
577 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a91b282041c78283ad2fd1a333cf3fdc4">column_number</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
578 
        </tr>
579 
      </table>
580 
</div>
581 
<div class="memdoc">
582 
 
583 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00108">108</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
584 
 
585 
</div>
586 
</div>
587 
<a class="anchor" id="a0197eedf5b87ff26b0b2035e18b8c1c1"></a><!-- doxytag: member="ocs_control::pulse_709379_hz" ref="a0197eedf5b87ff26b0b2035e18b8c1c1" args="" -->
588 
<div class="memitem">
589 
<div class="memproto">
590 
      <table class="memname">
591 
        <tr>
592 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0197eedf5b87ff26b0b2035e18b8c1c1">pulse_709379_hz</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
593 
        </tr>
594 
      </table>
595 
</div>
596 
<div class="memdoc">
597 
 
598 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00113">113</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
599 
 
600 
</div>
601 
</div>
602 
<a class="anchor" id="ac0fa0cd71802281503990be9fd87f900"></a><!-- doxytag: member="ocs_control::pulse_color" ref="ac0fa0cd71802281503990be9fd87f900" args="" -->
603 
<div class="memitem">
604 
<div class="memproto">
605 
      <table class="memname">
606 
        <tr>
607 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ac0fa0cd71802281503990be9fd87f900">pulse_color</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
608 
        </tr>
609 
      </table>
610 
</div>
611 
<div class="memdoc">
612 
 
613 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00114">114</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
614 
 
615 
</div>
616 
</div>
617 
<a class="anchor" id="a2ef3aff81fd20f8ae91d3e66c046fffe"></a><!-- doxytag: member="ocs_control::dma_con" ref="a2ef3aff81fd20f8ae91d3e66c046fffe" args="" -->
618 
<div class="memitem">
619 
<div class="memproto">
620 
      <table class="memname">
621 
        <tr>
622 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a2ef3aff81fd20f8ae91d3e66c046fffe">dma_con</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">10</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
623 
        </tr>
624 
      </table>
625 
</div>
626 
<div class="memdoc">
627 
 
628 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00119">119</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
629 
 
630 
</div>
631 
</div>
632 
<a class="anchor" id="ad1c254c7e4551d7f373b552e40652f5f"></a><!-- doxytag: member="ocs_control::adk_con" ref="ad1c254c7e4551d7f373b552e40652f5f" args="" -->
633 
<div class="memitem">
634 
<div class="memproto">
635 
      <table class="memname">
636 
        <tr>
637 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ad1c254c7e4551d7f373b552e40652f5f">adk_con</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">14</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
638 
        </tr>
639 
      </table>
640 
</div>
641 
<div class="memdoc">
642 
 
643 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00120">120</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
644 
 
645 
</div>
646 
</div>
647 
<a class="anchor" id="a02b5f619bee718ffca6c320ab96bda12"></a><!-- doxytag: member="ocs_control::blitter_busy" ref="a02b5f619bee718ffca6c320ab96bda12" args="" -->
648 
<div class="memitem">
649 
<div class="memproto">
650 
      <table class="memname">
651 
        <tr>
652 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a02b5f619bee718ffca6c320ab96bda12">blitter_busy</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
653 
        </tr>
654 
      </table>
655 
</div>
656 
<div class="memdoc">
657 
 
658 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00122">122</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
659 
 
660 
</div>
661 
</div>
662 
<a class="anchor" id="aa7ea7fc799ab33140366bd1015496a8d"></a><!-- doxytag: member="ocs_control::blitter_zero" ref="aa7ea7fc799ab33140366bd1015496a8d" args="" -->
663 
<div class="memitem">
664 
<div class="memproto">
665 
      <table class="memname">
666 
        <tr>
667 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa7ea7fc799ab33140366bd1015496a8d">blitter_zero</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
668 
        </tr>
669 
      </table>
670 
</div>
671 
<div class="memdoc">
672 
 
673 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00123">123</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
674 
 
675 
</div>
676 
</div>
677 
<a class="anchor" id="ae645835ecd291e80d3f61ec700e0ef83"></a><!-- doxytag: member="ocs_control::blitter_irq" ref="ae645835ecd291e80d3f61ec700e0ef83" args="" -->
678 
<div class="memitem">
679 
<div class="memproto">
680 
      <table class="memname">
681 
        <tr>
682 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#ae645835ecd291e80d3f61ec700e0ef83">blitter_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
683 
        </tr>
684 
      </table>
685 
</div>
686 
<div class="memdoc">
687 
 
688 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00128">128</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
689 
 
690 
</div>
691 
</div>
692 
<a class="anchor" id="a0c63e4bdbce5abb540b08a7e92f212a6"></a><!-- doxytag: member="ocs_control::cia_a_irq" ref="a0c63e4bdbce5abb540b08a7e92f212a6" args="" -->
693 
<div class="memitem">
694 
<div class="memproto">
695 
      <table class="memname">
696 
        <tr>
697 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a0c63e4bdbce5abb540b08a7e92f212a6">cia_a_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
698 
        </tr>
699 
      </table>
700 
</div>
701 
<div class="memdoc">
702 
 
703 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00129">129</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
704 
 
705 
</div>
706 
</div>
707 
<a class="anchor" id="afe3687249cafab6be582a087418a3398"></a><!-- doxytag: member="ocs_control::cia_b_irq" ref="afe3687249cafab6be582a087418a3398" args="" -->
708 
<div class="memitem">
709 
<div class="memproto">
710 
      <table class="memname">
711 
        <tr>
712 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#afe3687249cafab6be582a087418a3398">cia_b_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
713 
        </tr>
714 
      </table>
715 
</div>
716 
<div class="memdoc">
717 
 
718 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00130">130</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
719 
 
720 
</div>
721 
</div>
722 
<a class="anchor" id="a16bb90760ecef8bb189641ef3966630d"></a><!-- doxytag: member="ocs_control::floppy_syn_irq" ref="a16bb90760ecef8bb189641ef3966630d" args="" -->
723 
<div class="memitem">
724 
<div class="memproto">
725 
      <table class="memname">
726 
        <tr>
727 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a16bb90760ecef8bb189641ef3966630d">floppy_syn_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
728 
        </tr>
729 
      </table>
730 
</div>
731 
<div class="memdoc">
732 
 
733 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00131">131</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
734 
 
735 
</div>
736 
</div>
737 
<a class="anchor" id="a09d4c03109cf00edd231085ce18ab92c"></a><!-- doxytag: member="ocs_control::floppy_blk_irq" ref="a09d4c03109cf00edd231085ce18ab92c" args="" -->
738 
<div class="memitem">
739 
<div class="memproto">
740 
      <table class="memname">
741 
        <tr>
742 
          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a09d4c03109cf00edd231085ce18ab92c">floppy_blk_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
743 
        </tr>
744 
      </table>
745 
</div>
746 
<div class="memdoc">
747 
 
748 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00132">132</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
749 
 
750 
</div>
751 
</div>
752 
<a class="anchor" id="a5ec8650f5638dbfa0f0672a36fad69db"></a><!-- doxytag: member="ocs_control::serial_rbf_irq" ref="a5ec8650f5638dbfa0f0672a36fad69db" args="" -->
753 
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a5ec8650f5638dbfa0f0672a36fad69db">serial_rbf_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00133">133</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="a6ed777016a820616ed38f063c8578317"></a><!-- doxytag: member="ocs_control::serial_tbe_irq" ref="a6ed777016a820616ed38f063c8578317" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a6ed777016a820616ed38f063c8578317">serial_tbe_irq</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00134">134</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="aec4f636beb542cf2eba96883a664a736"></a><!-- doxytag: member="ocs_control::audio_irq" ref="aec4f636beb542cf2eba96883a664a736" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aec4f636beb542cf2eba96883a664a736">audio_irq</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00135">135</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa8d13b23544f041f1f633c8237e0ad03">interrupt</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00137">137</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a50bcd8b53c850440d22c18a40f5a3255">new_int_req</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[14:0]]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00159">159</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00175">175</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a37d5b61b43de582a29e66d99937762db">int_req</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[14:0]]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00176">176</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a30b9ec3d0a2504a8d4ce0c4f38bbe122">column_counter</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[10:0]]</code></td>
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868 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00177">177</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a60428caa020a8abe12a58b707c2f4dcc">long_frame</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00178">178</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<a class="anchor" id="aa9b59818fff4230873e441c8a2a60849"></a><!-- doxytag: member="ocs_control::counter_709379_hz" ref="aa9b59818fff4230873e441c8a2a60849" args="reg[2:0]" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#aa9b59818fff4230873e441c8a2a60849">counter_709379_hz</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[2:0]]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00271">271</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a4e8810952f8e3f0d2aaf70f534825718">pulse_counter</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00296">296</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a26d607f09a884c29628f3d1fb27d2284">counter_cpu</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[10:0]]</code></td>
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928 
<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00304">304</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__control.html#a8465c5335d8e7bc89684c040e41cbd53">pulse_cpu</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="ocs__control_8v_source.html#l00305">305</a> of file <a class="el" href="ocs__control_8v_source.html">ocs_control.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li><a class="el" href="ocs__control_8v_source.html">ocs_control.v</a></li>
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</ul>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by&#160;
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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