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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html xmlns="http://www.w3.org/1999/xhtml">
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<head>
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<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
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<title>aoOCS: ocs_serial Module Reference</title>
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      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
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      <li><a href="functions.html"><span>Design&#160;Unit&#160;Members</span></a></li>
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  <div class="summary">
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<a href="#Inputs">Inputs</a> &#124;
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<a href="#Outputs">Outputs</a> &#124;
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<a href="#Always Constructs">Always Constructs</a>  </div>
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  <div class="headertitle">
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<h1>ocs_serial Module Reference</h1>  </div>
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<div class="contents">
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<!-- doxytag: class="ocs_serial" -->
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<p><p>OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]. </p>
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<a href="#_details">More...</a></p>
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<!-- startSectionHeader --><div class="dynheader">
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Inheritance diagram for ocs_serial:<!-- endSectionHeader --></div>
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</map>
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<p><a href="classocs__serial-members.html">List of all members.</a></p>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
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Always Constructs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a52fa402c182371c96de65a44f4d0ad27">ALWAYS_49</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
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 <tr><td colspan="2"><div class="groupHeader">Clock and reset</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a220f1561e548a7d1762e444e0a3a8255">CYC_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a71181c2f7c1786e7c8d36efcc5cd6384">STB_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a26ba3360a85981afe01b1ba0d42ded79">WE_I</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ab522ee14d28ba506e3257da274de8052">ADR_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ae600c0f33099d217d6d6590c913a0474">SEL_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#ae8dce78204888df829f52c2943d646bd">DAT_I</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">na_dskbytr</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
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Outputs</h2></td></tr>
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 <tr><td colspan="2"><div class="groupHeader">WISHBONE slave</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a845b761bb592b34bbef8610710b4d089">DAT_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a469e46a6b2d056ab92f642bd7166a09b">ACK_O</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><div class="groupHeader">Not aligned register access on a 32-bit WISHBONE bus</div></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classocs__serial.html#a22cfe10bb9f32bd121b3e485129036ad">na_dskbytr_read</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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</table>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
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<p>OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]. </p>
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 <p>List of serial registers: </p>
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<div class="fragment"><pre class="fragment">
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Not implemented:
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    SERDATR     *018  R   P       Serial port data and status read              read implemented here
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     [DSKBYTR   *01A  R   P       Disk data byte and status read                read implemented here]
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    SERDAT      *030  W   P       Serial port data and stop bits write
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    SERPER      *032  W   P       Serial port period and control
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</pre></div>
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<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00042">42</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<hr/><h2>Member Function Documentation</h2>
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<a class="anchor" id="a52fa402c182371c96de65a44f4d0ad27"></a><!-- doxytag: member="ocs_serial::ALWAYS_49" ref="a52fa402c182371c96de65a44f4d0ad27" args="CLK_I, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_49          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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          <td class="paramkey"></td>
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          <td></td>
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          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classocs__serial.html#ab056ba3c82108a98db62cab2629c2f11">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00072">72</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<hr/><h2>Member Data Documentation</h2>
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<a class="anchor" id="afaf38f6309d65be30657673eda60b0d5"></a><!-- doxytag: member="ocs_serial::CLK_I" ref="afaf38f6309d65be30657673eda60b0d5" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#afaf38f6309d65be30657673eda60b0d5">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00045">45</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00056">56</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00057">57</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00064">64</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classocs__serial.html#a41b01454461979054072a9dd162861fe">na_dskbytr</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ocs__serial_8v_source.html#l00065">65</a> of file <a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li><a class="el" href="ocs__serial_8v_source.html">ocs_serial.v</a></li>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by&#160;
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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