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<title>aoOCS: debug.v Source File</title>
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<h1>debug.v</h1> </div>
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</div>
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<div class="contents">
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<a href="debug_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001 <span class="keyword">// ---------------- general DEBUG</span>
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| 32 |
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<a name="l00002"></a>00002 <span class="keyword">/*</span>
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| 33 |
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<a name="l00003"></a>00003 <span class="keyword">wire debug_write;</span>
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| 34 |
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<a name="l00004"></a>00004 <span class="keyword">assign debug_write = master1_cyc_o == 1'b1 && master1_stb_o == 1'b1 && master1_we_o == 1'b0 && master1_adr_o != last_addr &&</span>
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| 35 |
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<a name="l00005"></a>00005 <span class="keyword"> ({master1_adr_o[31:2], 2'b00} >= 32'h00DFF000) && ({master1_adr_o[31:2], 2'b00} <= 32'h00DFF01C);</span>
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| 36 |
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<a name="l00006"></a>00006 <span class="keyword"></span>
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| 37 |
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<a name="l00007"></a>00007 <span class="keyword">reg [11:0] debug_addr;</span>
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| 38 |
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<a name="l00008"></a>00008 <span class="keyword">reg [31:2] last_addr;</span>
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| 39 |
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<a name="l00009"></a>00009 <span class="keyword">always @(posedge clk_30 or negedge reset_n) begin</span>
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| 40 |
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<a name="l00010"></a>00010 <span class="keyword"> if(reset_n == 1'b0) last_addr <= 30'd0;</span>
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| 41 |
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<a name="l00011"></a>00011 <span class="keyword"> else last_addr <= master1_adr_o; </span>
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| 42 |
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<a name="l00012"></a>00012 <span class="keyword"><span class="vhdlkeyword">end</span></span>
|
| 43 |
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<a name="l00013"></a>00013 <span class="keyword"></span>
|
| 44 |
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<a name="l00014"></a>00014 <span class="keyword">always @(posedge clk_30 or negedge reset_n) begin</span>
|
| 45 |
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<a name="l00015"></a>00015 <span class="keyword"> if(reset_n == 1'b0) debug_addr <= 12'd0;</span>
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| 46 |
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<a name="l00016"></a>00016 <span class="keyword"> else if(debug_write == 1'b1 //&& debug_addr < 12'd4095//) debug_addr <= debug_addr + 12'd1;</span>
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| 47 |
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<a name="l00017"></a>00017 <span class="keyword"><span class="vhdlkeyword">end</span></span>
|
| 48 |
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<a name="l00018"></a>00018 <span class="keyword"></span>
|
| 49 |
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<a name="l00019"></a>00019 <span class="keyword">altsyncram debug_ram_inst(</span>
|
| 50 |
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<a name="l00020"></a>00020 <span class="keyword"> .clock0(clk_30),</span>
|
| 51 |
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<a name="l00021"></a>00021 <span class="keyword"></span>
|
| 52 |
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<a name="l00022"></a>00022 <span class="keyword"> .address_a(debug_addr),</span>
|
| 53 |
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<a name="l00023"></a>00023 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
|
| 54 |
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<a name="l00024"></a>00024 <span class="keyword"> .data_a( { 3'b0, master1_adr_o[8:2], 2'b00} ),</span>
|
| 55 |
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<a name="l00025"></a>00025 <span class="keyword"> .q_a()</span>
|
| 56 |
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<a name="l00026"></a>00026 <span class="keyword">);</span>
|
| 57 |
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<a name="l00027"></a>00027 <span class="keyword">defparam </span>
|
| 58 |
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<a name="l00028"></a>00028 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
|
| 59 |
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<a name="l00029"></a>00029 <span class="keyword"> debug_ram_inst.width_a = 12,</span>
|
| 60 |
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<a name="l00030"></a>00030 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem",</span>
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| 61 |
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<a name="l00031"></a>00031 <span class="keyword"> debug_ram_inst.widthad_a = 12;</span>
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| 62 |
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<a name="l00032"></a>00032 <span class="keyword">*/</span>
|
| 63 |
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<a name="l00033"></a>00033
|
| 64 |
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<a name="l00034"></a>00034 <span class="keyword">/*</span>
|
| 65 |
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<a name="l00035"></a>00035 <span class="keyword">// ----------------------------- copper DEBUG</span>
|
| 66 |
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<a name="l00036"></a>00036 <span class="keyword">wire debug_write;</span>
|
| 67 |
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<a name="l00037"></a>00037 <span class="keyword">assign debug_write = (state == S_SAVE && ACK_I == 1'b1);</span>
|
| 68 |
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<a name="l00038"></a>00038 <span class="keyword"></span>
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| 69 |
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<a name="l00039"></a>00039 <span class="keyword">reg [7:0] debug_addr;</span>
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| 70 |
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<a name="l00040"></a>00040 <span class="keyword">always @(posedge CLK_I) begin</span>
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| 71 |
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<a name="l00041"></a>00041 <span class="keyword"> if(line_start == 1'b1 && line_number == 9'd0) debug_addr <= 8'd0;</span>
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| 72 |
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<a name="l00042"></a>00042 <span class="keyword"> else if(debug_write == 1'b1 && debug_addr < 8'd255) debug_addr <= debug_addr + 8'd1;</span>
|
| 73 |
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<a name="l00043"></a>00043 <span class="keyword"><span class="vhdlkeyword">end</span></span>
|
| 74 |
|
|
<a name="l00044"></a>00044 <span class="keyword"></span>
|
| 75 |
|
|
<a name="l00045"></a>00045 <span class="keyword">altsyncram debug_ram_inst(</span>
|
| 76 |
|
|
<a name="l00046"></a>00046 <span class="keyword"> .clock0(CLK_I),</span>
|
| 77 |
|
|
<a name="l00047"></a>00047 <span class="keyword"></span>
|
| 78 |
|
|
<a name="l00048"></a>00048 <span class="keyword"> .address_a(debug_addr),</span>
|
| 79 |
|
|
<a name="l00049"></a>00049 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
|
| 80 |
|
|
<a name="l00050"></a>00050 <span class="keyword"> .data_a({3'b0, line_number, ir}),</span>
|
| 81 |
|
|
<a name="l00051"></a>00051 <span class="keyword"> .q_a()</span>
|
| 82 |
|
|
<a name="l00052"></a>00052 <span class="keyword">);</span>
|
| 83 |
|
|
<a name="l00053"></a>00053 <span class="keyword">defparam </span>
|
| 84 |
|
|
<a name="l00054"></a>00054 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
|
| 85 |
|
|
<a name="l00055"></a>00055 <span class="keyword"> debug_ram_inst.width_a = 60,</span>
|
| 86 |
|
|
<a name="l00056"></a>00056 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=cop",</span>
|
| 87 |
|
|
<a name="l00057"></a>00057 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
|
| 88 |
|
|
<a name="l00058"></a>00058 <span class="keyword">// ----------------------------- DEBUG</span>
|
| 89 |
|
|
<a name="l00059"></a>00059 <span class="keyword">*/</span>
|
| 90 |
|
|
<a name="l00060"></a>00060
|
| 91 |
|
|
<a name="l00061"></a>00061 <span class="keyword">//------------------------- video DEBUG</span>
|
| 92 |
|
|
<a name="l00062"></a>00062 <span class="keyword">/*</span>
|
| 93 |
|
|
<a name="l00063"></a>00063 <span class="keyword">altsyncram debug_ram_inst(</span>
|
| 94 |
|
|
<a name="l00064"></a>00064 <span class="keyword"> .clock0(CLK_I),</span>
|
| 95 |
|
|
<a name="l00065"></a>00065 <span class="keyword"></span>
|
| 96 |
|
|
<a name="l00066"></a>00066 <span class="keyword"> .address_a(bitplain_ram_addr),</span>
|
| 97 |
|
|
<a name="l00067"></a>00067 <span class="keyword"> .wren_a(burst_read_ready == 1'b1 && burst_read_request == 1'b1 && line_number == 9'hF4),</span>
|
| 98 |
|
|
<a name="l00068"></a>00068 <span class="keyword"> .data_a({dma_address_full, (dma_address_full[1] == 1'b0) ? burst_read_data : {even_data, burst_read_data[31:16]}, 3'b0, burst_read_enabled }),</span>
|
| 99 |
|
|
<a name="l00069"></a>00069 <span class="keyword"> .q_a()</span>
|
| 100 |
|
|
<a name="l00070"></a>00070 <span class="keyword">);</span>
|
| 101 |
|
|
<a name="l00071"></a>00071 <span class="keyword">defparam </span>
|
| 102 |
|
|
<a name="l00072"></a>00072 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
|
| 103 |
|
|
<a name="l00073"></a>00073 <span class="keyword"> debug_ram_inst.width_a = 68,</span>
|
| 104 |
|
|
<a name="l00074"></a>00074 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=bpl",</span>
|
| 105 |
|
|
<a name="l00075"></a>00075 <span class="keyword"> debug_ram_inst.widthad_a = 5;</span>
|
| 106 |
|
|
<a name="l00076"></a>00076 <span class="keyword">*/</span>
|
| 107 |
|
|
<a name="l00077"></a>00077 <span class="keyword">/*</span>
|
| 108 |
|
|
<a name="l00078"></a>00078 <span class="keyword">wire debug_write;</span>
|
| 109 |
|
|
<a name="l00079"></a>00079 <span class="keyword">assign debug_write = (line_number >= 9'd64 && write_ena == 1'b1 && write_address == 1'b0);</span>
|
| 110 |
|
|
<a name="l00080"></a>00080 <span class="keyword"></span>
|
| 111 |
|
|
<a name="l00081"></a>00081 <span class="keyword">reg [7:0] debug_addr;</span>
|
| 112 |
|
|
<a name="l00082"></a>00082 <span class="keyword">always @(posedge CLK_I or negedge reset_n) begin</span>
|
| 113 |
|
|
<a name="l00083"></a>00083 <span class="keyword"> if(reset_n == 1'b0) debug_addr <= 8'd0;</span>
|
| 114 |
|
|
<a name="l00084"></a>00084 <span class="keyword"> else if(debug_write == 1'b1) debug_addr <= debug_addr + 8'd1;</span>
|
| 115 |
|
|
<a name="l00085"></a>00085 <span class="keyword"><span class="vhdlkeyword">end</span></span>
|
| 116 |
|
|
<a name="l00086"></a>00086 <span class="keyword"></span>
|
| 117 |
|
|
<a name="l00087"></a>00087 <span class="keyword">altsyncram debug_ram_inst(</span>
|
| 118 |
|
|
<a name="l00088"></a>00088 <span class="keyword"> .clock0(CLK_I),</span>
|
| 119 |
|
|
<a name="l00089"></a>00089 <span class="keyword"></span>
|
| 120 |
|
|
<a name="l00090"></a>00090 <span class="keyword"> .address_a(debug_addr),</span>
|
| 121 |
|
|
<a name="l00091"></a>00091 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
|
| 122 |
|
|
<a name="l00092"></a>00092 <span class="keyword"> .data_a( { 3'b0, line_number, 3'b0, column_number, 2'b0, dma_state, write_sel, write_data, dma_address_full } ),</span>
|
| 123 |
|
|
<a name="l00093"></a>00093 <span class="keyword"> .q_a()</span>
|
| 124 |
|
|
<a name="l00094"></a>00094 <span class="keyword">);</span>
|
| 125 |
|
|
<a name="l00095"></a>00095 <span class="keyword">defparam </span>
|
| 126 |
|
|
<a name="l00096"></a>00096 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
|
| 127 |
|
|
<a name="l00097"></a>00097 <span class="keyword"> debug_ram_inst.width_a = 96,</span>
|
| 128 |
|
|
<a name="l00098"></a>00098 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem",</span>
|
| 129 |
|
|
<a name="l00099"></a>00099 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
|
| 130 |
|
|
<a name="l00100"></a>00100 <span class="keyword">*/</span>
|
| 131 |
|
|
<a name="l00101"></a>00101
|
| 132 |
|
|
<a name="l00102"></a>00102 <span class="keyword">// ---------------- floppy DEBUG</span>
|
| 133 |
|
|
<a name="l00103"></a>00103 <span class="keyword">/*</span>
|
| 134 |
|
|
<a name="l00104"></a>00104 <span class="keyword">wire debug_write;</span>
|
| 135 |
|
|
<a name="l00105"></a>00105 <span class="keyword">assign debug_write = (buffer_read_cycle == 1'b1 && state != S_WRITE_TO_SD);</span>
|
| 136 |
|
|
<a name="l00106"></a>00106 <span class="keyword"></span>
|
| 137 |
|
|
<a name="l00107"></a>00107 <span class="keyword">reg [7:0] debug_addr;</span>
|
| 138 |
|
|
<a name="l00108"></a>00108 <span class="keyword">always @(posedge clk_30 or negedge reset_n) begin</span>
|
| 139 |
|
|
<a name="l00109"></a>00109 <span class="keyword"> if(reset_n == 1'b0) debug_addr <= 8'd0;</span>
|
| 140 |
|
|
<a name="l00110"></a>00110 <span class="keyword"> else if(debug_write == 1'b1 && debug_addr < 8'd255) debug_addr <= debug_addr + 8'd1;</span>
|
| 141 |
|
|
<a name="l00111"></a>00111 <span class="keyword"><span class="vhdlkeyword">end</span></span>
|
| 142 |
|
|
<a name="l00112"></a>00112 <span class="keyword"></span>
|
| 143 |
|
|
<a name="l00113"></a>00113 <span class="keyword">altsyncram debug_ram_inst(</span>
|
| 144 |
|
|
<a name="l00114"></a>00114 <span class="keyword"> .clock0(clk_30),</span>
|
| 145 |
|
|
<a name="l00115"></a>00115 <span class="keyword"></span>
|
| 146 |
|
|
<a name="l00116"></a>00116 <span class="keyword"> .address_a(debug_addr),</span>
|
| 147 |
|
|
<a name="l00117"></a>00117 <span class="keyword"> .wren_a(debug_write == 1'b1),</span>
|
| 148 |
|
|
<a name="l00118"></a>00118 <span class="keyword"> .data_a( { mfm_decoder[11:8], dsklen, dskptr, 4'b1111 } ),</span>
|
| 149 |
|
|
<a name="l00119"></a>00119 <span class="keyword"> .q_a()</span>
|
| 150 |
|
|
<a name="l00120"></a>00120 <span class="keyword">);</span>
|
| 151 |
|
|
<a name="l00121"></a>00121 <span class="keyword">defparam </span>
|
| 152 |
|
|
<a name="l00122"></a>00122 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
|
| 153 |
|
|
<a name="l00123"></a>00123 <span class="keyword"> debug_ram_inst.width_a = 56,</span>
|
| 154 |
|
|
<a name="l00124"></a>00124 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=flop",</span>
|
| 155 |
|
|
<a name="l00125"></a>00125 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
|
| 156 |
|
|
<a name="l00126"></a>00126 <span class="keyword">*/</span>
|
| 157 |
|
|
<a name="l00127"></a>00127
|
| 158 |
|
|
<a name="l00128"></a>00128 <span class="keyword">//------------------------------------------------- video_priority DEBUG</span>
|
| 159 |
|
|
<a name="l00129"></a>00129 <span class="keyword">/*</span>
|
| 160 |
|
|
<a name="l00130"></a>00130 <span class="keyword">altsyncram debug_ram_inst(</span>
|
| 161 |
|
|
<a name="l00131"></a>00131 <span class="keyword"> .clock0(CLK_I),</span>
|
| 162 |
|
|
<a name="l00132"></a>00132 <span class="keyword"></span>
|
| 163 |
|
|
<a name="l00133"></a>00133 <span class="keyword"> .address_a(line_ram_addr),</span>
|
| 164 |
|
|
<a name="l00134"></a>00134 <span class="keyword"> .wren_a(line_ena == 1'b1 && line_number == 9'd150 && column_number >= 9'h81 &&</span>
|
| 165 |
|
|
<a name="l00135"></a>00135 <span class="keyword"> ((column_number == 9'h1C1 && line_ram_counter == 3'd1) || (column_number < 9'h1C1 && line_ram_counter == 3'd3))),</span>
|
| 166 |
|
|
<a name="l00136"></a>00136 <span class="keyword"> .data_a((column_number == 9'h1C1 && line_ram_counter == 3'd1)? { final_color_value, 24'd0 } : { line_ram_data[23:0], final_color_value }),</span>
|
| 167 |
|
|
<a name="l00137"></a>00137 <span class="keyword"> .q_a()</span>
|
| 168 |
|
|
<a name="l00138"></a>00138 <span class="keyword">);</span>
|
| 169 |
|
|
<a name="l00139"></a>00139 <span class="keyword">defparam </span>
|
| 170 |
|
|
<a name="l00140"></a>00140 <span class="keyword"> debug_ram_inst.operation_mode = "SINGLE_PORT",</span>
|
| 171 |
|
|
<a name="l00141"></a>00141 <span class="keyword"> debug_ram_inst.width_a = 36,</span>
|
| 172 |
|
|
<a name="l00142"></a>00142 <span class="keyword"> debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mem",</span>
|
| 173 |
|
|
<a name="l00143"></a>00143 <span class="keyword"> debug_ram_inst.widthad_a = 8;</span>
|
| 174 |
|
|
<a name="l00144"></a>00144 <span class="keyword">*/</span>
|
| 175 |
|
|
<a name="l00145"></a>00145
|
| 176 |
|
|
<a name="l00146"></a>00146
|
| 177 |
|
|
<a name="l00147"></a><a class="code" href="classdebug.html">00147</a> <span class="vhdlkeyword">module</span> <a class="code" href="classdebug.html">debug</a>(
|
| 178 |
|
|
<a name="l00148"></a><a class="code" href="classdebug.html#ab1c48d2e56da02d6177956ae5124fb85">00148</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdebug.html#ab1c48d2e56da02d6177956ae5124fb85">CLK_I</a>,
|
| 179 |
|
|
<a name="l00149"></a><a class="code" href="classdebug.html#a8ae6c1e7aeafd49daf6a2b9bb90fafcd">00149</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdebug.html#a8ae6c1e7aeafd49daf6a2b9bb90fafcd">reset_n</a>,
|
| 180 |
|
|
<a name="l00150"></a>00150
|
| 181 |
|
|
<a name="l00151"></a>00151 <span class="keyword">// hex output</span>
|
| 182 |
|
|
<a name="l00152"></a><a class="code" href="classdebug.html#aeb4d489be87782284f6b3d31cfc1a10c">00152</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#aeb4d489be87782284f6b3d31cfc1a10c">hex0</a>,
|
| 183 |
|
|
<a name="l00153"></a><a class="code" href="classdebug.html#abc43f973da2ad9f8af6b51599163232b">00153</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#abc43f973da2ad9f8af6b51599163232b">hex1</a>,
|
| 184 |
|
|
<a name="l00154"></a><a class="code" href="classdebug.html#afe483c1393ae8ace86ce1a7894c0d3d1">00154</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#afe483c1393ae8ace86ce1a7894c0d3d1">hex2</a>,
|
| 185 |
|
|
<a name="l00155"></a><a class="code" href="classdebug.html#a188c204136f3e91ff93037fd98128260">00155</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#a188c204136f3e91ff93037fd98128260">hex3</a>,
|
| 186 |
|
|
<a name="l00156"></a><a class="code" href="classdebug.html#ac6e75d3418af394c9a13d0bcfdfb9f36">00156</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#ac6e75d3418af394c9a13d0bcfdfb9f36">hex4</a>,
|
| 187 |
|
|
<a name="l00157"></a><a class="code" href="classdebug.html#a73cd8f3202fdd1a31986002169f70670">00157</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#a73cd8f3202fdd1a31986002169f70670">hex5</a>,
|
| 188 |
|
|
<a name="l00158"></a><a class="code" href="classdebug.html#a03d9534a0de2b1417bf086d9a00c8782">00158</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#a03d9534a0de2b1417bf086d9a00c8782">hex6</a>,
|
| 189 |
|
|
<a name="l00159"></a><a class="code" href="classdebug.html#aa71bf39a67aa1a8e7621f2678bc642d0">00159</a> <span class="vhdlkeyword">output</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#aa71bf39a67aa1a8e7621f2678bc642d0">hex7</a>,
|
| 190 |
|
|
<a name="l00160"></a>00160
|
| 191 |
|
|
<a name="l00161"></a>00161 <span class="keyword">// debug</span>
|
| 192 |
|
|
<a name="l00162"></a><a class="code" href="classdebug.html#ae5ab6f922efca9e22203914e4f84e97a">00162</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>] <a class="code" href="classdebug.html#ae5ab6f922efca9e22203914e4f84e97a">master_adr_o</a>,
|
| 193 |
|
|
<a name="l00163"></a><a class="code" href="classdebug.html#ae42440ca4b8ef53f6b05cada2f657727">00163</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#ae42440ca4b8ef53f6b05cada2f657727">debug_pc</a>,
|
| 194 |
|
|
<a name="l00164"></a><a class="code" href="classdebug.html#a55c22e045ac93efa3f7f1216413ea7ca">00164</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#a55c22e045ac93efa3f7f1216413ea7ca">debug_syscon</a>,
|
| 195 |
|
|
<a name="l00165"></a><a class="code" href="classdebug.html#aaaadb016837014fd7b8ca030b01f4e38">00165</a> <span class="vhdlkeyword">input</span> [<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#aaaadb016837014fd7b8ca030b01f4e38">debug_track</a>,
|
| 196 |
|
|
<a name="l00166"></a>00166
|
| 197 |
|
|
<a name="l00167"></a><a class="code" href="classdebug.html#a2b16e0291cc69b3a82ae88345fb15739">00167</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdebug.html#a2b16e0291cc69b3a82ae88345fb15739">debug_sw_pc</a>,
|
| 198 |
|
|
<a name="l00168"></a><a class="code" href="classdebug.html#a5e05365e3d472b0c699e6234a5ab0bf5">00168</a> <span class="vhdlkeyword">input</span> <a class="code" href="classdebug.html#a5e05365e3d472b0c699e6234a5ab0bf5">debug_sw_adr</a>
|
| 199 |
|
|
<a name="l00169"></a>00169 );
|
| 200 |
|
|
<a name="l00170"></a>00170
|
| 201 |
|
|
<a name="l00171"></a>00171 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#aeb4d489be87782284f6b3d31cfc1a10c">hex0</a> =
|
| 202 |
|
|
<a name="l00172"></a>00172 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 203 |
|
|
<a name="l00173"></a>00173 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 204 |
|
|
<a name="l00174"></a>00174 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 205 |
|
|
<a name="l00175"></a>00175 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 206 |
|
|
<a name="l00176"></a>00176 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 207 |
|
|
<a name="l00177"></a>00177 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 208 |
|
|
<a name="l00178"></a>00178 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 209 |
|
|
<a name="l00179"></a>00179 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 210 |
|
|
<a name="l00180"></a>00180 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 211 |
|
|
<a name="l00181"></a>00181 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 212 |
|
|
<a name="l00182"></a>00182 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 213 |
|
|
<a name="l00183"></a>00183 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 214 |
|
|
<a name="l00184"></a>00184 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 215 |
|
|
<a name="l00185"></a>00185 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 216 |
|
|
<a name="l00186"></a>00186 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 217 |
|
|
<a name="l00187"></a>00187 ~<span class="vhdllogic">8'b01110001</span>;
|
| 218 |
|
|
<a name="l00188"></a>00188 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#abc43f973da2ad9f8af6b51599163232b">hex1</a> =
|
| 219 |
|
|
<a name="l00189"></a>00189 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 220 |
|
|
<a name="l00190"></a>00190 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 221 |
|
|
<a name="l00191"></a>00191 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 222 |
|
|
<a name="l00192"></a>00192 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 223 |
|
|
<a name="l00193"></a>00193 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 224 |
|
|
<a name="l00194"></a>00194 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 225 |
|
|
<a name="l00195"></a>00195 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 226 |
|
|
<a name="l00196"></a>00196 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 227 |
|
|
<a name="l00197"></a>00197 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 228 |
|
|
<a name="l00198"></a>00198 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 229 |
|
|
<a name="l00199"></a>00199 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 230 |
|
|
<a name="l00200"></a>00200 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 231 |
|
|
<a name="l00201"></a>00201 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 232 |
|
|
<a name="l00202"></a>00202 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 233 |
|
|
<a name="l00203"></a>00203 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 234 |
|
|
<a name="l00204"></a>00204 ~<span class="vhdllogic">8'b01110001</span>;
|
| 235 |
|
|
<a name="l00205"></a>00205 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#afe483c1393ae8ace86ce1a7894c0d3d1">hex2</a> =
|
| 236 |
|
|
<a name="l00206"></a>00206 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 237 |
|
|
<a name="l00207"></a>00207 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 238 |
|
|
<a name="l00208"></a>00208 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 239 |
|
|
<a name="l00209"></a>00209 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 240 |
|
|
<a name="l00210"></a>00210 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 241 |
|
|
<a name="l00211"></a>00211 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 242 |
|
|
<a name="l00212"></a>00212 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 243 |
|
|
<a name="l00213"></a>00213 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 244 |
|
|
<a name="l00214"></a>00214 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 245 |
|
|
<a name="l00215"></a>00215 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 246 |
|
|
<a name="l00216"></a>00216 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 247 |
|
|
<a name="l00217"></a>00217 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 248 |
|
|
<a name="l00218"></a>00218 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 249 |
|
|
<a name="l00219"></a>00219 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 250 |
|
|
<a name="l00220"></a>00220 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 251 |
|
|
<a name="l00221"></a>00221 ~<span class="vhdllogic">8'b01110001</span>;
|
| 252 |
|
|
<a name="l00222"></a>00222 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#a188c204136f3e91ff93037fd98128260">hex3</a> =
|
| 253 |
|
|
<a name="l00223"></a>00223 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 254 |
|
|
<a name="l00224"></a>00224 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 255 |
|
|
<a name="l00225"></a>00225 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 256 |
|
|
<a name="l00226"></a>00226 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 257 |
|
|
<a name="l00227"></a>00227 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 258 |
|
|
<a name="l00228"></a>00228 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 259 |
|
|
<a name="l00229"></a>00229 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 260 |
|
|
<a name="l00230"></a>00230 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 261 |
|
|
<a name="l00231"></a>00231 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 262 |
|
|
<a name="l00232"></a>00232 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 263 |
|
|
<a name="l00233"></a>00233 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 264 |
|
|
<a name="l00234"></a>00234 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 265 |
|
|
<a name="l00235"></a>00235 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 266 |
|
|
<a name="l00236"></a>00236 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 267 |
|
|
<a name="l00237"></a>00237 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 268 |
|
|
<a name="l00238"></a>00238 ~<span class="vhdllogic">8'b01110001</span>;
|
| 269 |
|
|
<a name="l00239"></a>00239 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#ac6e75d3418af394c9a13d0bcfdfb9f36">hex4</a> =
|
| 270 |
|
|
<a name="l00240"></a>00240 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 271 |
|
|
<a name="l00241"></a>00241 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 272 |
|
|
<a name="l00242"></a>00242 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 273 |
|
|
<a name="l00243"></a>00243 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 274 |
|
|
<a name="l00244"></a>00244 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 275 |
|
|
<a name="l00245"></a>00245 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 276 |
|
|
<a name="l00246"></a>00246 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 277 |
|
|
<a name="l00247"></a>00247 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 278 |
|
|
<a name="l00248"></a>00248 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 279 |
|
|
<a name="l00249"></a>00249 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 280 |
|
|
<a name="l00250"></a>00250 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 281 |
|
|
<a name="l00251"></a>00251 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 282 |
|
|
<a name="l00252"></a>00252 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 283 |
|
|
<a name="l00253"></a>00253 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 284 |
|
|
<a name="l00254"></a>00254 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">16</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 285 |
|
|
<a name="l00255"></a>00255 ~<span class="vhdllogic">8'b01110001</span>;
|
| 286 |
|
|
<a name="l00256"></a>00256 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#a73cd8f3202fdd1a31986002169f70670">hex5</a> =
|
| 287 |
|
|
<a name="l00257"></a>00257 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 288 |
|
|
<a name="l00258"></a>00258 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 289 |
|
|
<a name="l00259"></a>00259 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 290 |
|
|
<a name="l00260"></a>00260 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 291 |
|
|
<a name="l00261"></a>00261 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 292 |
|
|
<a name="l00262"></a>00262 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 293 |
|
|
<a name="l00263"></a>00263 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 294 |
|
|
<a name="l00264"></a>00264 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 295 |
|
|
<a name="l00265"></a>00265 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 296 |
|
|
<a name="l00266"></a>00266 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 297 |
|
|
<a name="l00267"></a>00267 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 298 |
|
|
<a name="l00268"></a>00268 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 299 |
|
|
<a name="l00269"></a>00269 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 300 |
|
|
<a name="l00270"></a>00270 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 301 |
|
|
<a name="l00271"></a>00271 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">20</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 302 |
|
|
<a name="l00272"></a>00272 ~<span class="vhdllogic">8'b01110001</span>;
|
| 303 |
|
|
<a name="l00273"></a>00273 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#a03d9534a0de2b1417bf086d9a00c8782">hex6</a> =
|
| 304 |
|
|
<a name="l00274"></a>00274 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 305 |
|
|
<a name="l00275"></a>00275 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 306 |
|
|
<a name="l00276"></a>00276 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 307 |
|
|
<a name="l00277"></a>00277 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 308 |
|
|
<a name="l00278"></a>00278 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 309 |
|
|
<a name="l00279"></a>00279 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 310 |
|
|
<a name="l00280"></a>00280 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 311 |
|
|
<a name="l00281"></a>00281 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 312 |
|
|
<a name="l00282"></a>00282 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 313 |
|
|
<a name="l00283"></a>00283 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 314 |
|
|
<a name="l00284"></a>00284 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 315 |
|
|
<a name="l00285"></a>00285 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 316 |
|
|
<a name="l00286"></a>00286 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 317 |
|
|
<a name="l00287"></a>00287 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 318 |
|
|
<a name="l00288"></a>00288 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">27</span>:<span class="vhdllogic">24</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 319 |
|
|
<a name="l00289"></a>00289 ~<span class="vhdllogic">8'b01110001</span>;
|
| 320 |
|
|
<a name="l00290"></a>00290 <span class="vhdlkeyword">assign</span> <a class="code" href="classdebug.html#aa71bf39a67aa1a8e7621f2678bc642d0">hex7</a> =
|
| 321 |
|
|
<a name="l00291"></a>00291 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd0</span>) ? ~<span class="vhdllogic">8'b00111111</span> :
|
| 322 |
|
|
<a name="l00292"></a>00292 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd1</span>) ? ~<span class="vhdllogic">8'b00000110</span> :
|
| 323 |
|
|
<a name="l00293"></a>00293 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd2</span>) ? ~<span class="vhdllogic">8'b01011011</span> :
|
| 324 |
|
|
<a name="l00294"></a>00294 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd3</span>) ? ~<span class="vhdllogic">8'b01001111</span> :
|
| 325 |
|
|
<a name="l00295"></a>00295 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd4</span>) ? ~<span class="vhdllogic">8'b01100110</span> :
|
| 326 |
|
|
<a name="l00296"></a>00296 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd5</span>) ? ~<span class="vhdllogic">8'b01101101</span> :
|
| 327 |
|
|
<a name="l00297"></a>00297 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd6</span>) ? ~<span class="vhdllogic">8'b01111101</span> :
|
| 328 |
|
|
<a name="l00298"></a>00298 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd7</span>) ? ~<span class="vhdllogic">8'b00000111</span> :
|
| 329 |
|
|
<a name="l00299"></a>00299 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd8</span>) ? ~<span class="vhdllogic">8'b01111111</span> :
|
| 330 |
|
|
<a name="l00300"></a>00300 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd9</span>) ? ~<span class="vhdllogic">8'b01101111</span> :
|
| 331 |
|
|
<a name="l00301"></a>00301 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd10</span>) ? ~<span class="vhdllogic">8'b01110111</span> :
|
| 332 |
|
|
<a name="l00302"></a>00302 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd11</span>) ? ~<span class="vhdllogic">8'b01111100</span> :
|
| 333 |
|
|
<a name="l00303"></a>00303 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd12</span>) ? ~<span class="vhdllogic">8'b00111001</span> :
|
| 334 |
|
|
<a name="l00304"></a>00304 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd13</span>) ? ~<span class="vhdllogic">8'b01011110</span> :
|
| 335 |
|
|
<a name="l00305"></a>00305 (<a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">28</span>] == <span class="vhdllogic">4'd14</span>) ? ~<span class="vhdllogic">8'b01111001</span> :
|
| 336 |
|
|
<a name="l00306"></a>00306 ~<span class="vhdllogic">8'b01110001</span>;
|
| 337 |
|
|
<a name="l00307"></a><a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">00307</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a>;
|
| 338 |
|
|
<a name="l00308"></a>00308
|
| 339 |
|
|
<a name="l00309"></a><a class="code" href="classdebug.html#aca52003eff2f9d990db19c542ada30d4">00309</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classdebug.html#ab1c48d2e56da02d6177956ae5124fb85">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classdebug.html#a8ae6c1e7aeafd49daf6a2b9bb90fafcd">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 340 |
|
|
<a name="l00310"></a>00310 <span class="vhdlkeyword">if</span>(<a class="code" href="classdebug.html#a8ae6c1e7aeafd49daf6a2b9bb90fafcd">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 341 |
|
|
<a name="l00311"></a>00311 <a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a> <= <span class="vhdllogic">32'd0</span>;
|
| 342 |
|
|
<a name="l00312"></a>00312 <span class="vhdlkeyword">end</span>
|
| 343 |
|
|
<a name="l00313"></a>00313 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 344 |
|
|
<a name="l00314"></a>00314 <span class="vhdlkeyword">if</span>(<a class="code" href="classdebug.html#a2b16e0291cc69b3a82ae88345fb15739">debug_sw_pc</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a> <= <a class="code" href="classdebug.html#ae42440ca4b8ef53f6b05cada2f657727">debug_pc</a>;
|
| 345 |
|
|
<a name="l00315"></a>00315 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classdebug.html#a5e05365e3d472b0c699e6234a5ab0bf5">debug_sw_adr</a> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a> <= {<a class="code" href="classdebug.html#ae5ab6f922efca9e22203914e4f84e97a">master_adr_o</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>], <span class="vhdllogic">2'b00</span> };
|
| 346 |
|
|
<a name="l00316"></a>00316 <span class="vhdlkeyword">else</span> <a class="code" href="classdebug.html#a4eb8d9cdb91a48ab7e844fb0adc9e15b">display</a> <= { <a class="code" href="classdebug.html#aaaadb016837014fd7b8ca030b01f4e38">debug_track</a>, <span class="vhdllogic">16'd0</span>, <a class="code" href="classdebug.html#a55c22e045ac93efa3f7f1216413ea7ca">debug_syscon</a> };
|
| 347 |
|
|
<a name="l00317"></a>00317 <span class="vhdlkeyword">end</span>
|
| 348 |
|
|
<a name="l00318"></a>00318 <span class="vhdlkeyword">end</span>
|
| 349 |
|
|
<a name="l00319"></a>00319 <span class="vhdlkeyword">endmodule</span>
|
| 350 |
|
|
</pre></div></div>
|
| 351 |
|
|
</div>
|
| 352 |
|
|
<hr class="footer"/><address class="footer"><small>Generated on Sat Dec 18 2010 23:35:35 for aoOCS by 
|
| 353 |
|
|
<a href="http://www.doxygen.org/index.html">
|
| 354 |
|
|
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
|
| 355 |
|
|
</body>
|
| 356 |
|
|
</html>
|
