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/*

TODO:

- testbench specification

- on OpenCores page formating: 
make all

- WISHBONE datasheet: additional: maximum operand size

- ao68000: clean Dn, An RAM

*/

/*

Agnus: Address Generator Unit

    - Chip ram arbiter

        - odd clock (?) cycles: custom chips

        - even clock (?) cycles: CPU - 68000 can access memory every second clock cycle

    - color clocks: 280 ns, 281.94, one memory access cycle

        - 2 low resolution pixels 140 ns each

        - 4 high resolution pixels 70 ns each

        - can be synchronized to external source

    - DMA channels

    - copper: co-processor

        - finite state machine

        - executes programmed instruction stream: copper list

        - synchronized with video hardware

        - 3 states: read instruction, execute instruction, wait for beam position

        - reexecution at every new video frame

        - instructions: each four bytes

            - MOVE: write 16-bit value into chipset hardware register

            - WAIT: wait for beam position or blitter operation finish

            - SKIP: skip the following istruction if beam position already reached

        - each GUI screen can have a different resolution

        - S-HAM: sliced-HAM: swith palette on every scanline, improving HAM mode

    - blitter: block image transfer, bit blit

        - memory transfer

        - logic operation unit

        - 3 modes: copy memory block, fill block, line draw

            - copies memory images: BLOBS: blitter objects

            - copy direction: start-end, end-start

            - A,B,C sources -> D destination

            - width: multiple of 16 bits, height: in lines, stride: end of line to next line

            - barrel shift: 0 to 15 bits

            - BLOB: GUI windows

        - lines: Bresenham algorithm, single pixel thick

            - 16-bit repeating pattern

        - fill: each line from right to left

            - set pixel: toggle filling mode

*/

/*

Paula:

    - 4 independant DMA channels

        - 8-bit PCM: signed, linear, two's complement

        - hardware-mixed: two to left, two to right

    - every channel has an independent:

        - 65 level volume

        - frequency: sample rates from 20 kHz to 28867 Hz: time limit for Paula DMA ordered with video timing

    - audio hardware: four states machines: each having eight states

    - frequency or amplitude modulation

    - interrupts

    - floppy disk drive

        - read and write MFM or GCD data

        - DMA or programmed I/O

        - sync-on-word - $4489 for MFM

        - usage:

            - MFM encoding(3-pass) / decoding(1-pass) is usually performed by the blitter

            - usually one track at once, not sector-by-sector

    - serial port

        - programmed I/O only

        - no FIFO buffer

        - all possible bit rates

    - analog joystick

*/

/*

Audio notes:

- 1 word = 2 samples for every channel - for every line

- channel 1,2: left; 0,3: right;

- 8-bit signed samples

- pointer is word aligned; location and internal pointer, length also copied

- length: in words

- volume: 6 bits +1 max: 0-none, 63, 64 max

- frequency: clock ticks per sample; countdown - when 0 - next sample to DAC; min 123 (PAL), max 65535; when too fast - repeat sample

- after stop DMA - replay from start location;

- interrupt after copy of location and length is made - at the beginning

- modulate higher channel; when on - turn off audio output, even on channel 3; write new value of amplitude or period when countdown

    - volume: 7 bits; period: 16 bits; both: alternating volume, period

- lowpass filter at 7 kHz; can be disabled; min sampling rate = fmax + 7kHz; 124-256 no aliasing distortion

- direct mode: 1 word at a time; interrupt after these two samples; last value stays

*/

/* video notes:

640/16=40 fetches, 5 bitplanes x40 = 200 cycles, NTSC: 227.5 total, 226 usable, E0 = 224,

always: 4 memory refresh, 3 disk DMA, 4 audio DMA = 11 cycles

sometimes: 16 sprite DMA

rest: copper, blitter, 68000

68000 PAL: 7.09379 MHz /PAL standard=7.09375MHz/ = 2 cycles = 281.9367 ns = color cycle

68000 NTSC: 7.15909 MHz = 2 cycles = 279.3651 ns = color cycle

PAL 15.625kHz = 64 us = 227.00128 color cycles

PAL hsync 4.7 us, back 5.65 us, image 52 us, front 1.65 us

hsync = 16.67 color cycles

vsync = 25*64 us = 1.6 ms

NTSC 15.734kHz =  63.5566 us = 227.5038 color cycles

Displayable: 52 us, Not displayable: 12 us

Master PAL oscillator: 28.37516 MHz

PAL colorburst: 4.43361875 MHz = 5/4 * 3.546895 MHz /a500plus_sm/

7M: 7.09379 MHz - processor

C1: 3.546895 MHz - color clock

"Here is the solution I have found based on the ITU-601/656 standards:

Clock source: 27MHz.

27,000,000 / 429 x 455 = 28,636,363 (NTSC clock, 0 ppm)

27,000,000 / 432 x 454 = 28,375,000 (PAL clock, 6 ppm)"

http://www.opencircuits.com/Minimig_NTSC

"The PAL TV signal has 283.7516 color subcarrier cycles per scanline, 312.5 scanlines per field,

and 50 fields per second, so that gives us a color subcarrier frequency of 283.7516 * 312.5 * 50,

which equals 4433618.75 Hz, or 4.43361875 MHz. But the PAL Atari generates 228 color clocks per

scanline (the same as the NTSC Atari), and then it converts those 228 color clocks into a PAL signal.

Note that the PAL Atari's 228 color clocks per scanline are *not* drawn at the NTSC rate

(which is roughly 3579545 Hz). I'm not sure about the PAL Atari numbers, but I *think* that each of the

228 color clocks (which are neither NTSC color clocks nor PAL color clocks) have a rate of

283.7516 * 312.5 * 50 * 4 / 5 (or four-fifths the rate of a PAL color clock), which equals 3546895 Hz, or 3.546895 MHz.

Assuming the above formula is correct, you can calculate the exact PAL Atari framerate as

FR = 283.7516 * 312.5 * 50 * 4 / 5 / 228 / SL. So a 312-line frame has a framerate of approximately 49.86076 Hz."

http://atari2600.org/pipermail/stella/2008-May/020514.html

Characteristics

B,G/PAL

Number of lines per picture (frame): 625

Field frequency, nominal value (fields/s): 50

Line frequency (Hz): 15625±0.0001%

Nominal line period (µs): 64

Line-blanking interval (µs): 12±0.3

"Active" scanlines per field : 287.5 (288)

http://lipas.uwasa.fi/~f76998/video/modes/

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Vertical PAL:

Vertical blank: 0 - 29 ($1D)

Displayable no LACE: 312.5 - 29 = 283.5 = 283

Displayable LACE:    625 - (29*2) = 567

Limit VSTART: 0-255

Normal VSTART: 44 ($2C) - PAL+NTSC

Limit VSTOP /complement MSB/: 128 ($80) to 383-256=127 ($17F,$7F)

Normal VSTOP: 300-256=44 ($12C,2C) - PAL, $F4 for NTSC

Horizontal:

DDF: 4 lowres pixel resolution = 1.0 color clock, recommended 16 pixel resolution, PAL+NTSC;

DW: always lowres non-interlace, 1 lowres pixel resolution = 0.5 color clock

HW DDFSTRT limit: 24 ($18)

HW DDFSTOP limit: 216 ($D8) --> 192 color clocks, for PAL+NTSC; but custom.c says: HARD_DDF_STOP = 0xD4

25 lowres word/bitmap fetches, 49 hires word/bitmap fetches (on $D8 only one word fetch)

horizontal blanking limits to 23 lowres words/bitmap = 368 lowres pixels

Normal lowres DDFSRT: 56 ($38) = $81/2-8.5=$38, below: disables some sprites; DDFSTOP: 208 ($D0)

Normal hires DDFSRT: 60 ($3C) = $81/2-4.5=$3C; DDFSTOP: 212 ($D4)

DDFSTOP - DDFSTRT = (8(fetches per word) * (word/bitmap count - 1)) for low resolution

DDFSTOP - DDFSTRT = (4(fetches per word) * (word/bitmap count - 2)) for high resolution

160 = 4x40; 640 = 16x40; 160 = 4x(640/16)

Limit HSTART: 0 to 255; HSTOP: /-256/: 256=0 to 511-256=255

Normal HSTART: 129 ($81) - PAL+NTSC; HSTOP: 449-256=193 ($1C1,$C1) - PAL+NTSC

Horizontal blank limit = Displayable: 368 lowres pixels = 23 words/bitmap = 184 color clocks =  - PAL+NTSC

1 word fetch = 1 color clock

4.5 color clock from first fetch to disply

VPOSR: identification bits

http://www.winnicki.net/amiga/memmap/VPOSR.html

*********

audio maximum sampling rate: PAL: 28,867 samples/s, 123 ticks/sample

*/

/*

Denise:

    - video: no overlay:

        - lowres: 320x256

        - hires: 640x256

    - interlace: double vertical size

    - wide overscan: no border around graphics

    - can be synchronized to external source: genlock

        - 1-bit output: is Amiga generating backround color or not

    - bitplanes: 1 to 5

        - fetch bits and perform color lookup

    - palette of 4096 colors

    - 6th bitplane for:

        - Extra-Halfbright mode: if pixel set: brightness of regular 32 color pixel is halved

        - Hold and Modify mode, 4096 colors on screen at once, 6-bit pixel: 2-bit control + 4-bit data:

            - set(data - regular color lookup)

            - modify-red, modify-green, modify-blue (data - modify that component, leave rest unchanged)

        - dual-playfield: two playfields with 8 colors each

            - drawn on top of each other

            - independant scrolling

            - backround color of top field displays bottom field

    - 8 sprites on top of graphics

        - detect collision between: sprites, sprites and bachground

        - 3 visible colors and one transparent

        - attached sprites: 2 sprites attached making a single 15 color sprite

    - sub-pixel scrolling

    - mouse and joystick input

*/

/* Floppy notes:

ID shift register:

1) motor on -> off

2) SEL* inactive

3) SEL* inactive -> SEL* active -> read RDY* ->

MSB first, inversion needed to get $FFFF FFFF Amiga drive ID

fl_rdy_n: motor full speed - only when fl_mtr_n active OR id mode

fl_chg_n: inactive when reset or no floppy, active when selected and step

fl_wpro_n: asserted when selected

fl_tk0_n: asserted when slected and head over track 0

fl_index_n: once per revolution, between sectors

fl_mtr_n: clocked on SEL* inactive -> SEL* active, LED control

fl_side_n: inactive: side 0, active: side 1

fl_step_n: selected drive step pulse

fl_dir: inactive: higher tracks, active: lower tracks, seperate write than fl_step_n

floppy_syn_irq - always on sync word, independent of adk_con

floppy_blk_irq - DMA complete

DMA read and write one track every revolution

Synchronize CPU with specific data

Read single bytes

adk_con

    [14:13] precompensation,                                                                    not used

    [12]    0 - GCR precompensation, 1 - MFM precompensation, only MFM supported,               not used

    [10]    1 - synchronize on DSKSYNC and start DMA - read from next word,

    [9]     1 - synchronize on MSB for GCD,                                                     not used

    [8]     1 - 2us for bit of MFM, 0 - 4us for bit of GCD,                                     not used

dskptr - address, bit 0 always 0

dsklen

    [15]    secondary DMA enable

    [14]    DMA write

            second write with [15:14] == 2'b11 starts DMA write to floppy

            single write with [15:14] == 2'b0X resets counter

            second write with [15:14] == 2'b10 starts DMA read from floppy

    [13:0]  number of words move

dskbytr

    [15]    1 - byte read ready, cleaned after read

    [14]    1 - DMA is on: in DMACON and DSKLEN

    [13]    dsklen[14]

    [12]    dsksync match, for at least 2us

    [7:0]   read byte

dsksync - sync word

transfer: dskptr += 2; size -= 1;

DMA write: last 3 bits lost

DMA read: last word may not be read, single byte read: always ok (?),       (implemented: always all words read)

80 cylinders/160 tracks

Track: gap (nulls) | 11 sectors

Sector MFM encoded:

odd bits of segment, even bits of segment

encoding: data -> MFM

1 -> 01

MFM sync mark value: $4489

checksum: simple XOR

*/

/* vga_eth_capture notes:

Send UDP packet:

ethernet

    dest mac(6), src mac(6), type(2 = 0x0800 IPv4)

ip

    version,header([1] = 0x45), tos([1] = 0x00), length([2] = 4*5 + 4*2 + len = 990 = 0x03DE)

    id([2] = 0x0000), flags,offset([2] = 0x40, 0x00)

    ttl([1] = 0x0F), protocol([1] = 0x11), header checksum([2] = 0)

    source ip([4])

    dest ip([4])

udp

    source port([2]), dest port([2])

    length([2] = 8 + len = 970 = 0x03CA), checksum([2] = 0)

data

    (len = line num(2) + line(640*12/8 = 960) = 962)

--full ethernet packet len = 990 + 14 = 1004 = 0x03EC

DM9000A control to send:

    set IMR(FFh = 0x80)

    set checksum reg (31h = 0x05)

    set early transmit (30h = 0x83) ? threshold 75%

    power-up PHY (1Fh = 0x00)

    dummy MWCDM ?

    DO

        packet I

        set MWCMD(F8h = 16-bit data)

        wait for packet II

        read TX(02h bit 0 == 0)

        set TXPLL(FCh = low byte)

        set TXPLH(FDh = high byte)

        write TX(02h 0x01)

        packet II

        set MWCMD(F8h = 16-bit data)

        wait for packet I

        read TX(02h bit 0 == 0)

        set TXPLL(FCh = low byte)

        set TXPLH(FDh = high byte)

        write TX(02h 0x01)

    LOOP

*/

/* bus_terminator notes:

 32'h00E80000  --> from PC: 0x00FC503A

 problem: PC: 0x00FCAC04, access: 0 ? -> read from ocs_video -> solved

 problem: PC: 0x00FE9318, access: 0 ?

 32'h00DFF0A4

 32'h00DFF008

 32'h00DFF034

 32'h00DFF014

 32'h00DFF0FC

 32'h00dc003c rtc

 32'h00d8003c rtc ?

 32'hFFFFFFFC at PC: 0x00FF5A10, while LoadWB - also in uae: 0+0xFFFFFFFF -> in 24-bit addressing ok,

      but in 32-bit addressing not ok

*/

/* cia8520 notes:

    - name: 8520(1MHz, A - 2MHz, both used in different Amiga models)

    - clock input: 0.709379 Mhz

    - peripheral interfacing:

        - serial I/O: internal bidirectional 8-bit shift-register

            - input: clocked with external source

            - output: clocked with internal timer

            - interrupt generated when transfer completed

        - parallel I/O: 2x 8-bit, each line: input or output, read always returned current state

            - two control lines: /FLAG, /PAGE coordinated multiple CIA + parallel I/O: for Centronics Port

    - system timers

        - 2 programmable interval timers with submicrosecond precision

        - can take input from external input: CNT

        - each timer has a:

            - 16-bit read-only register: down counter

            - 16-bit write-only latch

            - at underflow: interrupt and/or gated to second I/O port: PB6(timer A),PB7(timer B), overrides direction

            - modes: once, continuous

    - Time-of-Day clock:

        - 1 read/write 24-bit binary counter: read: read stop MSB, read continue LSB, write: stop MSB(?), start LSB

        - after reset: 1:00:00.0 (from 6526)

        - alarm clock: interrupt at given time

            - write only

            - at same address as TOD, selected by control bit

    - output: pulse pin

    - input: edge detection

    - CIA-B: even: 0: floppy control, serial control, some parallel port status

    - CIA-A: odd: 1: parallel port, keyboard, some floppy support, joystick and mouse buttons

 Diffrences:

 Timer A,B: CNT transitions: not transitions but pulses: as cnt_i == 1'b0

 pc_n == 1'b0 one cycle after port B access, not 3 cycles.

 serial output cnt_o

*/

/*

Low-Pass filter: LED-filter

    - analog filter

    - external to Paula

    - 12 dB/octet Butterworth low-pass filter at 3.3 kHz

    - applied globally to all 4 channels

Static low-pass filter: models before Amiga 1200

    - static "tone knob" type low-pass filter

    - enabled regardless of the optional LED-filter

    - 6 dB/octet low-passfilter with cut-off at 4.5 kHz or 5 kHz

*/

/*

Gary: A500,A2000,CDTV

    - glue logic for bus control

    - support functions for floppy drive

*/

/* ECS only

Agnus

    BLTCON0L    ~05A  W   A( E!)  Blitter control 0, lower 8 bits (minterms)

    BLTSIZV     ~05C  W   A( E!)  Blitter V size (for 15 bit vertical size)

    BLTSIZH     ~05E  W   A( E!)  Blitter H size and start (for 11 bit H size)

    SPRHDAT     ~078  W   A( E!)  Ext. logic UHRES sprite pointer and data id

    HTOTAL       1C0  W   A( E!)  Highest number count, horiz line (VARBEAMEN=1)

    HSSTOP       1C2  W   A( E!)  Horizontal line position for HSYNC stop

    HBSTRT       1C4  W   A( E!)  Horizontal line position for HBLANK start

    HBSTOP       1C6  W   A( E!)  Horizontal line position for HBLANK stop

    VTOTAL       1C8  W   A( E!)  Highest numbered vertical line (VARBEAMEN=1)

    VSSTOP       1CA  W   A( E!)  Vertical line position for VSYNC stop

    VBSTRT       1CC  W   A( E!)  Vertical line for VBLANK start

    VBSTOP       1CE  W   A( E!)  Vertical line for VBLANK stop

    BEAMCON0     1DC  W   A( E!)  Beam counter control register (SHRES,PAL)

    HSSTRT       1DE  W   A( E!)  Horizontal sync start (VARHSY)

    VSSTRT       1E0  W   A( E!)  Vertical sync start   (VARVSY)

    HCENTER      1E2  W   A( E!)  Horizontal position for Vsync on interlace

Denise

    DENISEID    ~07C  R   D( E!)  Chip revision level for Denise (video out chip)

    BPLCON3      106  W   D( E!)  Bitplane control (enhanced features)

    DIWHIGH      1E4  W   AD( E!) Display window -  upper bits for start, stop

*/

/* From operations:

 * 
Setting up the core

 *

 * 
Resetting the core

 *

 * 
Modes and states

 */