OpenCores
URL https://opencores.org/ocsvn/aoocs/aoocs/trunk

Subversion Repositories aoocs

[/] [aoocs/] [trunk/] [rtl/] [bus_syscon.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 alfik 
/*
2 
 * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
3 
 *
4 
 * Redistribution and use in source and binary forms, with or without modification, are
5 
 * permitted provided that the following conditions are met:
6 
 *
7 
 *  1. Redistributions of source code must retain the above copyright notice, this list of
8 
 *     conditions and the following disclaimer.
9 
 *
10 
 *  2. Redistributions in binary form must reproduce the above copyright notice, this list
11 
 *     of conditions and the following disclaimer in the documentation and/or other materials
12 
 *     provided with the distribution.
13 
 *
14 
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 
 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
17 
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
21 
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
22 
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 
 */
24 
 
25 
/*! \file
26 
 * \brief WISHBONE priority and round-robin SYSCON.
27 
 */
28 
 
29 
/*! \brief \copybrief bus_syscon.v
30 
*/
31 
module bus_syscon(
32 
    //% \name Clock and reset
33 
    //% @{
34 
    input CLK_I,
35 
    input reset_n,
36 
    input halt_switch,
37 
    //% @}
38 
 
39 
    //% \name Priority WISHBONE master interfaces
40 
    //% @{
41 
    input           masterP_cyc_o,
42 
    input           masterP_stb_o,
43 
    input           masterP_we_o,
44 
    input   [31:2]  masterP_adr_o,
45 
    input   [3:0]   masterP_sel_o,
46 
    input   [31:0]  masterP_dat_o,
47 
    output          masterP_ack_i,
48 
    output          masterP_rty_i,
49 
    output          masterP_err_i,
50 
    //% @}
51 
 
52 
    //% \name Round-robin WISHBONE master interfaces
53 
    //% @{
54 
    input           masterR1_cyc_o,
55 
    input           masterR1_stb_o,
56 
    input           masterR1_we_o,
57 
    input   [31:2]  masterR1_adr_o,
58 
    input   [3:0]   masterR1_sel_o,
59 
    input   [31:0]  masterR1_dat_o,
60 
    output          masterR1_ack_i,
61 
    output          masterR1_rty_i,
62 
    output          masterR1_err_i,
63 
 
64 
    input           masterR2_cyc_o,
65 
    input           masterR2_stb_o,
66 
    input           masterR2_we_o,
67 
    input   [31:2]  masterR2_adr_o,
68 
    input   [3:0]   masterR2_sel_o,
69 
    input   [31:0]  masterR2_dat_o,
70 
    output          masterR2_ack_i,
71 
    output          masterR2_rty_i,
72 
    output          masterR2_err_i,
73 
 
74 
    input           masterR3_cyc_o,
75 
    input           masterR3_stb_o,
76 
    input           masterR3_we_o,
77 
    input   [31:2]  masterR3_adr_o,
78 
    input   [3:0]   masterR3_sel_o,
79 
    input   [31:0]  masterR3_dat_o,
80 
    output          masterR3_ack_i,
81 
    output          masterR3_rty_i,
82 
    output          masterR3_err_i,
83 
 
84 
    input           masterR4_cyc_o,
85 
    input           masterR4_stb_o,
86 
    input           masterR4_we_o,
87 
    input   [31:2]  masterR4_adr_o,
88 
    input   [3:0]   masterR4_sel_o,
89 
    input   [31:0]  masterR4_dat_o,
90 
    output          masterR4_ack_i,
91 
    output          masterR4_rty_i,
92 
    output          masterR4_err_i,
93 
 
94 
    input           masterR5_cyc_o,
95 
    input           masterR5_stb_o,
96 
    input           masterR5_we_o,
97 
    input   [31:2]  masterR5_adr_o,
98 
    input   [3:0]   masterR5_sel_o,
99 
    input   [31:0]  masterR5_dat_o,
100 
    output          masterR5_ack_i,
101 
    output          masterR5_rty_i,
102 
    output          masterR5_err_i,
103 
 
104 
    input           masterR6_cyc_o,
105 
    input           masterR6_stb_o,
106 
    input           masterR6_we_o,
107 
    input   [31:2]  masterR6_adr_o,
108 
    input   [3:0]   masterR6_sel_o,
109 
    input   [31:0]  masterR6_dat_o,
110 
    output          masterR6_ack_i,
111 
    output          masterR6_rty_i,
112 
    output          masterR6_err_i,
113 
 
114 
    input           masterR7_cyc_o,
115 
    input           masterR7_stb_o,
116 
    input           masterR7_we_o,
117 
    input   [31:2]  masterR7_adr_o,
118 
    input   [3:0]   masterR7_sel_o,
119 
    input   [31:0]  masterR7_dat_o,
120 
    output          masterR7_ack_i,
121 
    output          masterR7_rty_i,
122 
    output          masterR7_err_i,
123 
    //% @}
124 
 
125 
    //% \name Common WISHBONE master signals
126 
    //% @{
127 
    output  [31:2]  master_adr_o,
128 
    output          master_we_o,
129 
    output  [3:0]   master_sel_o,
130 
    output  [31:0]  master_dat_o,
131 
    output  [31:0]  slave_dat_o,
132 
    //% @}
133 
 
134 
    //% \name AND/OR master address mask signals
135 
    //% @{
136 
    output  [31:2]  master_adr_early_o,
137 
    input   [31:2]  master_adr_and_mask,
138 
    input   [31:2]  master_adr_or_mask,
139 
    //% @}
140 
 
141 
    //% \name WISHBONE slave interfaces
142 
    //% @{
143 
    output          slave0_cyc_i,
144 
    output          slave0_stb_i,
145 
    input           slave0_ack_o,
146 
    input           slave0_rty_o,
147 
    input           slave0_err_o,
148 
    input   [31:0]  slave0_dat_o,
149 
 
150 
    input           slave1_selected,
151 
    output          slave1_cyc_i,
152 
    output          slave1_stb_i,
153 
    input           slave1_ack_o,
154 
    input           slave1_rty_o,
155 
    input           slave1_err_o,
156 
    input   [31:0]  slave1_dat_o,
157 
 
158 
    input           slave2_selected,
159 
    output          slave2_cyc_i,
160 
    output          slave2_stb_i,
161 
    input           slave2_ack_o,
162 
    input           slave2_rty_o,
163 
    input           slave2_err_o,
164 
    input   [31:0]  slave2_dat_o,
165 
 
166 
    input           slave3_selected,
167 
    output          slave3_cyc_i,
168 
    output          slave3_stb_i,
169 
    input           slave3_ack_o,
170 
    input           slave3_rty_o,
171 
    input           slave3_err_o,
172 
    input   [31:0]  slave3_dat_o,
173 
 
174 
    input           slave4_selected,
175 
    output          slave4_cyc_i,
176 
    output          slave4_stb_i,
177 
    input           slave4_ack_o,
178 
    input           slave4_rty_o,
179 
    input           slave4_err_o,
180 
    input   [31:0]  slave4_dat_o,
181 
 
182 
    input           slave5_selected,
183 
    output          slave5_cyc_i,
184 
    output          slave5_stb_i,
185 
    input           slave5_ack_o,
186 
    input           slave5_rty_o,
187 
    input           slave5_err_o,
188 
    input   [31:0]  slave5_dat_o,
189 
 
190 
    input           slave6_selected,
191 
    output          slave6_cyc_i,
192 
    output          slave6_stb_i,
193 
    input           slave6_ack_o,
194 
    input           slave6_rty_o,
195 
    input           slave6_err_o,
196 
    input   [31:0]  slave6_dat_o,
197 
 
198 
    input           slave7_selected,
199 
    output          slave7_cyc_i,
200 
    output          slave7_stb_i,
201 
    input           slave7_ack_o,
202 
    input           slave7_rty_o,
203 
    input           slave7_err_o,
204 
    input   [31:0]  slave7_dat_o,
205 
 
206 
    input           slave8_selected,
207 
    output          slave8_cyc_i,
208 
    output          slave8_stb_i,
209 
    input           slave8_ack_o,
210 
    input           slave8_rty_o,
211 
    input           slave8_err_o,
212 
    input   [31:0]  slave8_dat_o,
213 
 
214 
    input           slave9_selected,
215 
    output          slave9_cyc_i,
216 
    output          slave9_stb_i,
217 
    input           slave9_ack_o,
218 
    input           slave9_rty_o,
219 
    input           slave9_err_o,
220 
    input   [31:0]  slave9_dat_o,
221 
 
222 
    input           slave10_selected,
223 
    output          slave10_cyc_i,
224 
    output          slave10_stb_i,
225 
    input           slave10_ack_o,
226 
    input           slave10_rty_o,
227 
    input           slave10_err_o,
228 
    input   [31:0]  slave10_dat_o,
229 
 
230 
    input           slave11_selected,
231 
    output          slave11_cyc_i,
232 
    output          slave11_stb_i,
233 
    input           slave11_ack_o,
234 
    input           slave11_rty_o,
235 
    input           slave11_err_o,
236 
    input   [31:0]  slave11_dat_o,
237 
 
238 
    input           slave12_selected,
239 
    output          slave12_cyc_i,
240 
    output          slave12_stb_i,
241 
    input           slave12_ack_o,
242 
    input           slave12_rty_o,
243 
    input           slave12_err_o,
244 
    input   [31:0]  slave12_dat_o,
245 
 
246 
    input           slave13_selected,
247 
    output          slave13_cyc_i,
248 
    output          slave13_stb_i,
249 
    input           slave13_ack_o,
250 
    input           slave13_rty_o,
251 
    input           slave13_err_o,
252 
    input   [31:0]  slave13_dat_o,
253 
 
254 
    input           slave14_selected,
255 
    output          slave14_cyc_i,
256 
    output          slave14_stb_i,
257 
    input           slave14_ack_o,
258 
    input           slave14_rty_o,
259 
    input           slave14_err_o,
260 
    input   [31:0]  slave14_dat_o,
261 
 
262 
    input           slave15_selected,
263 
    output          slave15_cyc_i,
264 
    output          slave15_stb_i,
265 
    input           slave15_ack_o,
266 
    input           slave15_rty_o,
267 
    input           slave15_err_o,
268 
    input   [31:0]  slave15_dat_o,
269 
 
270 
    //% \name Debug signals
271 
    //% @{
272 
    output [7:0]    debug_syscon
273 
    //% @}
274 
);
275 
assign debug_syscon = { 3'b0, last_master_reg };
276 
 
277 
assign master_adr_early_o =
278 
    (last_master_reg == 5'd1)?  masterP_adr_o :
279 
    (last_master_reg == 5'd2)?  masterR1_adr_o :
280 
    (last_master_reg == 5'd3)?  masterR2_adr_o :
281 
    (last_master_reg == 5'd4)?  masterR3_adr_o :
282 
    (last_master_reg == 5'd5)?  masterR4_adr_o :
283 
    (last_master_reg == 5'd6)?  masterR5_adr_o :
284 
    (last_master_reg == 5'd7)?  masterR6_adr_o :
285 
                                masterR7_adr_o;
286 
 
287 
assign master_adr_o = (master_adr_early_o & master_adr_and_mask) | master_adr_or_mask;
288 
 
289 
assign master_we_o =
290 
    (last_master_reg == 5'd1)?  masterP_we_o :
291 
    (last_master_reg == 5'd2)?  masterR1_we_o :
292 
    (last_master_reg == 5'd3)?  masterR2_we_o :
293 
    (last_master_reg == 5'd4)?  masterR3_we_o :
294 
    (last_master_reg == 5'd5)?  masterR4_we_o :
295 
    (last_master_reg == 5'd6)?  masterR5_we_o :
296 
    (last_master_reg == 5'd7)?  masterR6_we_o :
297 
                                masterR7_we_o;
298 
assign master_sel_o =
299 
    (last_master_reg == 5'd1)?  masterP_sel_o :
300 
    (last_master_reg == 5'd2)?  masterR1_sel_o :
301 
    (last_master_reg == 5'd3)?  masterR2_sel_o :
302 
    (last_master_reg == 5'd4)?  masterR3_sel_o :
303 
    (last_master_reg == 5'd5)?  masterR4_sel_o :
304 
    (last_master_reg == 5'd6)?  masterR5_sel_o :
305 
    (last_master_reg == 5'd7)?  masterR6_sel_o :
306 
                                masterR7_sel_o;
307 
assign master_dat_o =
308 
    (last_master_reg == 5'd1)?  masterP_dat_o :
309 
    (last_master_reg == 5'd2)?  masterR1_dat_o :
310 
    (last_master_reg == 5'd3)?  masterR2_dat_o :
311 
    (last_master_reg == 5'd4)?  masterR3_dat_o :
312 
    (last_master_reg == 5'd5)?  masterR4_dat_o :
313 
    (last_master_reg == 5'd6)?  masterR5_dat_o :
314 
    (last_master_reg == 5'd7)?  masterR6_dat_o :
315 
                                masterR7_dat_o;
316 
wire master_cyc_stb_o =
317 
    (last_master_reg == 5'd1    && masterP_stb_o == 1'b1  && masterP_cyc_o == 1'b1) ||
318 
    (last_master_reg == 5'd2    && masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ||
319 
    (last_master_reg == 5'd3    && masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ||
320 
    (last_master_reg == 5'd4    && masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ||
321 
    (last_master_reg == 5'd5    && masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ||
322 
    (last_master_reg == 5'd6    && masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ||
323 
    (last_master_reg == 5'd7    && masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ||
324 
    (last_master_reg == 5'd8    && masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1);
325 
 
326 
assign masterP_ack_i = master_ack_i && last_master_reg == 5'd1;
327 
assign masterP_rty_i = master_rty_i && last_master_reg == 5'd1;
328 
assign masterP_err_i = master_err_i && last_master_reg == 5'd1;
329 
 
330 
assign masterR1_ack_i = master_ack_i && last_master_reg == 5'd2;
331 
assign masterR1_rty_i = master_rty_i && last_master_reg == 5'd2;
332 
assign masterR1_err_i = master_err_i && last_master_reg == 5'd2;
333 
 
334 
assign masterR2_ack_i = master_ack_i && last_master_reg == 5'd3;
335 
assign masterR2_rty_i = master_rty_i && last_master_reg == 5'd3;
336 
assign masterR2_err_i = master_err_i && last_master_reg == 5'd3;
337 
 
338 
assign masterR3_ack_i = master_ack_i && last_master_reg == 5'd4;
339 
assign masterR3_rty_i = master_rty_i && last_master_reg == 5'd4;
340 
assign masterR3_err_i = master_err_i && last_master_reg == 5'd4;
341 
 
342 
assign masterR4_ack_i = master_ack_i && last_master_reg == 5'd5;
343 
assign masterR4_rty_i = master_rty_i && last_master_reg == 5'd5;
344 
assign masterR4_err_i = master_err_i && last_master_reg == 5'd5;
345 
 
346 
assign masterR5_ack_i = master_ack_i && last_master_reg == 5'd6;
347 
assign masterR5_rty_i = master_rty_i && last_master_reg == 5'd6;
348 
assign masterR5_err_i = master_err_i && last_master_reg == 5'd6;
349 
 
350 
assign masterR6_ack_i = master_ack_i && last_master_reg == 5'd7;
351 
assign masterR6_rty_i = master_rty_i && last_master_reg == 5'd7;
352 
assign masterR6_err_i = master_err_i && last_master_reg == 5'd7;
353 
 
354 
assign masterR7_ack_i = master_ack_i && last_master_reg == 5'd8;
355 
assign masterR7_rty_i = master_rty_i && last_master_reg == 5'd8;
356 
assign masterR7_err_i = master_err_i && last_master_reg == 5'd8;
357 
 
358 
wire slave0_selected =
359 
    slave1_selected == 1'b0 &&
360 
    slave2_selected == 1'b0 &&
361 
    slave3_selected == 1'b0 &&
362 
    slave4_selected == 1'b0 &&
363 
    slave5_selected == 1'b0 &&
364 
    slave6_selected == 1'b0 &&
365 
    slave7_selected == 1'b0 &&
366 
    slave8_selected == 1'b0 &&
367 
    slave9_selected == 1'b0 &&
368 
    slave10_selected == 1'b0 &&
369 
    slave11_selected == 1'b0 &&
370 
    slave12_selected == 1'b0 &&
371 
    slave13_selected == 1'b0 &&
372 
    slave14_selected == 1'b0 &&
373 
    slave15_selected == 1'b0;
374 
 
375 
assign { slave0_cyc_i, slave0_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave0_selected == 1'b1)} };
376 
assign { slave1_cyc_i, slave1_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave1_selected == 1'b1)} };
377 
assign { slave2_cyc_i, slave2_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave2_selected == 1'b1)} };
378 
assign { slave3_cyc_i, slave3_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave3_selected == 1'b1)} };
379 
assign { slave4_cyc_i, slave4_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave4_selected == 1'b1)} };
380 
assign { slave5_cyc_i, slave5_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave5_selected == 1'b1)} };
381 
assign { slave6_cyc_i, slave6_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave6_selected == 1'b1)} };
382 
assign { slave7_cyc_i, slave7_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave7_selected == 1'b1)} };
383 
assign { slave8_cyc_i, slave8_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave8_selected == 1'b1)} };
384 
assign { slave9_cyc_i, slave9_stb_i }   = { 2{(master_cyc_stb_o == 1'b1) && (slave9_selected == 1'b1)} };
385 
assign { slave10_cyc_i, slave10_stb_i } = { 2{(master_cyc_stb_o == 1'b1) && (slave10_selected == 1'b1)} };
386 
assign { slave11_cyc_i, slave11_stb_i } = { 2{(master_cyc_stb_o == 1'b1) && (slave11_selected == 1'b1)} };
387 
assign { slave12_cyc_i, slave12_stb_i } = { 2{(master_cyc_stb_o == 1'b1) && (slave12_selected == 1'b1)} };
388 
assign { slave13_cyc_i, slave13_stb_i } = { 2{(master_cyc_stb_o == 1'b1) && (slave13_selected == 1'b1)} };
389 
assign { slave14_cyc_i, slave14_stb_i } = { 2{(master_cyc_stb_o == 1'b1) && (slave14_selected == 1'b1)} };
390 
assign { slave15_cyc_i, slave15_stb_i } = { 2{(master_cyc_stb_o == 1'b1) && (slave15_selected == 1'b1)} };
391 
 
392 
assign slave_dat_o =
393 
    (slave0_selected == 1'b1) ?     slave0_dat_o :
394 
    (slave1_selected == 1'b1) ?     slave1_dat_o :
395 
    (slave2_selected == 1'b1) ?     slave2_dat_o :
396 
    (slave3_selected == 1'b1) ?     slave3_dat_o :
397 
    (slave4_selected == 1'b1) ?     slave4_dat_o :
398 
    (slave5_selected == 1'b1) ?     slave5_dat_o :
399 
    (slave6_selected == 1'b1) ?     slave6_dat_o :
400 
    (slave7_selected == 1'b1) ?     slave7_dat_o :
401 
    (slave8_selected == 1'b1) ?     slave8_dat_o :
402 
    (slave9_selected == 1'b1) ?     slave9_dat_o :
403 
    (slave10_selected == 1'b1) ?    slave10_dat_o :
404 
    (slave11_selected == 1'b1) ?    slave11_dat_o :
405 
    (slave12_selected == 1'b1) ?    slave12_dat_o :
406 
    (slave13_selected == 1'b1) ?    slave13_dat_o :
407 
    (slave14_selected == 1'b1) ?    slave14_dat_o :
408 
    slave15_dat_o;
409 
 
410 
 
411 
wire master_ack_i =
412 
    (slave0_selected == 1'b1) ?     slave0_ack_o :
413 
    (slave1_selected == 1'b1) ?     slave1_ack_o :
414 
    (slave2_selected == 1'b1) ?     slave2_ack_o :
415 
    (slave3_selected == 1'b1) ?     slave3_ack_o :
416 
    (slave4_selected == 1'b1) ?     slave4_ack_o :
417 
    (slave5_selected == 1'b1) ?     slave5_ack_o :
418 
    (slave6_selected == 1'b1) ?     slave6_ack_o :
419 
    (slave7_selected == 1'b1) ?     slave7_ack_o :
420 
    (slave8_selected == 1'b1) ?     slave8_ack_o :
421 
    (slave9_selected == 1'b1) ?     slave9_ack_o :
422 
    (slave10_selected == 1'b1) ?    slave10_ack_o :
423 
    (slave11_selected == 1'b1) ?    slave11_ack_o :
424 
    (slave12_selected == 1'b1) ?    slave12_ack_o :
425 
    (slave13_selected == 1'b1) ?    slave13_ack_o :
426 
    (slave14_selected == 1'b1) ?    slave14_ack_o :
427 
                                    slave15_ack_o;
428 
wire master_rty_i =
429 
    (slave0_selected == 1'b1) ?     slave0_rty_o :
430 
    (slave1_selected == 1'b1) ?     slave1_rty_o :
431 
    (slave2_selected == 1'b1) ?     slave2_rty_o :
432 
    (slave3_selected == 1'b1) ?     slave3_rty_o :
433 
    (slave4_selected == 1'b1) ?     slave4_rty_o :
434 
    (slave5_selected == 1'b1) ?     slave5_rty_o :
435 
    (slave6_selected == 1'b1) ?     slave6_rty_o :
436 
    (slave7_selected == 1'b1) ?     slave7_rty_o :
437 
    (slave8_selected == 1'b1) ?     slave8_rty_o :
438 
    (slave9_selected == 1'b1) ?     slave9_rty_o :
439 
    (slave10_selected == 1'b1) ?    slave10_rty_o :
440 
    (slave11_selected == 1'b1) ?    slave11_rty_o :
441 
    (slave12_selected == 1'b1) ?    slave12_rty_o :
442 
    (slave13_selected == 1'b1) ?    slave13_rty_o :
443 
    (slave14_selected == 1'b1) ?    slave14_rty_o :
444 
                                    slave15_rty_o;
445 
wire master_err_i =
446 
    (slave0_selected == 1'b1) ?     slave0_err_o :
447 
    (slave1_selected == 1'b1) ?     slave1_err_o :
448 
    (slave2_selected == 1'b1) ?     slave2_err_o :
449 
    (slave3_selected == 1'b1) ?     slave3_err_o :
450 
    (slave4_selected == 1'b1) ?     slave4_err_o :
451 
    (slave5_selected == 1'b1) ?     slave5_err_o :
452 
    (slave6_selected == 1'b1) ?     slave6_err_o :
453 
    (slave7_selected == 1'b1) ?     slave7_err_o :
454 
    (slave8_selected == 1'b1) ?     slave8_err_o :
455 
    (slave9_selected == 1'b1) ?     slave9_err_o :
456 
    (slave10_selected == 1'b1) ?    slave10_err_o :
457 
    (slave11_selected == 1'b1) ?    slave11_err_o :
458 
    (slave12_selected == 1'b1) ?    slave12_err_o :
459 
    (slave13_selected == 1'b1) ?    slave13_err_o :
460 
    (slave14_selected == 1'b1) ?    slave14_err_o :
461 
                                    slave15_err_o;
462 
 
463 
wire [4:0] last_master =
464 
    (last_master_reg == 5'd0) ?
465 
    (
466 
        (halt_switch == 1'b1) ?                                                         5'd0 :
467 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
468 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
469 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
470 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
471 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
472 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
473 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
474 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
475 
                                                                                        5'd0
476 
    ) :
477 
 
478 
    (last_master_reg == 5'd1) ?
479 
    (
480 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd1 :
481 
        (halt_switch == 1'b1) ?                                                         5'd0 :
482 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
483 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
484 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
485 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
486 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
487 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
488 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
489 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
490 
                                                                                        5'd1
491 
    ) :
492 
 
493 
    (last_master_reg == 5'd2) ?
494 
    (
495 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd2 :
496 
        (halt_switch == 1'b1) ?                                                         5'd0 :
497 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
498 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
499 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
500 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
501 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
502 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
503 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
504 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
505 
                                                                                        5'd2
506 
    ) :
507 
 
508 
    (last_master_reg == 5'd3) ?
509 
    (
510 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd3 :
511 
        (halt_switch == 1'b1) ?                                                         5'd0 :
512 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
513 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
514 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
515 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
516 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
517 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
518 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
519 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
520 
                                                                                        5'd3
521 
    ) :
522 
 
523 
    (last_master_reg == 5'd4) ?
524 
    (
525 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd4 :
526 
        (halt_switch == 1'b1) ?                                                         5'd0 :
527 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
528 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
529 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
530 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
531 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
532 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
533 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
534 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
535 
                                                                                        5'd4
536 
    ) :
537 
 
538 
    (last_master_reg == 5'd5) ?
539 
    (
540 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd5 :
541 
        (halt_switch == 1'b1) ?                                                         5'd0 :
542 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
543 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
544 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
545 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
546 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
547 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
548 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
549 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
550 
                                                                                        5'd5
551 
    ) :
552 
 
553 
    (last_master_reg == 5'd6) ?
554 
    (
555 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd6 :
556 
        (halt_switch == 1'b1) ?                                                         5'd0 :
557 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
558 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
559 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
560 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
561 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
562 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
563 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
564 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
565 
                                                                                        5'd6
566 
    ) :
567 
 
568 
    (last_master_reg == 5'd7) ?
569 
    (
570 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd7 :
571 
        (halt_switch == 1'b1) ?                                                         5'd0 :
572 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
573 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
574 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
575 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
576 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
577 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
578 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
579 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
580 
                                                                                        5'd7
581 
    ) :
582 
 
583 
    (last_master_reg == 5'd8) ?
584 
    (
585 
        (master_cyc_stb_o == 1'b1) ?                                                    5'd8 :
586 
        (halt_switch == 1'b1) ?                                                         5'd0 :
587 
            (masterP_stb_o == 1'b1 && masterP_cyc_o == 1'b1) ?                          5'd1 :
588 
        (masterR1_stb_o == 1'b1 && masterR1_cyc_o == 1'b1) ?                            5'd2 :
589 
        (masterR2_stb_o == 1'b1 && masterR2_cyc_o == 1'b1) ?                            5'd3 :
590 
        (masterR3_stb_o == 1'b1 && masterR3_cyc_o == 1'b1) ?                            5'd4 :
591 
        (masterR4_stb_o == 1'b1 && masterR4_cyc_o == 1'b1) ?                            5'd5 :
592 
        (masterR5_stb_o == 1'b1 && masterR5_cyc_o == 1'b1) ?                            5'd6 :
593 
        (masterR6_stb_o == 1'b1 && masterR6_cyc_o == 1'b1) ?                            5'd7 :
594 
        (masterR7_stb_o == 1'b1 && masterR7_cyc_o == 1'b1) ?                            5'd8 :
595 
                                                                                        5'd8
596 
    ) :
597 
 
598 
    5'd0;
599 
 
600 
reg [4:0] last_master_reg;
601 
 
602 
always @(posedge CLK_I or negedge reset_n) begin
603 
    if(reset_n == 1'b0) last_master_reg <= 5'd0;
604 
    else                last_master_reg <= last_master;
605 
end
606 
 
607 
endmodule
608 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.