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alfik |
/*
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* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are
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* permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*! \file
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* \brief Terminator for not handled WISHBONE bus cycles.
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*/
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/*! \brief \copybrief bus_terminator.v
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*/
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module bus_terminator(
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//% \name Clock and reset
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//% @{
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input CLK_I,
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input reset_n,
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//% @}
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//% \name WISHBONE slave
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//% @{
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input [31:2] ADR_I,
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input CYC_I,
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input WE_I,
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input STB_I,
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input [3:0] SEL_I,
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input [31:0] slave_DAT_I,
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output [31:0] slave_DAT_O,
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output reg ACK_O,
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output reg RTY_O,
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output ERR_O,
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//% @}
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//% \name ao68000 interrupt cycle indicator
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//% @{
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input cpu_space_cycle
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//% @}
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);
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assign ERR_O = 1'b0;
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assign slave_DAT_O = 32'd0;
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wire accepted_addresses =
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({ADR_I, 2'b00} >= 32'h00F00000 && {ADR_I, 2'b00} <= 32'h00F7FFFC) ||
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({ADR_I, 2'b00} >= 32'h00E80000 && {ADR_I, 2'b00} <= 32'h00EFFFFC) ||
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// Lotus2
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({ADR_I, 2'b00} >= 32'h00200000 && {ADR_I, 2'b00} <= 32'h009FFFFF) ||
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// Pinball Dreams
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{ADR_I, 2'b00} == 32'h00DFF11C ||
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{ADR_I, 2'b00} == 32'h00DFF1FC ||
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{ADR_I, 2'b00} == 32'h00DFF0FC ||
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{ADR_I, 2'b00} == 32'h00DC003C ||
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{ADR_I, 2'b00} == 32'h00D8003C ||
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{ADR_I, 2'b00} == 32'hFFFFFFFC;
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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ACK_O <= 1'b0;
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RTY_O <= 1'b0;
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end
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else begin
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if( cpu_space_cycle == 1'b0 &&
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accepted_addresses == 1'b1 &&
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CYC_I == 1'b1 && STB_I == 1'b1 && ACK_O == 1'b0) ACK_O <= 1'b1;
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else ACK_O <= 1'b0;
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if( cpu_space_cycle == 1'b1 &&
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ADR_I[31:5] == 27'b111_1111_1111_1111_1111_1111_1111 &&
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CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0)
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begin
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RTY_O <= 1'b1;
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end
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else begin
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RTY_O <= 1'b0;
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end
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end
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end
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endmodule
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