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alfik |
/*
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* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are
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* permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*! \file
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* \brief OCS copper implementation with WISHBONE master and slave interface.
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*/
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/*! \brief \copybrief ocs_copper.v
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List of copper registers:
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\verbatim
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Implemented:
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COPCON *02E W A( E ) Coprocessor control register (CDANG)
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COP1LCH + 080 W A( E ) Coprocessor first location register (high 3 bits, high 5 bits if ECS)
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COP1LCL + 082 W A Coprocessor first location register (low 15 bits)
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COP2LCH + 084 W A( E ) Coprocessor second location register (high 3 bits, high 5 bits if ECS)
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COP2LCL + 086 W A Coprocessor second location register (low 15 bits)
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COPJMP1 088 S A Coprocessor restart at first location
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COPJMP2 08A S A Coprocessor restart at second location
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Not implemented:
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COPINS 08C W A Coprocessor instruction fetch identify
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\endverbatim
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\note
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\li \c COPINS is not implemented.
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*/
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module ocs_copper(
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//% \name Clock and reset
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//% @{
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input CLK_I,
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input reset_n,
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//% @}
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//% \name WISHBONE master
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//% @{
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output reg CYC_O,
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output reg STB_O,
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output reg WE_O,
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output reg [31:2] ADR_O,
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output reg [3:0] SEL_O,
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output reg [31:0] master_DAT_O,
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input [31:0] master_DAT_I,
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input ACK_I,
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//% @}
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//% \name WISHBONE slave
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//% @{
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input CYC_I,
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input STB_I,
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input WE_I,
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input [8:2] ADR_I,
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input [3:0] SEL_I,
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input [31:0] slave_DAT_I,
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output reg ACK_O,
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//% @}
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//% \name Internal OCS ports
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//% @{
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input line_start,
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input [8:0] line_number,
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input [8:0] column_number,
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input [10:0] dma_con,
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input blitter_busy
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//% @}
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);
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reg [15:0] cop_con;
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reg [31:0] cop1_loc;
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reg [31:0] cop2_loc;
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reg [1:0] jump_strobe;
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reg [1:0] state;
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reg [31:0] pc;
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reg [47:0] ir;
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reg [1:0] avail;
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parameter [1:0]
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S_IDLE = 2'd0,
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S_LOAD = 2'd1,
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S_SAVE = 2'd2;
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// MOVE: >= 0x20($80-$FF) always, >= 0x10 && < 0x20 CDANG, < 0x10($00-$3E) never
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// WAIT: pos >= params; PAL max(226,312)
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// horiz [7:1] bits, DDF, 0x0-0xE2, resolution 4 lowres, 8 hires, horiz blanking 0x0F-0x35, lowres 0x04-0x47 not used
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// vert [7:0] bits,
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// SKIP: pos >= params then skip next instruction
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//
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// enable bits: if 0 -> always true, vert[7] not masked, always checked
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wire [31:0] move_address;
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assign move_address = { 8'd0, 12'hDFF, 3'b0, ir[40:32] };
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wire beam_compare;
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assign beam_compare =
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(line_number[7:0] & { 1'b1, ir[30:24] }) > (ir[47:40] & { 1'b1, ir[30:24] }) ||
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( (line_number[7:0] & { 1'b1, ir[30:24] }) == (ir[47:40] & { 1'b1, ir[30:24] }) &&
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(column_number[8:0] & { ir[23:17], 2'b0 }) >= ({ ir[39:33], 2'b0 } & { ir[23:17], 2'b0 })
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);
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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CYC_O <= 1'b0;
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STB_O <= 1'b0;
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WE_O <= 1'b0;
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ADR_O <= 30'd0;
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SEL_O <= 4'b0000;
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master_DAT_O <= 32'd0;
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ACK_O <= 1'b0;
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cop_con <= 16'd0;
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cop1_loc <= 32'd0;
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cop2_loc <= 32'd0;
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jump_strobe <= 2'b11;
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state <= S_IDLE;
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pc <= 32'd0;
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ir <= 48'd0;
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avail <= 2'd0;
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end
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else begin
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if(CYC_I == 1'b1 && STB_I == 1'b1 /*&& WE_I == 1'b1*/ && ACK_O == 1'b0) ACK_O <= 1'b1;
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else ACK_O <= 1'b0;
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// JMP1
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if( (CYC_I == 1'b1 && STB_I == 1'b1 /*&& WE_I == 1'b1*/ && { ADR_I, 2'b0 } == 9'h088 && SEL_O[3:2] != 2'b00 && ACK_O == 1'b0) ||
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(line_start == 1'b1 && line_number == 9'd0) ) //PAL:25, NTSC: 20
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begin
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jump_strobe <= 2'b01;
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end
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// JMP2
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else if(CYC_I == 1'b1 && STB_I == 1'b1 /*&& WE_I == 1'b1*/ && { ADR_I, 2'b0 } == 9'h088 && SEL_O[1:0] != 2'b00 && ACK_O == 1'b0) begin
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jump_strobe <= 2'b10;
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end
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else if(state == S_SAVE &&
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((cop_con[1] == 1'b1 && move_address[8:0] <= 9'h03E) || (cop_con[1] == 1'b0 && move_address[8:0] <= 9'h07E)))
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begin
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jump_strobe <= 2'b11;
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end
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// 02C: VHPOSW(not used), COPCON,
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// 080: COP1LCH, COP1LCL,
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// 084: COP2LCH, COP2LCL,
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// 088: COPJMP1, COPJMP2,
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if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && ACK_O == 1'b0) begin
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if({ ADR_I, 2'b0 } == 9'h02C && SEL_I[0] == 1'b1) cop_con[7:0] <= slave_DAT_I[7:0];
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if({ ADR_I, 2'b0 } == 9'h02C && SEL_I[1] == 1'b1) cop_con[15:8] <= slave_DAT_I[15:8];
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if({ ADR_I, 2'b0 } == 9'h02C && SEL_I[2] == 1'b1) ;
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if({ ADR_I, 2'b0 } == 9'h02C && SEL_I[3] == 1'b1) ;
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if({ ADR_I, 2'b0 } == 9'h080 && SEL_I[0] == 1'b1) cop1_loc[7:0] <= slave_DAT_I[7:0];
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if({ ADR_I, 2'b0 } == 9'h080 && SEL_I[1] == 1'b1) cop1_loc[15:8] <= slave_DAT_I[15:8];
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if({ ADR_I, 2'b0 } == 9'h080 && SEL_I[2] == 1'b1) cop1_loc[23:16] <= slave_DAT_I[23:16];
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if({ ADR_I, 2'b0 } == 9'h080 && SEL_I[3] == 1'b1) cop1_loc[31:24] <= slave_DAT_I[31:24];
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if({ ADR_I, 2'b0 } == 9'h084 && SEL_I[0] == 1'b1) cop2_loc[7:0] <= slave_DAT_I[7:0];
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if({ ADR_I, 2'b0 } == 9'h084 && SEL_I[1] == 1'b1) cop2_loc[15:8] <= slave_DAT_I[15:8];
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if({ ADR_I, 2'b0 } == 9'h084 && SEL_I[2] == 1'b1) cop2_loc[23:16] <= slave_DAT_I[23:16];
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if({ ADR_I, 2'b0 } == 9'h084 && SEL_I[3] == 1'b1) cop2_loc[31:24] <= slave_DAT_I[31:24];
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end
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else if(state == S_IDLE) begin
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// DMAEN, COPEN
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if(dma_con[9] == 1'b0 || dma_con[7] == 1'b0 ) begin
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jump_strobe <= 2'b11;
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end
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else if(jump_strobe == 2'b11) begin
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// no operation
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end
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else if(jump_strobe == 2'b01) begin
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jump_strobe <= 2'b00;
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pc <= cop1_loc;
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avail <= 2'd0;
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state <= S_LOAD;
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end
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else if(jump_strobe == 2'b10) begin
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jump_strobe <= 2'b00;
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pc <= cop2_loc;
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avail <= 2'd0;
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state <= S_LOAD;
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end
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else if(avail < 2'd2) begin
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state <= S_LOAD;
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end
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// MOVE
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else if(ir[32] == 1'b0) begin
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state <= S_SAVE;
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end
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// WAIT
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else if(ir[32] == 1'b1 && ir[16] == 1'b0 && (ir[31] == 1'b1 || blitter_busy == 1'b0) && beam_compare == 1'b1) begin
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avail <= avail - 2'd2;
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ir <= { ir[15:0], 32'd0 };
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state <= S_LOAD;
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end
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// SKIP
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else if(ir[32] == 1'b1 && ir[16] == 1'b1 && (ir[31] == 1'b1 || blitter_busy == 1'b0) && beam_compare == 1'b1) begin
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if(avail == 2'd2) pc <= pc + 32'd4;
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else pc <= pc + 32'd2;
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avail <= 2'd0;
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ir <= { ir[15:0], 32'd0 };
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state <= S_LOAD;
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end
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end
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else if(state == S_LOAD) begin
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if(ACK_I == 1'b1) begin
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CYC_O <= 1'b0;
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STB_O <= 1'b0;
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if(pc[1] == 1'b0 && avail == 2'd0) begin
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pc <= pc + 32'd4;
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avail <= avail + 2'd2;
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ir[47:16] <= master_DAT_I[31:0];
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end
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else if(pc[1] == 1'b0 && avail == 2'd1) begin
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pc <= pc + 32'd4;
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avail <= avail + 2'd2;
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ir[31:0] <= master_DAT_I[31:0];
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end
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else if(pc[1] == 1'b1 && avail == 2'd0) begin
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pc <= pc + 32'd2;
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avail <= avail + 2'd1;
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ir[47:32] <= master_DAT_I[15:0];
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end
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else if(pc[1] == 1'b1 && avail == 2'd1) begin
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pc <= pc + 32'd2;
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avail <= avail + 2'd1;
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ir[31:16] <= master_DAT_I[15:0];
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end
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state <= S_IDLE;
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end
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else begin
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CYC_O <= 1'b1;
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STB_O <= 1'b1;
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WE_O <= 1'b0;
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ADR_O <= pc[31:2];
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SEL_O <= 4'b1111;
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end
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end
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else if(state == S_SAVE) begin
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if(ACK_I == 1'b1 || (cop_con[1] == 1'b1 && move_address[8:0] <= 9'h03E) || (cop_con[1] == 1'b0 && move_address[8:0] <= 9'h07E))
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begin
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CYC_O <= 1'b0;
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STB_O <= 1'b0;
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avail <= avail - 2'd2;
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ir <= { ir[15:0], 32'd0 };
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state <= S_IDLE;
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end
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else begin
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CYC_O <= 1'b1;
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STB_O <= 1'b1;
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WE_O <= 1'b1;
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ADR_O <= move_address[31:2];
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if(move_address[1] == 1'b0) begin
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SEL_O <= 4'b1100;
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master_DAT_O <= { ir[31:16], 16'd0 };
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end
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else begin
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SEL_O <= 4'b0011;
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master_DAT_O <= { 16'd0, ir[31:16] };
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end
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end
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end
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end
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end
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endmodule
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