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alfik |
/*
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* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are
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* permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*! \file
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* \brief OCS serial port implementation with WISHBONE slave interface. [functionality not implemented]
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*/
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/*! \brief \copybrief ocs_serial.v
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List of serial registers:
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\verbatim
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Not implemented:
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SERDATR *018 R P Serial port data and status read read implemented here
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[DSKBYTR *01A R P Disk data byte and status read read implemented here]
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SERDAT *030 W P Serial port data and stop bits write
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SERPER *032 W P Serial port period and control
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\endverbatim
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*/
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module ocs_serial(
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//% \name Clock and reset
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//% @{
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input CLK_I,
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input reset_n,
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//% @}
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//% \name WISHBONE slave
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//% @{
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input CYC_I,
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input STB_I,
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input WE_I,
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input [8:2] ADR_I,
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input [3:0] SEL_I,
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input [31:0] DAT_I,
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output reg [31:0] DAT_O,
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output reg ACK_O,
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//% @}
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//% \name Not aligned register access on a 32-bit WISHBONE bus
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//% @{
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// DSKBYTR read implemented here
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output na_dskbytr_read,
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input [15:0] na_dskbytr
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//% @}
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);
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assign na_dskbytr_read =
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(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0 && { ADR_I, 2'b0 } == 9'h018 && SEL_I[1:0] != 2'b00 && ACK_O == 1'b0);
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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DAT_O <= 32'd0;
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ACK_O <= 1'b0;
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end
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else begin
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if(CYC_I == 1'b1 && STB_I == 1'b1 && ACK_O == 1'b0) ACK_O <= 1'b1;
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else ACK_O <= 1'b0;
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if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0) begin
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if({ ADR_I, 2'b0 } == 9'h018 && SEL_I[0] == 1'b1) DAT_O[7:0] <= na_dskbytr[7:0];
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if({ ADR_I, 2'b0 } == 9'h018 && SEL_I[1] == 1'b1) DAT_O[15:8] <= na_dskbytr[15:8];
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if({ ADR_I, 2'b0 } == 9'h018 && SEL_I[2] == 1'b1) DAT_O[23:16] <= 8'd0;
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if({ ADR_I, 2'b0 } == 9'h018 && SEL_I[3] == 1'b1) DAT_O[31:24] <= 8'd0;
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end
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end
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end
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endmodule
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