Subversion Repositories aoocs

/*

 * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without modification, are

 * permitted provided that the following conditions are met:

 *

 *  1. Redistributions of source code must retain the above copyright notice, this list of

 *     conditions and the following disclaimer.

 *

 *  2. Redistributions in binary form must reproduce the above copyright notice, this list

 *     of conditions and the following disclaimer in the documentation and/or other materials

 *     provided with the distribution.

 *

 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED

 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND

 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR

 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON

 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF

 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

/*! \file

 * \brief aoOCS top-level module for the Terasic DE2-70 board.

 */

/*! \brief \copybrief aoOCS.v

*/

module aoOCS(

        //% \name Clock and reset

    //% @{

        input           clk_50,

        input           reset_ext_n,

        //% @}

        //% \name IS61LPS51236A pipelined SSRAM hardware interface

    //% @{

        output [18:0]   ssram_address,

        output          ssram_oe_n,

        output          ssram_writeen_n,

        output [3:0]    ssram_byteen_n,

        inout [35:0]    ssram_data,

        output          ssram_clk,

        output          ssram_globalw_n,

        output          ssram_advance_n,

        output          ssram_adsp_n,

        output          ssram_adsc_n,

        output          ssram_ce1_n,

        output          ssram_ce2,

        output          ssram_ce3_n,

        //% @}

        //% \name SD bus 1-bit hardware interface

    //% @{

        output          sd_clk_o,

        inout           sd_cmd_io,

        inout           sd_dat_io,

        //% @}

        //% \name ADV7123 Video DAC hardware interface

    //% @{

        output [9:0]    vga_r,

        output [9:0]    vga_g,

        output [9:0]    vga_b,

        output          vga_blank_n,

        output          vga_sync_n,

        output          vga_clock,

        output          vga_hsync,

        output          vga_vsync,

        //% @}

        //% \name PS/2 keyboard hardware interface

    //% @{

        inout           ps2_kbclk,

    inout           ps2_kbdat,

        //% @}

        //% \name PS/2 mouse hardware interface

    //% @{

    inout           ps2_mouseclk,

    inout           ps2_mousedat,

    //% @}

    //% \name WM8731 audio codec hardware interface

    //% @{

    output          ac_sclk,

    inout           ac_sdat,

    output          ac_xclk,

    output          ac_bclk,

    output          ac_dat,

    output          ac_lr,

    //% @}

    //% \name DM9000A Ethernet hardware interface

    //% @{

    output          enet_clk_25,

    output          enet_reset_n,

    output          enet_cs_n,

    input           enet_irq,

    output          enet_ior_n,

    output          enet_iow_n,

    output          enet_cmd,

    inout [15:0]    enet_data,

    //% @}

    //% \name Switches and hex leds hardware interface from drv_debug

    //% @{

    // hex output

        output [7:0]    hex0,

        output [7:0]    hex1,

        output [7:0]    hex2,

        output [7:0]    hex3,

        output [7:0]    hex4,

        output [7:0]    hex5,

        output [7:0]    hex6,

        output [7:0]    hex7,

         // switches input

    input           debug_sw1_pc,

    input           debug_sw2_adr,

    input           debug_sw3_halt,

    //% @}

    //% \name Leds hardware interface for debug purposes

    //% @{

        output [7:0]    debug_sd,

        output [7:0]    debug_68k_state,

        output [7:0]    debug_floppy

        //% @}

);

/*

Amiga:

    00 0000 - 0F FFFF       1MB Chip RAM

    BF D000 - BF DF00       8520-B  (access at even-byte addresses only)

        -         -

    BF E001 - BF EF01       8520-A  (access at odd-byte addresses only)

    DF F000 - DF FFFF       Chip registers.

    C0 0000 - D7 FFFF       Internal expansion (slow) memory (on some systems).

    C0 0000 - DB FFFF       Slow memory check in ROM

    FC 0000 - FF FFFF       256K System ROM.

    0000 0000 0000 xxxx xxxx xxxx xxxx xxxx - chip ram

    0000 0000 1011 1111 11** **** **** **** - 8520-A/B

    0000 0000 1101 1111 1111 000x xxxx xxxx - chip registes

    0000 0000 1100 xxxx xxxx xxxx xxxx xxxx - slow memory

    0000 0000 1101 0xxx xxxx xxxx xxxx xxxx - slow memory

    0000 0000 1101 10xx xxxx xxxx xxxx xxxx - slow memory

    0000 0000 1111 11xx xxxx xxxx xxxx xxxx - system rom

    0000 0000 110* **** **** **** **** **** - chip registers and copy of chip registers

    0x00F00000 - no ROM at this address

bus_ssram

    SLAVE 2: ssram memory

        0x00000000 - 0x001FFFFF - 1MB Chip RAM and copies

            0x00000000 - 0x000FFFFF - 1MB Chip RAM          -> 0x00000000 - 0x000FFFFF in SSRAM

            0x00100000 - 0x001FFFFF - copy of Chip RAM

            AND mask:           0000 0000 0000 1111 1111 1111 1111 1111

            overlay OR mask:    0000 0000 0001 1100 0000 0000 0000 0000

        0x10100000 - 0x101BFFFF - 768Kb firmware RAM        -> 0x00100000 - 0x001BFFFF in SSRAM

            0x10180000 - 0x101B5FFF - video buffer          -> 0x00180000 - 0x001B5FFF in SSRAM, 216*4*256

            0x101B6000 - 0x101BFFFF - free                  -> 0x001B6000 - 0x001BFFFF in SSRAM

            AND mask:           0000 0000 0001 1111 1111 1111 1111 1111

        0x00FC0000 - 0x00FFFFFF - 256Kb ROM                 -> 0x001C0000 - 0x001FFFFF in SSRAM

            AND mask:           0000 0000 0001 1111 1111 1111 1111 1111

bus_sd

    SLAVE 1: control

        0x10001000 - 0x1000100F - 4 long words

    MASTER R1

control_osd

    SLAVE 3: on screen display

        0x10000000 - 0x10000FFF - 512x8

    MASTER R2

bus_terminator

    SLAVE 0:

        all unused addresses

ao68000

    MASTER R3

ocs_video

    SLAVE 4:

        chip registers

        08C-09B, 100-10B, 0E0-0F7, 120-1BF, 110-11B

    MASTER P1

ocs_control

    SLAVE 5:

        chip registers

        000-007 R, 09C-09F, 010-013 R, 01C-01F R, 028-02B

ocs_blitter

    SLAVE 6:

        chip registers

        040-059, 060-067, 070-075

    MASTER P2

ocs_copper

    SLAVE 7:

        chip registers

        02C-02F, 080-08B

    MASTER R4

cia_a

    SLAVE 8:

    0000_0000_101*_****_**10_****_****_****

cia_b

    SLAVE 9:

    0000_0000_101*_****_**01_****_****_****

ocs_serial

    SLAVE 10:

        chip registers

        018-01B R, 030-033

ocs_floppy

    SLAVE 11:

        chip registers

        020-027, 07C-07F

    SLAVE 12: floppy buffer

        0x10004000 - 0x100055FF, 11x512

    MASTER R5

ocs_input

    SLAVE 13:

        chip registers

        008-00F R, 014-017 R, 034-037

ocs_audio

    SLAVE 14:

        chip registers

        0A0-0AB, 0B0-0BB, 0C0-0CB, 0D0-0DB

    MASTER R6

*/

/***********************************************************************************************************************

 * System PLL

 **********************************************************************************************************************/

wire [5:0]  pll_clocks;

wire        clk_30 = pll_clocks[0];

wire        clk_12 = pll_clocks[1];

wire        clk_25 = pll_clocks[2];

wire        pll_locked;

altpll pll_inst(

        .inclk  ( {1'b0, clk_50} ),

        .clk    (pll_clocks),

        .locked (pll_locked)

);

defparam

    pll_inst.clk0_divide_by             = 5,

    pll_inst.clk0_duty_cycle            = 50,

    pll_inst.clk0_multiply_by           = 3,

    pll_inst.clk0_phase_shift           = "0",

    pll_inst.clk1_divide_by             = 25,

    pll_inst.clk1_duty_cycle            = 50,

    pll_inst.clk1_multiply_by           = 6,

    pll_inst.clk1_phase_shift           = "0",

    pll_inst.clk2_divide_by             = 2,

    pll_inst.clk2_duty_cycle            = 50,

    pll_inst.clk2_multiply_by           = 1,

    pll_inst.clk2_phase_shift           = "0",

    pll_inst.compensate_clock           = "CLK0",

    pll_inst.gate_lock_counter          = 1048575,

    pll_inst.gate_lock_signal           = "YES",

    pll_inst.inclk0_input_frequency     = 20000,

    pll_inst.intended_device_family     = "Cyclone II",

    pll_inst.invalid_lock_multiplier    = 5,

    pll_inst.lpm_hint                   = "CBX_MODULE_PREFIX=pll30",

    pll_inst.lpm_type                   = "altpll",

    pll_inst.operation_mode             = "NORMAL",

    pll_inst.valid_lock_multiplier      = 1;

wire reset_n            = pll_locked & reset_ext_n & ~reset_request;

wire management_reset_n = reset_n & ~management_mode;

/***********************************************************************************************************************

 * drv_audio

 **********************************************************************************************************************/

drv_audio drv_audio_inst(

    .clk_12 (clk_12),

    .reset_n(management_reset_n),

    // drv_audio interface

    .volume0(volume0), /*[6:0]*/

    .volume1(volume1), /*[6:0]*/

    .volume2(volume2), /*[6:0]*/

    .volume3(volume3), /*[6:0]*/

    .sample0(sample0), /*[7:0]*/

    .sample1(sample1), /*[7:0]*/

    .sample2(sample2), /*[7:0]*/

    .sample3(sample3), /*[7:0]*/

    // WM8731 audio codec hardware interface

    .ac_sclk(ac_sclk),

    .ac_sdat(ac_sdat),

    .ac_xclk(ac_xclk),

    .ac_bclk(ac_bclk),

    .ac_dat (ac_dat),

    .ac_lr  (ac_lr)

);

/***********************************************************************************************************************

 * drv_keyboard

 **********************************************************************************************************************/

wire        joystick_1_up;

wire        joystick_1_down;

wire        joystick_1_left;

wire        joystick_1_right;

wire        joystick_1_fire;

wire        request_osd;

wire        keyboard_event;

wire [7:0]  keyboard_scancode;

drv_keyboard drv_keyboard_inst (

    .clk_30             (clk_30),

    .reset_n            (reset_n),

    // On-Screen-Display management interface

    .request_osd        (request_osd),

    .enable_joystick_1  (on_screen_display | joystick_enable),

    // drv_keyboard interface

    .keyboard_ready     (keyboard_ready),

    .keyboard_event     (keyboard_event),

    .keyboard_scancode  (keyboard_scancode), /*[7:0]*/

    // joystick on port 1

    .joystick_1_up      (joystick_1_up),

    .joystick_1_down    (joystick_1_down),

    .joystick_1_left    (joystick_1_left),

    .joystick_1_right   (joystick_1_right),

    .joystick_1_fire    (joystick_1_fire),

    // PS/2 keyboard hardware interface

    .ps2_kbclk          (ps2_kbclk),

    .ps2_kbdat          (ps2_kbdat)

);

/***********************************************************************************************************************

 * drv_mouse

 **********************************************************************************************************************/

wire        mouse_moved;

wire [8:0]  mouse_y_move;

wire [8:0]  mouse_x_move;

wire        mouse_left_button;

wire        mouse_right_button;

wire        mouse_middle_button;

drv_mouse drv_mouse_inst(

    .clk_30                 (clk_30),

    .reset_n                (management_reset_n),

    // drv_keyboard interface

    .mouse_moved            (mouse_moved),

    .mouse_y_move           (mouse_y_move), /*[8:0]*/

    .mouse_x_move           (mouse_x_move), /*[8:0]*/

    .mouse_left_button      (mouse_left_button),

    .mouse_right_button     (mouse_right_button),

    .mouse_middle_button    (mouse_middle_button),

    // PS/2 mouse hardware interface

    .ps2_mouseclk           (ps2_mouseclk),

    .ps2_mousedat           (ps2_mousedat)

);

/***********************************************************************************************************************

 * bus_sd

 **********************************************************************************************************************/

bus_sd bus_sd_inst(

    .clk_30         (clk_30),

    .reset_n        (reset_n),

    // WISHBONE master

    .CYC_O          (masterR1_cyc_o),

    .DAT_O          (masterR1_dat_o),

    .STB_O          (masterR1_stb_o),

    .WE_O           (masterR1_we_o),

    .ADR_O          (masterR1_adr_o),

    .SEL_O          (masterR1_sel_o),

    .DAT_I          (slave_dat_o),

    .ACK_I          (masterR1_ack_i),

    .ERR_I          (masterR1_err_i),

    .RTY_I          (masterR1_rty_i),

    // TAG_TYPE: TGC_O

    .SGL_O          (),

    .BLK_O          (),

    .RMW_O          (),

    // TAG_TYPE: TGA_O

    .CTI_O          (),

    .BTE_O          (),

    // WISHBONE slave

    .slave_DAT_O    (slave1_dat_o),

    .slave_DAT_I    (master_dat_o),

    .ACK_O          (slave1_ack_o),

    .ERR_O          (slave1_err_o),

    .RTY_O          (slave1_rty_o),

    .CYC_I          (slave1_cyc_i),

    .ADR_I          (master_adr_o[3:2]), /*[3:2]*/

    .STB_I          (slave1_stb_i),

    .WE_I           (master_we_o),

    .SEL_I          (master_sel_o),

    // SD bus 1-bit hardware interface

    .sd_clk_o       (sd_clk_o),

    .sd_cmd_io      (sd_cmd_io),

    .sd_dat_io      (sd_dat_io),

    // Debug signals

    .debug_sd       (debug_sd)

);

/***********************************************************************************************************************

 * bus_ssram

 **********************************************************************************************************************/

wire [35:0] burst_read_data;

bus_ssram bus_ssram_inst(

    .clk_30                     (clk_30),

    .reset_n                    (reset_n),

    // WISHBONE slave

    .ADR_I                      (master_adr_o[20:2]), /*[20:2]*/

    .CYC_I                      (slave2_cyc_i),

    .WE_I                       (master_we_o),

    .SEL_I                      (master_sel_o),

    .STB_I                      (slave2_stb_i),

    .DAT_I                      (master_dat_o),

    .DAT_O                      (slave2_dat_o),

    .ACK_O                      (slave2_ack_o),

    // Direct drv_ssram read/write burst DMA for ocs_video and drv_vga 

    // drv_vga read burst

    .burst_read_vga_request     (burst_read_vga_request),

    .burst_read_vga_address     (burst_read_vga_address),

    .burst_read_vga_ready       (burst_read_vga_ready),

    // ocs_video bitplain read burst

    .burst_read_video_request   (burst_read_video_request),

    .burst_read_video_address   (burst_read_video_address),

    .burst_read_video_ready     (burst_read_video_ready),

    // common read burst data signal

    .burst_read_data            (burst_read_data),

    // ocs_video video output write burst

    .burst_write_request        (burst_write_request),

    .burst_write_address        (burst_write_address),

    .burst_write_ready          (burst_write_ready),

    .burst_write_data           (burst_write_data),

    // IS61LPS51236A pipelined SSRAM hardware interface

    .ssram_address              (ssram_address),

    .ssram_oe_n                 (ssram_oe_n),

    .ssram_writeen_n            (ssram_writeen_n),

    .ssram_byteen_n             (ssram_byteen_n),

    .ssram_adsp_n               (ssram_adsp_n),

    .ssram_clk                  (ssram_clk),

    .ssram_globalw_n            (ssram_globalw_n),

    .ssram_advance_n            (ssram_advance_n),

    .ssram_adsc_n               (ssram_adsc_n),

    .ssram_ce1_n                (ssram_ce1_n),

    .ssram_ce2                  (ssram_ce2),

    .ssram_ce3_n                (ssram_ce3_n),

    .ssram_data                 (ssram_data)

);

/***********************************************************************************************************************

 * drv_vga

 **********************************************************************************************************************/

wire        burst_read_vga_request;

wire [31:2] burst_read_vga_address;

wire        burst_read_vga_ready;

wire [4:0]  osd_line;

wire [4:0]  osd_column;

wire        display_valid;

drv_vga drv_vga_inst(

    .clk_30             (clk_30),

    .reset_n            (reset_n),

    // On-Screen-Display management interface

    .management_mode    (management_mode),

    .on_screen_display  (on_screen_display),

    .osd_line           (osd_line),

    .osd_column         (osd_column),

    .character          (character),

    // Control signal for VGA capture

    .display_valid(display_valid),

    // Direct drv_ssram burst read DMA video interface

    .burst_read_request (burst_read_vga_request),

    .burst_read_address (burst_read_vga_address),   /*[18:0]*/

    .burst_read_ready   (burst_read_vga_ready),

    .burst_read_data    (burst_read_data),          /*[35:0]*/

    // ADV7123 Video DAC hardware interface

    .vga_r              (vga_r),        /*[9:0]*/

    .vga_g              (vga_g),        /*[9:0]*/

    .vga_b              (vga_b),        /*[9:0]*/

    .vga_blank_n        (vga_blank_n),

    .vga_sync_n         (vga_sync_n),

    .vga_clock          (vga_clock),

    .vga_hsync          (vga_hsync),

    .vga_vsync          (vga_vsync)

);

/***********************************************************************************************************************

 * drv_eth_vga_capture

 **********************************************************************************************************************/

drv_eth_vga_capture drv_eth_vga_capture_inst(

    .clk_30         (clk_30),

    .clk_25         (clk_25),

    .reset_n        (reset_n),

    // Captured VGA output signals

    .display_valid  (display_valid),

    .vga_r          (vga_r),

    .vga_g          (vga_g),

    .vga_b          (vga_b),

    // DM9000A Ethernet hardware interface

    .enet_clk_25(enet_clk_25),

    .enet_reset_n(enet_reset_n),

    .enet_cs_n(enet_cs_n),

    .enet_irq(enet_irq),

    .enet_ior_n(enet_ior_n),

    .enet_iow_n(enet_iow_n),

    .enet_cmd(enet_cmd),

    .enet_data(enet_data) /*[15:0]*/

);

/***********************************************************************************************************************

 * drv_debug

 **********************************************************************************************************************/

drv_debug drv_debug_inst(

    .CLK_I          (clk_30),

    .reset_n        (reset_n),

    // Internal debug signals

    .master_adr_o   (master_adr_o),

    .debug_pc       (debug_pc),

    .debug_syscon   (debug_syscon),

    .debug_track    (debug_track),

    // Switches and hex leds hardware interface

    // hex output

    .hex0           (hex0),

    .hex1           (hex1),

    .hex2           (hex2),

    .hex3           (hex3),

    .hex4           (hex4),

    .hex5           (hex5),

    .hex6           (hex6),

    .hex7           (hex7),

    // switches input

    .debug_sw_pc    (debug_sw1_pc),

    .debug_sw_adr   (debug_sw2_adr)

);

/***********************************************************************************************************************

 * control_osd

 **********************************************************************************************************************/

wire        management_mode;

wire        on_screen_display;

wire [7:0]  character;

wire        floppy_inserted;

wire [31:0] floppy_sector;

wire        floppy_write_enabled;

wire        joystick_enable;

wire        reset_request;

control_osd control_osd_inst(

    .CLK_I                  (clk_30),

    .reset_n                (reset_n),

    .reset_request          (reset_request),

    .management_mode        (management_mode),

    // WISHBONE master

    .CYC_O                  (masterR2_cyc_o),

    .STB_O                  (masterR2_stb_o),

    .WE_O                   (masterR2_we_o),

    .ADR_O                  (masterR2_adr_o), /*[31:2]*/

    .SEL_O                  (masterR2_sel_o),

    .master_DAT_O           (masterR2_dat_o),

    .master_DAT_I           (slave_dat_o),

    .ACK_I                  (masterR2_ack_i),

    // WISHBONE slave

    .ADR_I                  (master_adr_o),

    .CYC_I                  (slave3_cyc_i),

    .WE_I                   (master_we_o),

    .STB_I                  (slave3_stb_i),

    .SEL_I                  (master_sel_o),

    .slave_DAT_I            (master_dat_o),

    .slave_DAT_O            (slave3_dat_o),

    .ACK_O                  (slave3_ack_o),

    .RTY_O                  (slave3_rty_o),

    .ERR_O                  (slave3_err_o),

    // On-Screen-Display management interface

    .request_osd            (request_osd),

    .on_screen_display      (on_screen_display),

    .osd_line               (osd_line),

    .osd_column             (osd_column),

    .character              (character),

    .joystick_enable        (joystick_enable),

    .keyboard_select        (joystick_1_fire),

    .keyboard_up            (joystick_1_up),

    .keyboard_down          (joystick_1_down),

    // On-Screen-Display floppy management interface

    .floppy_inserted        (floppy_inserted),

    .floppy_sector          (floppy_sector),

    .floppy_write_enabled   (floppy_write_enabled),

    .floppy_error           (floppy_error)

);

/***********************************************************************************************************************

 * bus_terminator

 **********************************************************************************************************************/

bus_terminator bus_terminator_inst(

    .CLK_I(clk_30),

    .reset_n(reset_n),

    // WISHBONE slave

    .ADR_I                  (master_adr_o),

    .CYC_I                  (slave0_cyc_i),

    .WE_I                   (master_we_o),

    .STB_I                  (slave0_stb_i),

    .SEL_I                  (master_sel_o),

    .slave_DAT_I            (master_dat_o),

    .slave_DAT_O            (slave0_dat_o),

    .ACK_O                  (slave0_ack_o),

    .RTY_O                  (slave0_rty_o),

    .ERR_O                  (slave0_err_o),

    // ao68000 interrupt cycle indicator

    .cpu_space_cycle( masterR3_cyc_o == 1'b1 && masterR3_stb_o == 1'b1 && masterR3_we_o == 1'b0 && fc == 3'd7 )

);

/***********************************************************************************************************************

 * ao68000

 **********************************************************************************************************************/

wire [31:0] debug_pc;

wire [2:0]  fc;

ao68000 ao68000_inst(

        .CLK_I              (clk_30),

        .reset_n            (management_reset_n),

    // WISHBONE master

        .CYC_O              (masterR3_cyc_o),

        .ADR_O              (masterR3_adr_o),

        .DAT_O              (masterR3_dat_o),

        .DAT_I              (slave_dat_o),

        .SEL_O              (masterR3_sel_o),

        .STB_O              (masterR3_stb_o),

        .WE_O               (masterR3_we_o),

        .ACK_I              (masterR3_ack_i),

        .ERR_I              (masterR3_err_i),

        .RTY_I              (masterR3_rty_i),

        // TAG_TYPE: TGC_O

        .SGL_O              (),

        .BLK_O              (),

        .RMW_O              (),

        // TAG_TYPE: TGA_O

        .CTI_O              (),

        .BTE_O              (),

        // TAG_TYPE: TGC_O

        .fc_o               (fc),

        //****************** OTHER

        /* interrupt acknowlege:

         * ACK_I: interrupt vector on DAT_I[7:0]

         * ERR_I: spurious interrupt

         * RTY_I: autovector

         */

        .ipl_i              (interrupt),

        .reset_o            (),

        .blocked_o          (),

        .debug_pc           (debug_pc),

        .debug_68k_state    (debug_68k_state)

);

/***********************************************************************************************************************

 * ocs_video

 **********************************************************************************************************************/

wire        burst_read_video_request;

wire [31:2] burst_read_video_address;

wire        burst_read_video_ready;

wire        burst_write_request;

wire [31:2] burst_write_address;

wire [35:0] burst_write_data;

wire        burst_write_ready;

wire        na_int_ena_write;

wire [15:0] na_int_ena;

wire [1:0]  na_int_ena_sel;

wire        na_dma_con_write;

wire [15:0] na_dma_con;

wire [1:0]  na_dma_con_sel;

wire [15:0] na_clx_dat;