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[/] [aoocs/] [trunk/] [rtl/] [terasic_de2_70/] [bus_ssram.v] - Blame information for rev 2

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/*
 * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification, are
 * permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright notice, this list of
 *     conditions and the following disclaimer.
 *
 *  2. Redistributions in binary form must reproduce the above copyright notice, this list
 *     of conditions and the following disclaimer in the documentation and/or other materials
 *     provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/*! \file
 * \brief IS61LPS51236A pipelined SSRAM driver with WISHBONE slave interface.
 */
 
/*! \brief \copybrief bus_ssram.v
*/
module bus_ssram(
        //% \name Clock and reset
    //% @{
        input               clk_30,
        input               reset_n,
        //% @}
 
        //% \name WISHBONE slave
    //% @{
        input [20:2]        ADR_I,
        input               CYC_I,
        input               WE_I,
        input [3:0]         SEL_I,
        input               STB_I,
        input [31:0]        DAT_I,
        output reg [31:0]   DAT_O,
        output reg          ACK_O,
        //% @}
 
        //% \name Direct drv_ssram read/write burst DMA for ocs_video and drv_vga 
    //% @{
    // drv_vga read burst
    input               burst_read_vga_request,
    input [31:2]        burst_read_vga_address,
    output              burst_read_vga_ready,
    // ocs_video bitplain read burst
        input               burst_read_video_request,
        input [31:2]        burst_read_video_address,
        output              burst_read_video_ready,
        // common read burst data signal
        output reg [35:0]   burst_read_data,
        //% @}
 
        // ocs_video video output write burst
        input               burst_write_request,
        input [31:2]        burst_write_address,
        output reg          burst_write_ready,
        input [35:0]        burst_write_data,
        //% @}
 
        //% \name IS61LPS51236A pipelined SSRAM hardware interface
    //% @{
        output reg [18:0]   ssram_address,
        output reg          ssram_oe_n,
        output reg          ssram_writeen_n,
        output reg [3:0]    ssram_byteen_n,
        output              ssram_adsp_n,
        output              ssram_clk,
        output              ssram_globalw_n,
        output reg          ssram_advance_n,
        output reg          ssram_adsc_n,
        output              ssram_ce1_n,
        output              ssram_ce2,
        output              ssram_ce3_n,
        inout [35:0]        ssram_data
        //% @}
);
 
assign ssram_clk = clk_30;
assign ssram_globalw_n = 1'b1;
assign ssram_adsp_n = 1'b1;
assign ssram_ce1_n = 1'b0;
assign ssram_ce2 = 1'b1;
assign ssram_ce3_n = 1'b0;
 
reg ssram_data_oe;
reg [35:0] ssram_data_reg;
assign ssram_data = (ssram_data_oe == 1'b1) ? ssram_data_reg : 36'bZ;
 
reg [18:0] burst_address;
 
reg burst_read_select;
reg burst_read_ready;
 
assign burst_read_vga_ready = (burst_read_select == 1'b0)? burst_read_ready : 1'b0;
assign burst_read_video_ready = (burst_read_select == 1'b0)? 1'b0 : burst_read_ready;
 
reg [3:2] burst_read_low_address;
reg burst_read_one_loop;
wire burst_read_request;
assign burst_read_request = (burst_read_select == 1'b0)? burst_read_vga_request : burst_read_video_request;
 
reg [3:0] state;
parameter [3:0]
        S_IDLE      = 4'd0,
        S_VW0       = 4'd1,
        S_VW1       = 4'd2,
        S_VW2       = 4'd3,
        S_VW3       = 4'd4,
        S_VW4       = 4'd5,
        S_VR1       = 4'd6,
        S_VR2       = 4'd7,
        S_VR3       = 4'd8,
        S_VR4       = 4'd9,
        S_R1        = 4'd10,
        S_R2        = 4'd11,
        S_R3        = 4'd12,
        S_PRE_IDLE  = 4'd13;
 
always @(posedge clk_30 or negedge reset_n) begin
        if(reset_n == 1'b0) begin
                ssram_address <= 19'd0;
                ssram_adsc_n <= 1'b1;
                ssram_advance_n <= 1'b1;
                ssram_data_reg <= 36'd0;
                ssram_data_oe <= 1'b0;
                ssram_oe_n <= 1'b1;
                ssram_writeen_n <= 1'b1;
                ssram_byteen_n <= 4'b1111;
 
                burst_address <= 19'd0;
 
                burst_read_data <= 36'd0;
        burst_read_ready <= 1'b0;
        burst_read_select <= 1'b0;
                burst_read_low_address <= 2'd0;
                burst_read_one_loop <= 1'b0;
 
                burst_write_ready <= 1'b0;
 
                ACK_O <= 1'b0;
                DAT_O <= 32'd0;
 
                state <= S_IDLE;
        end
        else if(state == S_IDLE) begin
        ACK_O <= 1'b0;
 
        if(burst_read_vga_request == 1'b1 || burst_read_video_request == 1'b1) begin
            // address and byte enables output
            if(burst_read_vga_request == 1'b1)          ssram_address <= { burst_read_vga_address[20:4], 2'b0 };
            else if(burst_read_video_request == 1'b1)   ssram_address <= { burst_read_video_address[20:4], 2'b0 };
            ssram_adsc_n <= 1'b0;
            ssram_advance_n <= 1'b1;
            ssram_data_reg <= 32'd0;
            ssram_data_oe <= 1'b0;
            ssram_oe_n <= 1'b1;
            ssram_writeen_n <= 1'b1;
            ssram_byteen_n <= 4'b0000;
 
            if(burst_read_vga_request == 1'b1) begin
                burst_address <= { burst_read_vga_address[20:4], 2'b0 } + 19'd4;
                burst_read_low_address <= burst_read_vga_address[3:2];
                burst_read_select <= 1'b0;
            end
            else if(burst_read_video_request == 1'b1) begin
                burst_address <= { burst_read_video_address[20:4], 2'b0 } + 19'd4;
                burst_read_low_address <= burst_read_video_address[3:2];
                burst_read_select <= 1'b1;
            end
            burst_read_one_loop <= 1'b0;
            state <= S_VR1;
        end
        else if(burst_write_request == 1'b1) begin
            burst_write_ready <= 1'b1;
            burst_address <= burst_write_address[20:2];
            state <= S_VW0;
        end
        else if(ACK_O == 1'b0 && CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0) begin
            // address and byte enables output
            ssram_address <= ADR_I[20:2];
            ssram_adsc_n <= 1'b0;
            ssram_advance_n <= 1'b1;
            ssram_data_reg <= 32'd0;
            ssram_data_oe <= 1'b0;
            ssram_oe_n <= 1'b1;
            ssram_writeen_n <= 1'b1;
            ssram_byteen_n <= 4'b0000;
 
            state <= S_R1;
        end
        else if(ACK_O == 1'b0 && CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1) begin
            // address, byte enables and write enables output
            ssram_address <= ADR_I[20:2];
            ssram_adsc_n <= 1'b0;
            ssram_advance_n <= 1'b1;
            ssram_data_reg <= { 4'b0, DAT_I };
            ssram_data_oe <= 1'b1;
            ssram_oe_n <= 1'b1;
            ssram_writeen_n <= 1'b0;
            ssram_byteen_n <= ~SEL_I;
 
            ACK_O <= 1'b1;
            state <= S_PRE_IDLE;
        end
    end
    else if(state == S_VW0) begin
                state <= S_VW1;
        end
        else if(state == S_VW1) begin
        if(burst_write_request == 1'b0) begin
            burst_write_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            ssram_data_oe <= 1'b0;
            ssram_writeen_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            // address, byte enables and write enables output
            ssram_address <= burst_address;
            ssram_adsc_n <= 1'b0;
            ssram_advance_n <= 1'b1;
            ssram_data_reg <= burst_write_data;
            ssram_data_oe <= 1'b1;
            ssram_oe_n <= 1'b1;
            ssram_writeen_n <= 1'b0;
            ssram_byteen_n <= 4'b0000;
 
            burst_address <= burst_address + 19'd4;
            state <= S_VW2;
        end
    end
    else if(state == S_VW2) begin
        if(burst_write_request == 1'b0) begin
            burst_write_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            ssram_data_oe <= 1'b0;
            ssram_writeen_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b0;
            ssram_data_reg <= burst_write_data;
 
            state <= S_VW3;
        end
    end
    else if(state == S_VW3) begin
        if(burst_write_request == 1'b0) begin
            burst_write_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            ssram_data_oe <= 1'b0;
            ssram_writeen_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            ssram_data_reg <= burst_write_data;
 
            state <= S_VW4;
        end
    end
    else if(state == S_VW4) begin
        if(burst_write_request == 1'b0) begin
            burst_write_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            ssram_data_oe <= 1'b0;
            ssram_writeen_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            ssram_data_reg <= burst_write_data;
 
            state <= S_VW1;
        end
    end
    else if(state == S_VR1) begin
        if(burst_read_request == 1'b0) begin
            burst_read_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            if(burst_read_low_address[3:2] == 2'b10 && burst_read_one_loop == 1'b1) burst_read_ready <= 1'b1;
 
            // address and byte enables latched
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b0;
 
            burst_read_data <= ssram_data;
            state <= S_VR2;
        end
    end
    else if(state == S_VR2) begin
        if(burst_read_request == 1'b0) begin
            burst_read_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            if(burst_read_low_address[3:2] == 2'b11 && burst_read_one_loop == 1'b1) burst_read_ready <= 1'b1;
 
            // output enable output
            ssram_oe_n <= 1'b0;
 
            burst_read_data <= ssram_data;
            state <= S_VR3;
        end
    end
    else if(state == S_VR3) begin
        if(burst_read_request == 1'b0) begin
            burst_read_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            if(burst_read_low_address[3:2] == 2'b00) burst_read_ready <= 1'b1;
 
            burst_read_data <= ssram_data;
            state <= S_VR4;
        end
    end
    else if(state == S_VR4) begin
        if(burst_read_request == 1'b0) begin
            burst_read_ready <= 1'b0;
            ssram_adsc_n <= 1'b1;
            ssram_advance_n <= 1'b1;
            state <= S_PRE_IDLE;
        end
        else begin
            if(burst_read_low_address[3:2] == 2'b01) burst_read_ready <= 1'b1;
            burst_read_one_loop <= 1'b1;
 
            ssram_address <= burst_address;
            ssram_adsc_n <= 1'b0;
            ssram_advance_n <= 1'b1;
 
            burst_read_data <= ssram_data;
            burst_address <= burst_address + 19'd4;
            state <= S_VR1;
        end
    end
    else if(state == S_R1) begin
        // address and byte enables latched
        ssram_adsc_n <= 1'b1;
        ssram_advance_n <= 1'b1;
 
        state <= S_R2;
    end
    else if(state == S_R2) begin
        // output enable output
        ssram_oe_n <= 1'b0;
 
        state <= S_R3;
    end
    else if(state == S_R3) begin
        DAT_O <= ssram_data[31:0];
        ACK_O <= 1'b1;
 
        ssram_address <= 19'd0;
        ssram_adsc_n <= 1'b1;
        ssram_advance_n <= 1'b1;
        ssram_data_reg <= 36'd0;
        ssram_data_oe <= 1'b0;
        ssram_oe_n <= 1'b1;
        ssram_writeen_n <= 1'b1;
        ssram_byteen_n <= 4'b1111;
 
        state <= S_IDLE;
    end
    else if(state == S_PRE_IDLE) begin
        ACK_O <= 1'b0;
 
        ssram_address <= 19'd0;
        ssram_adsc_n <= 1'b1;
        ssram_advance_n <= 1'b1;
        ssram_data_reg <= 36'd0;
        ssram_data_oe <= 1'b0;
        ssram_oe_n <= 1'b1;
        ssram_writeen_n <= 1'b1;
        ssram_byteen_n <= 4'b1111;
 
        state <= S_IDLE;
    end
end
 
endmodule

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[/] [aoocs/] [trunk/] [rtl/] [terasic_de2_70/] [bus_ssram.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.`
3			`*`
4			`* Redistribution and use in source and binary forms, with or without modification, are`
5			`* permitted provided that the following conditions are met:`
6			`*`
7			`* 1. Redistributions of source code must retain the above copyright notice, this list of`
8			`* conditions and the following disclaimer.`
9			`*`
10			`* 2. Redistributions in binary form must reproduce the above copyright notice, this list`
11			`* of conditions and the following disclaimer in the documentation and/or other materials`
12			`* provided with the distribution.`
13			`*`
14			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
15			`* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND`
16			`* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR`
17			`* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR`
18			`* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR`
19			`* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON`
20			`* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING`
21			`* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
22			`* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
23			`*/`
24
25			`/*! \file`
26			`* \brief IS61LPS51236A pipelined SSRAM driver with WISHBONE slave interface.`
27			`*/`
28
29			`/*! \brief \copybrief bus_ssram.v`
30			`*/`
31			`module bus_ssram(`
32			`//% \name Clock and reset`
33			`//% @{`
34			`input clk_30,`
35			`input reset_n,`
36			`//% @}`
37
38			`//% \name WISHBONE slave`
39			`//% @{`
40			`input [20:2] ADR_I,`
41			`input CYC_I,`
42			`input WE_I,`
43			`input [3:0] SEL_I,`
44			`input STB_I,`
45			`input [31:0] DAT_I,`
46			`output reg [31:0] DAT_O,`
47			`output reg ACK_O,`
48			`//% @}`
49
50			`//% \name Direct drv_ssram read/write burst DMA for ocs_video and drv_vga`
51			`//% @{`
52			`// drv_vga read burst`
53			`input burst_read_vga_request,`
54			`input [31:2] burst_read_vga_address,`
55			`output burst_read_vga_ready,`
56			`// ocs_video bitplain read burst`
57			`input burst_read_video_request,`
58			`input [31:2] burst_read_video_address,`
59			`output burst_read_video_ready,`
60			`// common read burst data signal`
61			`output reg [35:0] burst_read_data,`
62			`//% @}`
63
64			`// ocs_video video output write burst`
65			`input burst_write_request,`
66			`input [31:2] burst_write_address,`
67			`output reg burst_write_ready,`
68			`input [35:0] burst_write_data,`
69			`//% @}`
70
71			`//% \name IS61LPS51236A pipelined SSRAM hardware interface`
72			`//% @{`
73			`output reg [18:0] ssram_address,`
74			`output reg ssram_oe_n,`
75			`output reg ssram_writeen_n,`
76			`output reg [3:0] ssram_byteen_n,`
77			`output ssram_adsp_n,`
78			`output ssram_clk,`
79			`output ssram_globalw_n,`
80			`output reg ssram_advance_n,`
81			`output reg ssram_adsc_n,`
82			`output ssram_ce1_n,`
83			`output ssram_ce2,`
84			`output ssram_ce3_n,`
85			`inout [35:0] ssram_data`
86			`//% @}`
87			`);`
88
89			`assign ssram_clk = clk_30;`
90			`assign ssram_globalw_n = 1'b1;`
91			`assign ssram_adsp_n = 1'b1;`
92			`assign ssram_ce1_n = 1'b0;`
93			`assign ssram_ce2 = 1'b1;`
94			`assign ssram_ce3_n = 1'b0;`
95
96			`reg ssram_data_oe;`
97			`reg [35:0] ssram_data_reg;`
98			`assign ssram_data = (ssram_data_oe == 1'b1) ? ssram_data_reg : 36'bZ;`
99
100			`reg [18:0] burst_address;`
101
102			`reg burst_read_select;`
103			`reg burst_read_ready;`
104
105			`assign burst_read_vga_ready = (burst_read_select == 1'b0)? burst_read_ready : 1'b0;`
106			`assign burst_read_video_ready = (burst_read_select == 1'b0)? 1'b0 : burst_read_ready;`
107
108			`reg [3:2] burst_read_low_address;`
109			`reg burst_read_one_loop;`
110			`wire burst_read_request;`
111			`assign burst_read_request = (burst_read_select == 1'b0)? burst_read_vga_request : burst_read_video_request;`
112
113			`reg [3:0] state;`
114			`parameter [3:0]`
115			`S_IDLE = 4'd0,`
116			`S_VW0 = 4'd1,`
117			`S_VW1 = 4'd2,`
118			`S_VW2 = 4'd3,`
119			`S_VW3 = 4'd4,`
120			`S_VW4 = 4'd5,`
121			`S_VR1 = 4'd6,`
122			`S_VR2 = 4'd7,`
123			`S_VR3 = 4'd8,`
124			`S_VR4 = 4'd9,`
125			`S_R1 = 4'd10,`
126			`S_R2 = 4'd11,`
127			`S_R3 = 4'd12,`
128			`S_PRE_IDLE = 4'd13;`
129
130			`always @(posedge clk_30 or negedge reset_n) begin`
131			`if(reset_n == 1'b0) begin`
132			`ssram_address <= 19'd0;`
133			`ssram_adsc_n <= 1'b1;`
134			`ssram_advance_n <= 1'b1;`
135			`ssram_data_reg <= 36'd0;`
136			`ssram_data_oe <= 1'b0;`
137			`ssram_oe_n <= 1'b1;`
138			`ssram_writeen_n <= 1'b1;`
139			`ssram_byteen_n <= 4'b1111;`
140
141			`burst_address <= 19'd0;`
142
143			`burst_read_data <= 36'd0;`
144			`burst_read_ready <= 1'b0;`
145			`burst_read_select <= 1'b0;`
146			`burst_read_low_address <= 2'd0;`
147			`burst_read_one_loop <= 1'b0;`
148
149			`burst_write_ready <= 1'b0;`
150
151			`ACK_O <= 1'b0;`
152			`DAT_O <= 32'd0;`
153
154			`state <= S_IDLE;`
155			`end`
156			`else if(state == S_IDLE) begin`
157			`ACK_O <= 1'b0;`
158
159			`if(burst_read_vga_request == 1'b1 \|\| burst_read_video_request == 1'b1) begin`
160			`// address and byte enables output`
161			`if(burst_read_vga_request == 1'b1) ssram_address <= { burst_read_vga_address[20:4], 2'b0 };`
162			`else if(burst_read_video_request == 1'b1) ssram_address <= { burst_read_video_address[20:4], 2'b0 };`
163			`ssram_adsc_n <= 1'b0;`
164			`ssram_advance_n <= 1'b1;`
165			`ssram_data_reg <= 32'd0;`
166			`ssram_data_oe <= 1'b0;`
167			`ssram_oe_n <= 1'b1;`
168			`ssram_writeen_n <= 1'b1;`
169			`ssram_byteen_n <= 4'b0000;`
170
171			`if(burst_read_vga_request == 1'b1) begin`
172			`burst_address <= { burst_read_vga_address[20:4], 2'b0 } + 19'd4;`
173			`burst_read_low_address <= burst_read_vga_address[3:2];`
174			`burst_read_select <= 1'b0;`
175			`end`
176			`else if(burst_read_video_request == 1'b1) begin`
177			`burst_address <= { burst_read_video_address[20:4], 2'b0 } + 19'd4;`
178			`burst_read_low_address <= burst_read_video_address[3:2];`
179			`burst_read_select <= 1'b1;`
180			`end`
181			`burst_read_one_loop <= 1'b0;`
182			`state <= S_VR1;`
183			`end`
184			`else if(burst_write_request == 1'b1) begin`
185			`burst_write_ready <= 1'b1;`
186			`burst_address <= burst_write_address[20:2];`
187			`state <= S_VW0;`
188			`end`
189			`else if(ACK_O == 1'b0 && CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0) begin`
190			`// address and byte enables output`
191			`ssram_address <= ADR_I[20:2];`
192			`ssram_adsc_n <= 1'b0;`
193			`ssram_advance_n <= 1'b1;`
194			`ssram_data_reg <= 32'd0;`
195			`ssram_data_oe <= 1'b0;`
196			`ssram_oe_n <= 1'b1;`
197			`ssram_writeen_n <= 1'b1;`
198			`ssram_byteen_n <= 4'b0000;`
199
200			`state <= S_R1;`
201			`end`
202			`else if(ACK_O == 1'b0 && CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1) begin`
203			`// address, byte enables and write enables output`
204			`ssram_address <= ADR_I[20:2];`
205			`ssram_adsc_n <= 1'b0;`
206			`ssram_advance_n <= 1'b1;`
207			`ssram_data_reg <= { 4'b0, DAT_I };`
208			`ssram_data_oe <= 1'b1;`
209			`ssram_oe_n <= 1'b1;`
210			`ssram_writeen_n <= 1'b0;`
211			`ssram_byteen_n <= ~SEL_I;`
212
213			`ACK_O <= 1'b1;`
214			`state <= S_PRE_IDLE;`
215			`end`
216			`end`
217			`else if(state == S_VW0) begin`
218			`state <= S_VW1;`
219			`end`
220			`else if(state == S_VW1) begin`
221			`if(burst_write_request == 1'b0) begin`
222			`burst_write_ready <= 1'b0;`
223			`ssram_adsc_n <= 1'b1;`
224			`ssram_advance_n <= 1'b1;`
225			`ssram_data_oe <= 1'b0;`
226			`ssram_writeen_n <= 1'b1;`
227			`state <= S_PRE_IDLE;`
228			`end`
229			`else begin`
230			`// address, byte enables and write enables output`
231			`ssram_address <= burst_address;`
232			`ssram_adsc_n <= 1'b0;`
233			`ssram_advance_n <= 1'b1;`
234			`ssram_data_reg <= burst_write_data;`
235			`ssram_data_oe <= 1'b1;`
236			`ssram_oe_n <= 1'b1;`
237			`ssram_writeen_n <= 1'b0;`
238			`ssram_byteen_n <= 4'b0000;`
239
240			`burst_address <= burst_address + 19'd4;`
241			`state <= S_VW2;`
242			`end`
243			`end`
244			`else if(state == S_VW2) begin`
245			`if(burst_write_request == 1'b0) begin`
246			`burst_write_ready <= 1'b0;`
247			`ssram_adsc_n <= 1'b1;`
248			`ssram_advance_n <= 1'b1;`
249			`ssram_data_oe <= 1'b0;`
250			`ssram_writeen_n <= 1'b1;`
251			`state <= S_PRE_IDLE;`
252			`end`
253			`else begin`
254			`ssram_adsc_n <= 1'b1;`
255			`ssram_advance_n <= 1'b0;`
256			`ssram_data_reg <= burst_write_data;`
257
258			`state <= S_VW3;`
259			`end`
260			`end`
261			`else if(state == S_VW3) begin`
262			`if(burst_write_request == 1'b0) begin`
263			`burst_write_ready <= 1'b0;`
264			`ssram_adsc_n <= 1'b1;`
265			`ssram_advance_n <= 1'b1;`
266			`ssram_data_oe <= 1'b0;`
267			`ssram_writeen_n <= 1'b1;`
268			`state <= S_PRE_IDLE;`
269			`end`
270			`else begin`
271			`ssram_data_reg <= burst_write_data;`
272
273			`state <= S_VW4;`
274			`end`
275			`end`
276			`else if(state == S_VW4) begin`
277			`if(burst_write_request == 1'b0) begin`
278			`burst_write_ready <= 1'b0;`
279			`ssram_adsc_n <= 1'b1;`
280			`ssram_advance_n <= 1'b1;`
281			`ssram_data_oe <= 1'b0;`
282			`ssram_writeen_n <= 1'b1;`
283			`state <= S_PRE_IDLE;`
284			`end`
285			`else begin`
286			`ssram_data_reg <= burst_write_data;`
287
288			`state <= S_VW1;`
289			`end`
290			`end`
291			`else if(state == S_VR1) begin`
292			`if(burst_read_request == 1'b0) begin`
293			`burst_read_ready <= 1'b0;`
294			`ssram_adsc_n <= 1'b1;`
295			`ssram_advance_n <= 1'b1;`
296			`state <= S_PRE_IDLE;`
297			`end`
298			`else begin`
299			`if(burst_read_low_address[3:2] == 2'b10 && burst_read_one_loop == 1'b1) burst_read_ready <= 1'b1;`
300
301			`// address and byte enables latched`
302			`ssram_adsc_n <= 1'b1;`
303			`ssram_advance_n <= 1'b0;`
304
305			`burst_read_data <= ssram_data;`
306			`state <= S_VR2;`
307			`end`
308			`end`
309			`else if(state == S_VR2) begin`
310			`if(burst_read_request == 1'b0) begin`
311			`burst_read_ready <= 1'b0;`
312			`ssram_adsc_n <= 1'b1;`
313			`ssram_advance_n <= 1'b1;`
314			`state <= S_PRE_IDLE;`
315			`end`
316			`else begin`
317			`if(burst_read_low_address[3:2] == 2'b11 && burst_read_one_loop == 1'b1) burst_read_ready <= 1'b1;`
318
319			`// output enable output`
320			`ssram_oe_n <= 1'b0;`
321
322			`burst_read_data <= ssram_data;`
323			`state <= S_VR3;`
324			`end`
325			`end`
326			`else if(state == S_VR3) begin`
327			`if(burst_read_request == 1'b0) begin`
328			`burst_read_ready <= 1'b0;`
329			`ssram_adsc_n <= 1'b1;`
330			`ssram_advance_n <= 1'b1;`
331			`state <= S_PRE_IDLE;`
332			`end`
333			`else begin`
334			`if(burst_read_low_address[3:2] == 2'b00) burst_read_ready <= 1'b1;`
335
336			`burst_read_data <= ssram_data;`
337			`state <= S_VR4;`
338			`end`
339			`end`
340			`else if(state == S_VR4) begin`
341			`if(burst_read_request == 1'b0) begin`
342			`burst_read_ready <= 1'b0;`
343			`ssram_adsc_n <= 1'b1;`
344			`ssram_advance_n <= 1'b1;`
345			`state <= S_PRE_IDLE;`
346			`end`
347			`else begin`
348			`if(burst_read_low_address[3:2] == 2'b01) burst_read_ready <= 1'b1;`
349			`burst_read_one_loop <= 1'b1;`
350
351			`ssram_address <= burst_address;`
352			`ssram_adsc_n <= 1'b0;`
353			`ssram_advance_n <= 1'b1;`
354
355			`burst_read_data <= ssram_data;`
356			`burst_address <= burst_address + 19'd4;`
357			`state <= S_VR1;`
358			`end`
359			`end`
360			`else if(state == S_R1) begin`
361			`// address and byte enables latched`
362			`ssram_adsc_n <= 1'b1;`
363			`ssram_advance_n <= 1'b1;`
364
365			`state <= S_R2;`
366			`end`
367			`else if(state == S_R2) begin`
368			`// output enable output`
369			`ssram_oe_n <= 1'b0;`
370
371			`state <= S_R3;`
372			`end`
373			`else if(state == S_R3) begin`
374			`DAT_O <= ssram_data[31:0];`
375			`ACK_O <= 1'b1;`
376
377			`ssram_address <= 19'd0;`
378			`ssram_adsc_n <= 1'b1;`
379			`ssram_advance_n <= 1'b1;`
380			`ssram_data_reg <= 36'd0;`
381			`ssram_data_oe <= 1'b0;`
382			`ssram_oe_n <= 1'b1;`
383			`ssram_writeen_n <= 1'b1;`
384			`ssram_byteen_n <= 4'b1111;`
385
386			`state <= S_IDLE;`
387			`end`
388			`else if(state == S_PRE_IDLE) begin`
389			`ACK_O <= 1'b0;`
390
391			`ssram_address <= 19'd0;`
392			`ssram_adsc_n <= 1'b1;`
393			`ssram_advance_n <= 1'b1;`
394			`ssram_data_reg <= 36'd0;`
395			`ssram_data_oe <= 1'b0;`
396			`ssram_oe_n <= 1'b1;`
397			`ssram_writeen_n <= 1'b1;`
398			`ssram_byteen_n <= 4'b1111;`
399
400			`state <= S_IDLE;`
401			`end`
402			`end`
403
404			`endmodule`