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[/] [aoocs/] [trunk/] [tests/] [audio_test/] [audio_test.v] - Blame information for rev 2

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module audio_test(
    input clk_50,
    input reset_ext_n,
 
    // audio codec
    output ac_sclk,
    inout ac_sdat,
    output ac_xclk,
    output reg ac_bclk,
    output ac_dat,
    output reg ac_lr,
 
    output [7:0] pc_debug
);
 
assign pc_debug = { 4'd0, state };
 
wire clk_30;
wire clk_12;
wire pll_locked;
 
altpll pll_inst(
    .inclk( {1'b0, clk_50} ),
    .clk( {clk_12, clk_30} ), //{5'b0, clk_30} ),
    .locked(pll_locked)
);
defparam    pll_inst.clk0_divide_by = 5,
            pll_inst.clk0_duty_cycle = 50,
            pll_inst.clk0_multiply_by = 3,
            pll_inst.clk0_phase_shift = "0",
            pll_inst.clk1_divide_by = 25,
            pll_inst.clk1_duty_cycle = 50,
            pll_inst.clk1_multiply_by = 6,
            pll_inst.clk1_phase_shift = "0",
            pll_inst.compensate_clock = "CLK0",
            pll_inst.gate_lock_counter = 1048575,
            pll_inst.gate_lock_signal = "YES",
            pll_inst.inclk0_input_frequency = 20000,
            pll_inst.intended_device_family = "Cyclone II",
            pll_inst.invalid_lock_multiplier = 5,
            pll_inst.lpm_hint = "CBX_MODULE_PREFIX=pll30",
            pll_inst.lpm_type = "altpll",
            pll_inst.operation_mode = "NORMAL",
            pll_inst.valid_lock_multiplier = 1;
 
wire reset_n;
assign reset_n = pll_locked & reset_ext_n;
 
reg [5:0] volume0f;
reg [5:0] volume1f;
reg [5:0] volume2f;
reg [5:0] volume3f;
reg [7:0] sample0f;
reg [7:0] sample1f;
reg [7:0] sample2f;
reg [7:0] sample3f;
 
always @(posedge clk_12 or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        volume0f <= 6'd0;
        volume1f <= 6'd0;
        volume2f <= 6'd0;
        volume3f <= 6'd0;
        sample0f <= 8'd0;
        sample1f <= 8'd0;
        sample2f <= 8'd0;
        sample3f <= 8'd0;
    end
    else begin
        volume0f <= 6'd60;
        volume1f <= 6'd60;
        volume2f <= 6'd60;
        volume3f <= 6'd60;
 
        sample0f <= sample0f + 8'd1;
        sample1f <= sample1f + 8'd1;
        sample2f <= sample2f + 8'd1;
        sample3f <= sample3f + 8'd1;
    end
end
 
 
 
assign ac_dat = left_right_sample[31];
assign ac_xclk = clk_12;
 
// left MSB-LSB, right MSB-LSB
reg [31:0] left_right_sample;
reg [7:0] data_counter;
 
wire [13:0] mult_left_1;
assign mult_left_1 =
    ((volume1f[0] == 1'b1)? { {6{sample1f[7]}}, sample1f[7:0] } : 14'd0) +
    ((volume1f[1] == 1'b1)? { {5{sample1f[7]}}, sample1f[7:0], 1'b0 } : 14'd0) +
    ((volume1f[2] == 1'b1)? { {4{sample1f[7]}}, sample1f[7:0], 2'b0 } : 14'd0) +
    ((volume1f[3] == 1'b1)? { {3{sample1f[7]}}, sample1f[7:0], 3'b0 } : 14'd0) +
    ((volume1f[4] == 1'b1)? { {2{sample1f[7]}}, sample1f[7:0], 4'b0 } : 14'd0) +
    ((volume1f[5] == 1'b1)? { {1{sample1f[7]}}, sample1f[7:0], 5'b0 } : 14'd0);
 
wire [13:0] mult_left_2;
assign mult_left_2 =
    ((volume2f[0] == 1'b1)? { {6{sample2f[7]}}, sample2f[7:0] } : 14'd0) +
    ((volume2f[1] == 1'b1)? { {5{sample2f[7]}}, sample2f[7:0], 1'b0 } : 14'd0) +
    ((volume2f[2] == 1'b1)? { {4{sample2f[7]}}, sample2f[7:0], 2'b0 } : 14'd0) +
    ((volume2f[3] == 1'b1)? { {3{sample2f[7]}}, sample2f[7:0], 3'b0 } : 14'd0) +
    ((volume2f[4] == 1'b1)? { {2{sample2f[7]}}, sample2f[7:0], 4'b0 } : 14'd0) +
    ((volume2f[5] == 1'b1)? { {1{sample2f[7]}}, sample2f[7:0], 5'b0 } : 14'd0);
 
wire [13:0] mult_right_0;
assign mult_right_0 =
    ((volume0f[0] == 1'b1)? { {6{sample0f[7]}}, sample0f[7:0] } : 14'd0) +
    ((volume0f[1] == 1'b1)? { {5{sample0f[7]}}, sample0f[7:0], 1'b0 } : 14'd0) +
    ((volume0f[2] == 1'b1)? { {4{sample0f[7]}}, sample0f[7:0], 2'b0 } : 14'd0) +
    ((volume0f[3] == 1'b1)? { {3{sample0f[7]}}, sample0f[7:0], 3'b0 } : 14'd0) +
    ((volume0f[4] == 1'b1)? { {2{sample0f[7]}}, sample0f[7:0], 4'b0 } : 14'd0) +
    ((volume0f[5] == 1'b1)? { {1{sample0f[7]}}, sample0f[7:0], 5'b0 } : 14'd0);
 
wire [13:0] mult_right_3;
assign mult_right_3 =
    ((volume3f[0] == 1'b1)? { {6{sample3f[7]}}, sample3f[7:0] } : 14'd0) +
    ((volume3f[1] == 1'b1)? { {5{sample3f[7]}}, sample3f[7:0], 1'b0 } : 14'd0) +
    ((volume3f[2] == 1'b1)? { {4{sample3f[7]}}, sample3f[7:0], 2'b0 } : 14'd0) +
    ((volume3f[3] == 1'b1)? { {3{sample3f[7]}}, sample3f[7:0], 3'b0 } : 14'd0) +
    ((volume3f[4] == 1'b1)? { {2{sample3f[7]}}, sample3f[7:0], 4'b0 } : 14'd0) +
    ((volume3f[5] == 1'b1)? { {1{sample3f[7]}}, sample3f[7:0], 5'b0 } : 14'd0);
 
wire [14:0] left_channel;
assign left_channel = mult_left_1 + mult_left_2;
 
wire [14:0] right_channel;
assign right_channel = mult_right_0 + mult_right_3;
 
always @(posedge clk_12 or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        data_counter        <= 8'd0;
        left_right_sample   <= 32'd0;
        ac_bclk             <= 1'b0;
        ac_lr               <= 1'b0;
    end
    else if(data_counter == 8'd0 && state == S_READY) begin
        data_counter <= data_counter + 8'd1;
        left_right_sample <= { 1'b0, left_channel, 1'b0, right_channel };
        ac_bclk <= 1'b0;
        ac_lr <= 1'b1;
    end
    else if(data_counter == 8'd1) begin
        data_counter <= data_counter + 8'd1;
        ac_bclk <= 1'b1;
        ac_lr <= 1'b1;
    end
    else if(data_counter >= 8'd127 && data_counter <= 8'd248) begin
        data_counter <= data_counter + 8'd1;
        left_right_sample <= { left_right_sample[30:0], 1'b0 };
        ac_bclk <= 1'b0;
        ac_lr <= 1'b0;
    end
    else if(data_counter == 8'd249) begin
        data_counter <= 8'd0;
        ac_bclk <= 1'b0;
        ac_lr <= 1'b0;
    end
    else if(data_counter[1:0] == 2'b11) begin
        data_counter <= data_counter + 8'd1;
        left_right_sample <= { left_right_sample[30:0], 1'b0 };
        ac_bclk <= 1'b0;
        ac_lr <= 1'b0;
    end
    else if(data_counter[1:0] == 2'b01) begin
        data_counter <= data_counter + 8'd1;
        ac_bclk <= 1'b1;
        ac_lr <= 1'b0;
    end
    else if(data_counter != 8'd0 && state == S_READY) begin
        data_counter <= data_counter + 8'd1;
    end
end
 
reg i2c_start;
reg [15:0] i2c_data;
reg [3:0] state;
 
parameter [3:0]
    S_IDLE      = 4'd0,
    S_RESET     = 4'd1,
    S_POWER     = 4'd2,
    S_OUTPUT    = 4'd3,
    S_SIDE      = 4'd4,
    S_EMPH      = 4'd5,
    S_FORMAT    = 4'd6,
    S_SAMPLING  = 4'd7,
    S_ACTIVATE  = 4'd8,
    S_READY     = 4'd9;
 
wire i2c_ready;
 
i2c_send i2c_send_inst(
    .clk_12(clk_12),
    .reset_n(reset_n),
 
    .start(i2c_start),
    .data(i2c_data),
    .ready(i2c_ready),
 
    .sclk(ac_sclk),
    .sdat(ac_sdat)
);
 
always @(posedge clk_12 or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        i2c_start <= 1'b0;
        i2c_data <= 16'd0;
        state <= S_IDLE;
    end
    else begin
        if(state == S_IDLE) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0001111_000000000;
            state <= S_RESET;
        end
        else if(state == S_RESET && i2c_ready == 1'b1) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0000110_001100111; // power down unused parts
            state <= S_POWER;
        end
        else if(state == S_POWER && i2c_ready == 1'b1) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0000010_101111111; // +3dB headphone output
            state <= S_OUTPUT;
        end
        else if(state == S_OUTPUT && i2c_ready == 1'b1) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0000100_011010010; // DAC select
            state <= S_SIDE;
        end
        else if(state == S_SIDE && i2c_ready == 1'b1) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0000101_000000011; // disable mute, 32kHz de-emphasis
            state <= S_EMPH;
        end
        else if(state == S_EMPH && i2c_ready == 1'b1) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0000111_000000011; // DSP mode
            state <= S_FORMAT;
        end
        else if(state == S_FORMAT && i2c_ready == 1'b1) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0001000_000000001; // USB mode, 12MHz, 48 kHz
            state <= S_SAMPLING;
        end
        else if(state == S_SAMPLING && i2c_ready == 1'b1) begin
            i2c_start <= 1'b1;
            i2c_data <= 16'b0001001_000000001;
            state <= S_ACTIVATE;
        end
        else if(state == S_ACTIVATE && i2c_ready == 1'b1) begin
            state <= S_READY;
        end
        else begin
            i2c_start <= 1'b0;
        end
    end
end
 
endmodule
 
 
module i2c_send(
    input clk_12,
    input reset_n,
 
    input start,
    input [15:0] data,
    output ready,
 
    output reg sclk,
    inout sdat
);
 
assign ready = (state == S_IDLE && start == 1'b0);
assign sdat = (sdat_oe == 1'b0)? 1'bZ : sdat_o;
 
reg sdat_oe;
reg sdat_o;
reg [7:0] dat_byte;
reg [1:0] part;
reg [2:0] counter;
reg [3:0] state;
parameter [3:0]
    S_IDLE      = 4'd0,
    S_SEND_0    = 4'd1,
    S_SEND_1    = 4'd2,
    S_SEND_2    = 4'd3,
    S_SEND_3    = 4'd4,
    S_SEND_4    = 4'd5,
    S_END_0     = 4'd6,
    S_END_1     = 4'd7,
    S_END_2     = 4'd8;
 
always @(posedge clk_12 or negedge reset_n) begin
    if(reset_n == 1'b0) begin
        sclk <= 1'b1;
        sdat_oe <= 1'b0;
        sdat_o <= 1'b1;
        dat_byte <= 8'd0;
        part <= 2'b0;
        counter <= 3'd0;
        state <= S_IDLE;
    end
    else if(state == S_IDLE && start == 1'b1) begin
        // start
        sdat_oe <= 1'b1;
        sdat_o <= 1'b0;
        sclk <= 1'b1;
 
        part <= 2'b0;
        dat_byte <= 8'b0011010_0;
        counter <= 3'd7;
        state <= S_SEND_0;
    end
    else if(state == S_SEND_0) begin
        sdat_oe <= 1'b1;
        sdat_o <= dat_byte[7];
        sclk <= 1'b0;
        state <= S_SEND_1;
    end
    else if(state == S_SEND_1) begin
        sclk <= 1'b1;
 
        if(counter == 3'd0) state <= S_SEND_2;
        else begin
            dat_byte <= { dat_byte[6:0], 1'b0 };
            counter <= counter - 3'd1;
            state <= S_SEND_0;
        end
    end
    else if(state == S_SEND_2) begin
        sdat_oe <= 1'b0;
        sclk <= 1'b0;
        state <= S_SEND_3;
    end
    else if(state == S_SEND_3) begin
        sclk <= 1'b1;
        state <= S_SEND_4;
    end
    else if(state == S_SEND_4 && sdat == 1'b0) begin
        sclk <= 1'b0;
        part <= part + 2'b1;
        counter <= 3'd7;
 
        if(part == 2'd0)        dat_byte <= data[15:8];
        else if(part == 2'd1)   dat_byte <= data[7:0];
 
        if(part == 2'd0 || part == 2'd1)    state <= S_SEND_0;
        else                                state <= S_END_0;
    end
    else if(state == S_END_0) begin
        sdat_oe <= 1'b1;
        sdat_o <= 1'b0;
        sclk <= 1'b0;
        state <= S_END_1;
    end
    else if(state == S_END_1) begin
        sclk <= 1'b1;
        state <= S_END_2;
    end
    else if(state == S_END_2) begin
        // end
        sdat_oe <= 1'b0;
        state <= S_IDLE;
    end
end
 
endmodule
 

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[/] [aoocs/] [trunk/] [tests/] [audio_test/] [audio_test.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik
2			`module audio_test(`
3			`input clk_50,`
4			`input reset_ext_n,`
5
6			`// audio codec`
7			`output ac_sclk,`
8			`inout ac_sdat,`
9			`output ac_xclk,`
10			`output reg ac_bclk,`
11			`output ac_dat,`
12			`output reg ac_lr,`
13
14			`output [7:0] pc_debug`
15			`);`
16
17			`assign pc_debug = { 4'd0, state };`
18
19			`wire clk_30;`
20			`wire clk_12;`
21			`wire pll_locked;`
22
23			`altpll pll_inst(`
24			`.inclk( {1'b0, clk_50} ),`
25			`.clk( {clk_12, clk_30} ), //{5'b0, clk_30} ),`
26			`.locked(pll_locked)`
27			`);`
28			`defparam pll_inst.clk0_divide_by = 5,`
29			`pll_inst.clk0_duty_cycle = 50,`
30			`pll_inst.clk0_multiply_by = 3,`
31			`pll_inst.clk0_phase_shift = "0",`
32			`pll_inst.clk1_divide_by = 25,`
33			`pll_inst.clk1_duty_cycle = 50,`
34			`pll_inst.clk1_multiply_by = 6,`
35			`pll_inst.clk1_phase_shift = "0",`
36			`pll_inst.compensate_clock = "CLK0",`
37			`pll_inst.gate_lock_counter = 1048575,`
38			`pll_inst.gate_lock_signal = "YES",`
39			`pll_inst.inclk0_input_frequency = 20000,`
40			`pll_inst.intended_device_family = "Cyclone II",`
41			`pll_inst.invalid_lock_multiplier = 5,`
42			`pll_inst.lpm_hint = "CBX_MODULE_PREFIX=pll30",`
43			`pll_inst.lpm_type = "altpll",`
44			`pll_inst.operation_mode = "NORMAL",`
45			`pll_inst.valid_lock_multiplier = 1;`
46
47			`wire reset_n;`
48			`assign reset_n = pll_locked & reset_ext_n;`
49
50			`reg [5:0] volume0f;`
51			`reg [5:0] volume1f;`
52			`reg [5:0] volume2f;`
53			`reg [5:0] volume3f;`
54			`reg [7:0] sample0f;`
55			`reg [7:0] sample1f;`
56			`reg [7:0] sample2f;`
57			`reg [7:0] sample3f;`
58
59			`always @(posedge clk_12 or negedge reset_n) begin`
60			`if(reset_n == 1'b0) begin`
61			`volume0f <= 6'd0;`
62			`volume1f <= 6'd0;`
63			`volume2f <= 6'd0;`
64			`volume3f <= 6'd0;`
65			`sample0f <= 8'd0;`
66			`sample1f <= 8'd0;`
67			`sample2f <= 8'd0;`
68			`sample3f <= 8'd0;`
69			`end`
70			`else begin`
71			`volume0f <= 6'd60;`
72			`volume1f <= 6'd60;`
73			`volume2f <= 6'd60;`
74			`volume3f <= 6'd60;`
75
76			`sample0f <= sample0f + 8'd1;`
77			`sample1f <= sample1f + 8'd1;`
78			`sample2f <= sample2f + 8'd1;`
79			`sample3f <= sample3f + 8'd1;`
80			`end`
81			`end`
82
83
84
85			`assign ac_dat = left_right_sample[31];`
86			`assign ac_xclk = clk_12;`
87
88			`// left MSB-LSB, right MSB-LSB`
89			`reg [31:0] left_right_sample;`
90			`reg [7:0] data_counter;`
91
92			`wire [13:0] mult_left_1;`
93			`assign mult_left_1 =`
94			`((volume1f[0] == 1'b1)? { {6{sample1f[7]}}, sample1f[7:0] } : 14'd0) +`
95			`((volume1f[1] == 1'b1)? { {5{sample1f[7]}}, sample1f[7:0], 1'b0 } : 14'd0) +`
96			`((volume1f[2] == 1'b1)? { {4{sample1f[7]}}, sample1f[7:0], 2'b0 } : 14'd0) +`
97			`((volume1f[3] == 1'b1)? { {3{sample1f[7]}}, sample1f[7:0], 3'b0 } : 14'd0) +`
98			`((volume1f[4] == 1'b1)? { {2{sample1f[7]}}, sample1f[7:0], 4'b0 } : 14'd0) +`
99			`((volume1f[5] == 1'b1)? { {1{sample1f[7]}}, sample1f[7:0], 5'b0 } : 14'd0);`
100
101			`wire [13:0] mult_left_2;`
102			`assign mult_left_2 =`
103			`((volume2f[0] == 1'b1)? { {6{sample2f[7]}}, sample2f[7:0] } : 14'd0) +`
104			`((volume2f[1] == 1'b1)? { {5{sample2f[7]}}, sample2f[7:0], 1'b0 } : 14'd0) +`
105			`((volume2f[2] == 1'b1)? { {4{sample2f[7]}}, sample2f[7:0], 2'b0 } : 14'd0) +`
106			`((volume2f[3] == 1'b1)? { {3{sample2f[7]}}, sample2f[7:0], 3'b0 } : 14'd0) +`
107			`((volume2f[4] == 1'b1)? { {2{sample2f[7]}}, sample2f[7:0], 4'b0 } : 14'd0) +`
108			`((volume2f[5] == 1'b1)? { {1{sample2f[7]}}, sample2f[7:0], 5'b0 } : 14'd0);`
109
110			`wire [13:0] mult_right_0;`
111			`assign mult_right_0 =`
112			`((volume0f[0] == 1'b1)? { {6{sample0f[7]}}, sample0f[7:0] } : 14'd0) +`
113			`((volume0f[1] == 1'b1)? { {5{sample0f[7]}}, sample0f[7:0], 1'b0 } : 14'd0) +`
114			`((volume0f[2] == 1'b1)? { {4{sample0f[7]}}, sample0f[7:0], 2'b0 } : 14'd0) +`
115			`((volume0f[3] == 1'b1)? { {3{sample0f[7]}}, sample0f[7:0], 3'b0 } : 14'd0) +`
116			`((volume0f[4] == 1'b1)? { {2{sample0f[7]}}, sample0f[7:0], 4'b0 } : 14'd0) +`
117			`((volume0f[5] == 1'b1)? { {1{sample0f[7]}}, sample0f[7:0], 5'b0 } : 14'd0);`
118
119			`wire [13:0] mult_right_3;`
120			`assign mult_right_3 =`
121			`((volume3f[0] == 1'b1)? { {6{sample3f[7]}}, sample3f[7:0] } : 14'd0) +`
122			`((volume3f[1] == 1'b1)? { {5{sample3f[7]}}, sample3f[7:0], 1'b0 } : 14'd0) +`
123			`((volume3f[2] == 1'b1)? { {4{sample3f[7]}}, sample3f[7:0], 2'b0 } : 14'd0) +`
124			`((volume3f[3] == 1'b1)? { {3{sample3f[7]}}, sample3f[7:0], 3'b0 } : 14'd0) +`
125			`((volume3f[4] == 1'b1)? { {2{sample3f[7]}}, sample3f[7:0], 4'b0 } : 14'd0) +`
126			`((volume3f[5] == 1'b1)? { {1{sample3f[7]}}, sample3f[7:0], 5'b0 } : 14'd0);`
127
128			`wire [14:0] left_channel;`
129			`assign left_channel = mult_left_1 + mult_left_2;`
130
131			`wire [14:0] right_channel;`
132			`assign right_channel = mult_right_0 + mult_right_3;`
133
134			`always @(posedge clk_12 or negedge reset_n) begin`
135			`if(reset_n == 1'b0) begin`
136			`data_counter <= 8'd0;`
137			`left_right_sample <= 32'd0;`
138			`ac_bclk <= 1'b0;`
139			`ac_lr <= 1'b0;`
140			`end`
141			`else if(data_counter == 8'd0 && state == S_READY) begin`
142			`data_counter <= data_counter + 8'd1;`
143			`left_right_sample <= { 1'b0, left_channel, 1'b0, right_channel };`
144			`ac_bclk <= 1'b0;`
145			`ac_lr <= 1'b1;`
146			`end`
147			`else if(data_counter == 8'd1) begin`
148			`data_counter <= data_counter + 8'd1;`
149			`ac_bclk <= 1'b1;`
150			`ac_lr <= 1'b1;`
151			`end`
152			`else if(data_counter >= 8'd127 && data_counter <= 8'd248) begin`
153			`data_counter <= data_counter + 8'd1;`
154			`left_right_sample <= { left_right_sample[30:0], 1'b0 };`
155			`ac_bclk <= 1'b0;`
156			`ac_lr <= 1'b0;`
157			`end`
158			`else if(data_counter == 8'd249) begin`
159			`data_counter <= 8'd0;`
160			`ac_bclk <= 1'b0;`
161			`ac_lr <= 1'b0;`
162			`end`
163			`else if(data_counter[1:0] == 2'b11) begin`
164			`data_counter <= data_counter + 8'd1;`
165			`left_right_sample <= { left_right_sample[30:0], 1'b0 };`
166			`ac_bclk <= 1'b0;`
167			`ac_lr <= 1'b0;`
168			`end`
169			`else if(data_counter[1:0] == 2'b01) begin`
170			`data_counter <= data_counter + 8'd1;`
171			`ac_bclk <= 1'b1;`
172			`ac_lr <= 1'b0;`
173			`end`
174			`else if(data_counter != 8'd0 && state == S_READY) begin`
175			`data_counter <= data_counter + 8'd1;`
176			`end`
177			`end`
178
179			`reg i2c_start;`
180			`reg [15:0] i2c_data;`
181			`reg [3:0] state;`
182
183			`parameter [3:0]`
184			`S_IDLE = 4'd0,`
185			`S_RESET = 4'd1,`
186			`S_POWER = 4'd2,`
187			`S_OUTPUT = 4'd3,`
188			`S_SIDE = 4'd4,`
189			`S_EMPH = 4'd5,`
190			`S_FORMAT = 4'd6,`
191			`S_SAMPLING = 4'd7,`
192			`S_ACTIVATE = 4'd8,`
193			`S_READY = 4'd9;`
194
195			`wire i2c_ready;`
196
197			`i2c_send i2c_send_inst(`
198			`.clk_12(clk_12),`
199			`.reset_n(reset_n),`
200
201			`.start(i2c_start),`
202			`.data(i2c_data),`
203			`.ready(i2c_ready),`
204
205			`.sclk(ac_sclk),`
206			`.sdat(ac_sdat)`
207			`);`
208
209			`always @(posedge clk_12 or negedge reset_n) begin`
210			`if(reset_n == 1'b0) begin`
211			`i2c_start <= 1'b0;`
212			`i2c_data <= 16'd0;`
213			`state <= S_IDLE;`
214			`end`
215			`else begin`
216			`if(state == S_IDLE) begin`
217			`i2c_start <= 1'b1;`
218			`i2c_data <= 16'b0001111_000000000;`
219			`state <= S_RESET;`
220			`end`
221			`else if(state == S_RESET && i2c_ready == 1'b1) begin`
222			`i2c_start <= 1'b1;`
223			`i2c_data <= 16'b0000110_001100111; // power down unused parts`
224			`state <= S_POWER;`
225			`end`
226			`else if(state == S_POWER && i2c_ready == 1'b1) begin`
227			`i2c_start <= 1'b1;`
228			`i2c_data <= 16'b0000010_101111111; // +3dB headphone output`
229			`state <= S_OUTPUT;`
230			`end`
231			`else if(state == S_OUTPUT && i2c_ready == 1'b1) begin`
232			`i2c_start <= 1'b1;`
233			`i2c_data <= 16'b0000100_011010010; // DAC select`
234			`state <= S_SIDE;`
235			`end`
236			`else if(state == S_SIDE && i2c_ready == 1'b1) begin`
237			`i2c_start <= 1'b1;`
238			`i2c_data <= 16'b0000101_000000011; // disable mute, 32kHz de-emphasis`
239			`state <= S_EMPH;`
240			`end`
241			`else if(state == S_EMPH && i2c_ready == 1'b1) begin`
242			`i2c_start <= 1'b1;`
243			`i2c_data <= 16'b0000111_000000011; // DSP mode`
244			`state <= S_FORMAT;`
245			`end`
246			`else if(state == S_FORMAT && i2c_ready == 1'b1) begin`
247			`i2c_start <= 1'b1;`
248			`i2c_data <= 16'b0001000_000000001; // USB mode, 12MHz, 48 kHz`
249			`state <= S_SAMPLING;`
250			`end`
251			`else if(state == S_SAMPLING && i2c_ready == 1'b1) begin`
252			`i2c_start <= 1'b1;`
253			`i2c_data <= 16'b0001001_000000001;`
254			`state <= S_ACTIVATE;`
255			`end`
256			`else if(state == S_ACTIVATE && i2c_ready == 1'b1) begin`
257			`state <= S_READY;`
258			`end`
259			`else begin`
260			`i2c_start <= 1'b0;`
261			`end`
262			`end`
263			`end`
264
265			`endmodule`
266
267
268			`module i2c_send(`
269			`input clk_12,`
270			`input reset_n,`
271
272			`input start,`
273			`input [15:0] data,`
274			`output ready,`
275
276			`output reg sclk,`
277			`inout sdat`
278			`);`
279
280			`assign ready = (state == S_IDLE && start == 1'b0);`
281			`assign sdat = (sdat_oe == 1'b0)? 1'bZ : sdat_o;`
282
283			`reg sdat_oe;`
284			`reg sdat_o;`
285			`reg [7:0] dat_byte;`
286			`reg [1:0] part;`
287			`reg [2:0] counter;`
288			`reg [3:0] state;`
289			`parameter [3:0]`
290			`S_IDLE = 4'd0,`
291			`S_SEND_0 = 4'd1,`
292			`S_SEND_1 = 4'd2,`
293			`S_SEND_2 = 4'd3,`
294			`S_SEND_3 = 4'd4,`
295			`S_SEND_4 = 4'd5,`
296			`S_END_0 = 4'd6,`
297			`S_END_1 = 4'd7,`
298			`S_END_2 = 4'd8;`
299
300			`always @(posedge clk_12 or negedge reset_n) begin`
301			`if(reset_n == 1'b0) begin`
302			`sclk <= 1'b1;`
303			`sdat_oe <= 1'b0;`
304			`sdat_o <= 1'b1;`
305			`dat_byte <= 8'd0;`
306			`part <= 2'b0;`
307			`counter <= 3'd0;`
308			`state <= S_IDLE;`
309			`end`
310			`else if(state == S_IDLE && start == 1'b1) begin`
311			`// start`
312			`sdat_oe <= 1'b1;`
313			`sdat_o <= 1'b0;`
314			`sclk <= 1'b1;`
315
316			`part <= 2'b0;`
317			`dat_byte <= 8'b0011010_0;`
318			`counter <= 3'd7;`
319			`state <= S_SEND_0;`
320			`end`
321			`else if(state == S_SEND_0) begin`
322			`sdat_oe <= 1'b1;`
323			`sdat_o <= dat_byte[7];`
324			`sclk <= 1'b0;`
325			`state <= S_SEND_1;`
326			`end`
327			`else if(state == S_SEND_1) begin`
328			`sclk <= 1'b1;`
329
330			`if(counter == 3'd0) state <= S_SEND_2;`
331			`else begin`
332			`dat_byte <= { dat_byte[6:0], 1'b0 };`
333			`counter <= counter - 3'd1;`
334			`state <= S_SEND_0;`
335			`end`
336			`end`
337			`else if(state == S_SEND_2) begin`
338			`sdat_oe <= 1'b0;`
339			`sclk <= 1'b0;`
340			`state <= S_SEND_3;`
341			`end`
342			`else if(state == S_SEND_3) begin`
343			`sclk <= 1'b1;`
344			`state <= S_SEND_4;`
345			`end`
346			`else if(state == S_SEND_4 && sdat == 1'b0) begin`
347			`sclk <= 1'b0;`
348			`part <= part + 2'b1;`
349			`counter <= 3'd7;`
350
351			`if(part == 2'd0) dat_byte <= data[15:8];`
352			`else if(part == 2'd1) dat_byte <= data[7:0];`
353
354			`if(part == 2'd0 \|\| part == 2'd1) state <= S_SEND_0;`
355			`else state <= S_END_0;`
356			`end`
357			`else if(state == S_END_0) begin`
358			`sdat_oe <= 1'b1;`
359			`sdat_o <= 1'b0;`
360			`sclk <= 1'b0;`
361			`state <= S_END_1;`
362			`end`
363			`else if(state == S_END_1) begin`
364			`sclk <= 1'b1;`
365			`state <= S_END_2;`
366			`end`
367			`else if(state == S_END_2) begin`
368			`// end`
369			`sdat_oe <= 1'b0;`
370			`state <= S_IDLE;`
371			`end`
372			`end`
373
374			`endmodule`
375