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alfik |
module ps2_mouse_test(
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input clk_50,
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input reset_ext_n,
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inout ps2_mouseclk,
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inout ps2_mousedat,
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output [7:0] debug,
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output [7:0] debug2
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);
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wire CLK_I;
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wire pll_locked;
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altpll pll_inst(
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.inclk( {1'b0, clk_50} ),
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.clk( CLK_I ), //{5'b0, clk_30} ),
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.locked(pll_locked)
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);
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defparam pll_inst.clk0_divide_by = 5,
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pll_inst.clk0_duty_cycle = 50,
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pll_inst.clk0_multiply_by = 3,
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pll_inst.clk0_phase_shift = "0",
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pll_inst.compensate_clock = "CLK0",
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pll_inst.gate_lock_counter = 1048575,
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pll_inst.gate_lock_signal = "YES",
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pll_inst.inclk0_input_frequency = 20000,
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pll_inst.intended_device_family = "Cyclone II",
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pll_inst.invalid_lock_multiplier = 5,
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pll_inst.lpm_hint = "CBX_MODULE_PREFIX=pll30",
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pll_inst.lpm_type = "altpll",
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pll_inst.operation_mode = "NORMAL",
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pll_inst.valid_lock_multiplier = 1;
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wire reset_n;
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assign reset_n = pll_locked & reset_ext_n;
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assign debug = send_counter[7:0];
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assign debug2 = ctrl_counter[7:0];
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// ----------------------------------------------------------------------------- PS/2 mouse
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assign ps2_mouseclk = (send_counter >= 12'd1 && send_counter < 12'd4000) ? 1'b0 : 1'bZ;
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assign ps2_mousedat = (send_counter >= 12'd4000 && send_counter <= 12'd4009) ? send_shift[0] : 1'bZ;
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reg [15:0] mv;
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reg mv_wait;
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reg was_ps2_mouseclk;
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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mv <= 16'd0;
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mv_wait <= 1'b0;
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was_ps2_mouseclk <= 1'b0;
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end
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else begin
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mv <= { mv[14:0], ps2_mouseclk };
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if(mv_wait == 1'b0 && mv[15:12] == 4'b1111 && mv[3:0] == 4'b0000) begin
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was_ps2_mouseclk <= 1'b1;
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mv_wait <= 1'b1;
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end
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else if(mv_wait == 1'b1 && mv[15:0] == 16'h0000) begin
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mv_wait <= 1'b0;
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was_ps2_mouseclk <= 1'b0;
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end
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else begin
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was_ps2_mouseclk <= 1'b0;
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end
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end
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end
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reg [11:0] send_counter;
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reg [9:0] send_shift;
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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send_counter <= 12'd0;
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send_shift <= 10'd0;
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end
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else if(send_start == 1'b1) begin
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send_counter <= 12'd1;
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send_shift <= send_contents;
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end
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else if(send_counter > 12'd0 && send_counter < 12'd4000) begin
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send_counter <= send_counter + 12'd1;
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end
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else if(send_counter >= 12'd4000 && send_counter <= 12'd4009 && was_ps2_mouseclk == 1'b1) begin
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send_counter <= send_counter + 12'd1;
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if(send_counter <= 12'd4007) begin
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send_shift <= { send_shift[9] ^ send_shift[0], 1'b0, send_shift[8:1] };
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end
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else if(send_counter == 12'd4008) begin
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send_shift <= { 9'd0, send_shift[9] ^ send_shift[0] };
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end
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end
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else if(send_counter == 12'd4010 && was_ps2_mouseclk == 1'b1) begin
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if(ps2_mousedat == 1'b0) send_counter <= send_counter + 12'd1;
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end
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else if(send_counter == 12'd4011 && ps2_mouseclk == 1'b1 && ps2_mousedat == 1'b1) begin
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send_counter <= 12'd0;
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end
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end
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reg send_start;
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reg [9:0] send_contents;
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reg [23:0] ctrl_counter;
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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send_start <= 1'b0;
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send_contents <= 10'd0;
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ctrl_counter <= 24'd0;
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end
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else if(ctrl_counter < 24'hFFFFF0) begin
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ctrl_counter <= ctrl_counter + 16'd1;
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end
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else if(ctrl_counter == 24'hFFFFF0) begin
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send_contents <= { 1'b1, 8'hF4, 1'b0 };
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send_start <= 1'b1;
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ctrl_counter <= ctrl_counter + 24'd1;
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end
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else if(ctrl_counter == 24'hFFFFF1) begin
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send_start <= 1'b0;
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ctrl_counter <= ctrl_counter + 24'd1;
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end
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else if(ctrl_counter == 24'hFFFFF2 && send_counter == 12'd0) begin
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ctrl_counter <= ctrl_counter + 24'd1;
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end
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else if(ctrl_counter == 24'hFFFFF3 && new_ps2 == 1'b1 && mousedat[8:1] == 8'hFA) begin
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ctrl_counter <= 24'hFFFFFF;
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end
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else if(ctrl_counter == 24'hFFFFFF && (mousedat_timeout == 24'hFFFFFF || movement_timeout == 24'hFFFFFF)) begin
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ctrl_counter <= 24'h0;
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end
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end
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wire new_ps2;
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assign new_ps2 = (was_ps2_mouseclk == 1'b1 && mousedat_counter == 4'd10 && mousedat[0] == 1'b0 && ps2_mousedat == 1'b1 && mousedat_parity == 1'b1);
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reg [9:0] mousedat;
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reg [3:0] mousedat_counter;
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reg [23:0] mousedat_timeout;
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reg mousedat_parity;
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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mousedat <= 10'd0;
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mousedat_counter <= 4'd0;
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mousedat_parity <= 1'b0;
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mousedat_timeout <= 24'd0;
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end
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else if(ctrl_counter >= 24'hFFFFF3 && mousedat_timeout != 24'hFFFFFF) begin
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if(mousedat_counter != 4'd0) mousedat_timeout <= mousedat_timeout + 24'd1;
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else if(mousedat_counter == 4'd0) mousedat_timeout <= 24'd0;
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if(was_ps2_mouseclk == 1'b1) begin
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mousedat <= { ps2_mousedat, mousedat[9:1] };
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if(mousedat_counter == 4'd10) begin
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mousedat_counter <= 4'd0;
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end
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else begin
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mousedat_counter <= mousedat_counter + 4'd1;
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if(mousedat_counter == 4'd0) mousedat_parity <= 1'b0;
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else if(ps2_mousedat == 1'b1) mousedat_parity <= ~mousedat_parity;
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end
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end
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end
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else begin
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mousedat <= 10'd0;
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mousedat_counter <= 4'd0;
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mousedat_parity <= 1'b0;
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mousedat_timeout <= 24'd0;
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end
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end
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//assign mouse_y_move = (movement[23] == 1'b0)? { movement[21], movement[7:0] } : 9'd0;
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//assign mouse_x_move = (movement[22] == 1'b0)? { movement[20], movement[15:8] } : 9'd0;
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//assign mouse_left_button = movement[16];
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//assign mouse_right_button = movement[17];
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//assign mouse_middle_button = movement[18];
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reg mouse_moved;
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reg [1:0] movement_counter;
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reg [23:0] movement;
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reg [23:0] movement_timeout;
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always @(posedge CLK_I or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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movement_counter <= 2'd0;
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movement <= 24'd0;
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mouse_moved <= 1'b0;
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movement_timeout <= 24'd0;
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end
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else if(ctrl_counter == 24'hFFFFFF && movement_timeout != 24'hFFFFFF) begin
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if(movement_counter != 4'd0) movement_timeout <= movement_timeout + 24'd1;
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else if(movement_counter == 4'd0) movement_timeout <= 24'd0;
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if(mouse_moved == 1'b1) mouse_moved <= 1'b0;
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if(new_ps2 == 1'b1) begin
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movement <= { movement[15:0], mousedat[8:1] };
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if(movement_counter == 2'd2) begin
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movement_counter <= 2'd0;
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if(movement[11] == 1'b1) mouse_moved <= 1'b1;
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else movement_timeout <= 24'hFFFFFF;
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end
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else movement_counter <= movement_counter + 2'd1;
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end
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end
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else begin
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movement_counter <= 2'd0;
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movement <= 24'd0;
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mouse_moved <= 1'b0;
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movement_timeout <= 24'd0;
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end
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end
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// ----------------------------------------------------------------------------- PS/2 mouse END
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wire write_ena;
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assign write_ena = (mouse_moved == 1'b1); //(was_ps2_mouseclk == 1'b1 && ctrl_counter >= 24'hFFFF00 && (ctrl_counter[3:0] == 4'h3 || ctrl_counter[3:0] == 4'h4));
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reg [7:0] debug_addr;
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always @(posedge CLK_I) if(write_ena && debug_addr < 8'd255) debug_addr <= debug_addr + 8'd1;
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altsyncram debug_ram_inst(
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.clock0(CLK_I),
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.wren_a(write_ena),
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.address_a(debug_addr),
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.data_a( movement )
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);
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defparam debug_ram_inst.operation_mode = "SINGLE_PORT";
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defparam debug_ram_inst.width_a = 24;
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defparam debug_ram_inst.widthad_a = 8;
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defparam debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=mouse";
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endmodule
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