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alfik |
/*
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* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are
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* permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module serial_txd(
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input clk_30,
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input reset_n,
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// WISHBONE slave
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input [7:0] DAT_I,
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output reg ACK_O,
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input CYC_I,
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input STB_I,
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input WE_I,
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//serial output
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input uart_rxd,
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input uart_rts,
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output reg uart_txd,
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output uart_cts
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);
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assign uart_cts = uart_rts;
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reg [12:0] counter;
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// 115200 baud -> 8680.5555 ns / bit = 260 * 33.333 ns
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parameter [9:0] one_bit = 10'd260;
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always @(posedge clk_30 or negedge reset_n) begin
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if(reset_n == 1'b0) begin
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ACK_O <= 1'b0;
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uart_txd <= 1'b1;
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counter <= 13'd0;
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end
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else if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && ACK_O == 1'b0) begin
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if(counter < 13'd8191) counter <= counter + 13'd1;
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if(counter < one_bit*1) uart_txd <= 1'b0;
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else if(counter < one_bit*2) uart_txd <= DAT_I[0];
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else if(counter < one_bit*3) uart_txd <= DAT_I[1];
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else if(counter < one_bit*4) uart_txd <= DAT_I[2];
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else if(counter < one_bit*5) uart_txd <= DAT_I[3];
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else if(counter < one_bit*6) uart_txd <= DAT_I[4];
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else if(counter < one_bit*7) uart_txd <= DAT_I[5];
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else if(counter < one_bit*8) uart_txd <= DAT_I[6];
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else if(counter < one_bit*9) uart_txd <= DAT_I[7];
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else if(counter < one_bit*10) uart_txd <= 1'b1;
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else begin
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uart_txd <= 1'b1;
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ACK_O <= 1'b1;
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end
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end
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else begin
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ACK_O <= 1'b0;
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uart_txd <= 1'b1;
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counter <= 13'd0;
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end
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end
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endmodule
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