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alfik |
/*
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* This file is subject to the terms and conditions of the BSD License. See
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* the file "LICENSE" in the main directory of this archive for more details.
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*
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* Copyright (C) 2014 Aleksander Osman
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*/
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`include "defines.v"
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module aoR3000(
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input clk,
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input rst_n,
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//
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input [5:0] interrupt_vector,
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//
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output [31:0] avm_address,
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output [31:0] avm_writedata,
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output [3:0] avm_byteenable,
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output [2:0] avm_burstcount,
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output avm_write,
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output avm_read,
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input avm_waitrequest,
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input avm_readdatavalid,
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input [31:0] avm_readdata
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);
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//------------------------------------------------------------------------------
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wire if_exc_address_error;
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wire if_exc_tlb_inv;
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wire if_exc_tlb_miss;
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wire if_ready;
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wire [31:0] if_instr;
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wire [31:0] if_pc;
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wire [8:0] fetch_cache_read_address;
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wire [8:0] fetch_cache_write_address;
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wire fetch_cache_write_enable;
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wire [53:0] fetch_cache_data;
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wire tlb_ram_fetch_start;
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wire [19:0] tlb_ram_fetch_vpn;
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wire [31:0] ram_instr_address;
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wire ram_instr_req;
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pipeline_if pipeline_if_inst(
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.clk (clk),
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.rst_n (rst_n),
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//
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.config_kernel_mode (config_kernel_mode), //input
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.entryhi_asid (entryhi_asid), //input [5:0]
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//
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.micro_flush_do (micro_flush_do), //input
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//
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.exception_start (exception_start), //input
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.exception_start_pc (exception_start_pc), //input [31:0]
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//
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.mem_stall (mem_stall), //input
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//
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.if_exc_address_error (if_exc_address_error), //output
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.if_exc_tlb_inv (if_exc_tlb_inv), //output
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.if_exc_tlb_miss (if_exc_tlb_miss), //output
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.if_ready (if_ready), //output
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.if_instr (if_instr), //output [31:0]
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.if_pc (if_pc), //output [31:0]
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//
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.branch_start (branch_start), //input
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.branch_address (branch_address), //input [31:0]
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//
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.fetch_cache_read_address (fetch_cache_read_address), //output [8:0]
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.fetch_cache_q (fetch_cache_q), //input [53:0]
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.fetch_cache_write_address (fetch_cache_write_address),//output [8:0]
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.fetch_cache_write_enable (fetch_cache_write_enable), //output
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.fetch_cache_data (fetch_cache_data), //output [53:0]
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//
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.tlb_ram_fetch_start (tlb_ram_fetch_start), //output
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.tlb_ram_fetch_vpn (tlb_ram_fetch_vpn), //output [19:0]
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.tlb_ram_fetch_hit (tlb_ram_fetch_hit), //input
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.tlb_ram_fetch_result (tlb_ram_fetch_result), //input [49:0]
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.tlb_ram_fetch_missed (tlb_ram_fetch_missed), //input
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//
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.ram_instr_address (ram_instr_address), //output [31:0]
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.ram_instr_req (ram_instr_req), //output
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.ram_instr_ack (ram_instr_ack), //input
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//
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.ram_result_address (ram_result_address), //input [31:0]
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.ram_result_valid (ram_result_valid), //input
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.ram_result_is_read_instr (ram_result_is_read_instr), //input
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.ram_result_burstcount (ram_result_burstcount), //input [2:0]
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.ram_result (ram_result) //input [31:0]
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);
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//------------------------------------------------------------------------------
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wire [6:0] rf_cmd;
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wire [31:0] rf_instr;
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wire [31:0] rf_pc_plus4;
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wire [31:0] rf_badvpn;
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wire [31:0] rf_a;
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wire [31:0] rf_b;
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pipeline_rf pipeline_rf_inst(
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.clk (clk),
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.rst_n (rst_n),
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//
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.exception_start (exception_start), //input
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//
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.if_exc_address_error (if_exc_address_error), //input
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.if_exc_tlb_inv (if_exc_tlb_inv), //input
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.if_exc_tlb_miss (if_exc_tlb_miss), //input
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.if_ready (if_ready), //input
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.if_instr (if_instr), //input [31:0]
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.if_pc (if_pc), //input [31:0]
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//
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.rf_cmd (rf_cmd), //output [6:0]
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.rf_instr (rf_instr), //output [31:0]
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.rf_pc_plus4 (rf_pc_plus4), //output [31:0]
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.rf_badvpn (rf_badvpn), //output [31:0]
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.rf_a (rf_a), //output [31:0]
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.rf_b (rf_b), //output [31:0]
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//
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.mem_stall (mem_stall), //input
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//
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.exe_result_index (exe_result_index), //input [4:0]
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.exe_result (exe_result), //input [31:0]
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.mem_result_index (mem_result_index), //input [4:0]
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.mem_result (mem_result), //input [31:0]
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.muldiv_result_index (muldiv_result_index), //input [4:0]
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.muldiv_result (muldiv_result) //input [31:0]
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);
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//------------------------------------------------------------------------------
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wire [6:0] exe_cmd;
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wire [31:0] exe_instr;
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wire [31:0] exe_pc_plus4;
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wire exe_pc_user_seg;
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wire [31:0] exe_badvpn;
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wire [31:0] exe_a;
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wire [31:0] exe_b;
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wire [1:0] exe_branched;
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wire [31:0] exe_branch_address;
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wire exe_cmd_cp0;
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wire exe_cmd_load;
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wire exe_cmd_store;
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wire [4:0] exe_result_index;
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wire [31:0] exe_result;
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wire [31:0] data_address_next;
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wire [31:0] data_address;
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wire branch_start;
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wire [31:0] branch_address;
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pipeline_exe pipeline_exe_inst(
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.clk (clk),
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.rst_n (rst_n),
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//
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.config_kernel_mode (config_kernel_mode), //input
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//
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.exception_start (exception_start), //input
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//
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.mem_stall (mem_stall), //input
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//
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.rf_cmd (rf_cmd), //input [6:0]
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.rf_instr (rf_instr), //input [31:0]
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.rf_pc_plus4 (rf_pc_plus4), //input [31:0]
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.rf_badvpn (rf_badvpn), //input [31:0]
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.rf_a (rf_a), //input [31:0]
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.rf_b (rf_b), //input [31:0]
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//
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.exe_cmd (exe_cmd), //output [6:0]
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.exe_instr (exe_instr), //output [31:0]
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.exe_pc_plus4 (exe_pc_plus4), //output [31:0]
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.exe_pc_user_seg (exe_pc_user_seg), //output
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.exe_badvpn (exe_badvpn), //output [31:0]
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.exe_a (exe_a), //output [31:0]
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.exe_b (exe_b), //output [31:0]
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.exe_branched (exe_branched), //output [1:0]
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.exe_branch_address (exe_branch_address), //output [31:0]
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.exe_cmd_cp0 (exe_cmd_cp0), //output
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.exe_cmd_load (exe_cmd_load), //output
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.exe_cmd_store (exe_cmd_store), //output
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//
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.exe_result_index (exe_result_index), //output [4:0]
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.exe_result (exe_result), //output [31:0]
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//
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.data_address_next (data_address_next), //output [31:0]
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.data_address (data_address), //output [31:0]
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//
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.branch_start (branch_start), //output
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.branch_address (branch_address), //output [31:0]
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//
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.write_buffer_counter (write_buffer_counter) //input [4:0]
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);
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//------------------------------------------------------------------------------
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wire mem_stall;
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wire config_kernel_mode;
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wire config_switch_caches;
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wire [4:0] mem_result_index;
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wire [31:0] mem_result;
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wire tlb_ram_read_do;
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wire [5:0] tlb_ram_read_index;
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wire tlb_ram_write_do;
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wire [5:0] tlb_ram_write_index;
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wire [49:0] tlb_ram_write_value;
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wire tlb_ram_data_start;
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wire [19:0] tlb_ram_data_vpn;
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wire micro_flush_do;
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wire [5:0] entryhi_asid;
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wire exception_start;
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wire [31:0] exception_start_pc;
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wire [8:0] data_cache_read_address;
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wire [8:0] data_cache_write_address;
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wire data_cache_write_enable;
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wire [53:0] data_cache_data;
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wire ram_fifo_wrreq;
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wire [66:0] ram_fifo_data;
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wire [4:0] muldiv_result_index;
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wire [31:0] muldiv_result;
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pipeline_mem pipeline_mem_inst(
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.clk (clk),
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.rst_n (rst_n),
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//
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.interrupt_vector (interrupt_vector), //input [5:0]
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//
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.mem_stall (mem_stall), //output
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//
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.config_kernel_mode (config_kernel_mode), //output
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.config_switch_caches (config_switch_caches), //output
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//
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.exe_cmd (exe_cmd), //input [6:0]
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.exe_instr (exe_instr), //input [31:0]
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.exe_pc_plus4 (exe_pc_plus4), //input [31:0]
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.exe_pc_user_seg (exe_pc_user_seg), //input
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.exe_badvpn (exe_badvpn), //input [31:0]
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.exe_a (exe_a), //input [31:0]
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.exe_b (exe_b), //input [31:0]
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.exe_branched (exe_branched), //input [1:0]
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.exe_branch_address (exe_branch_address), //input [31:0]
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.exe_cmd_cp0 (exe_cmd_cp0), //input
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.exe_cmd_load (exe_cmd_load), //input
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.exe_cmd_store (exe_cmd_store), //input
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//
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.exe_result_index (exe_result_index), //input [4:0]
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.exe_result (exe_result), //input [31:0]
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//
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.mem_result_index (mem_result_index), //output [4:0]
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.mem_result (mem_result), //output [31:0]
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//
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.muldiv_result_index (muldiv_result_index), //output [4:0]
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.muldiv_result (muldiv_result), //output [31:0]
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//
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.tlb_ram_read_do (tlb_ram_read_do), //output
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.tlb_ram_read_index (tlb_ram_read_index), //output [5:0]
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.tlb_ram_read_result_ready (tlb_ram_read_result_ready),//input
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.tlb_ram_read_result (tlb_ram_read_result), //input [49:0]
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//
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317 |
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.tlb_ram_write_do (tlb_ram_write_do), //output
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.tlb_ram_write_index (tlb_ram_write_index), //output [5:0]
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.tlb_ram_write_value (tlb_ram_write_value), //output [49:0]
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//
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.tlb_ram_data_start (tlb_ram_data_start), //output
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323 |
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.tlb_ram_data_vpn (tlb_ram_data_vpn), //output [19:0]
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.tlb_ram_data_hit (tlb_ram_data_hit), //input
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325 |
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.tlb_ram_data_index (tlb_ram_data_index), //input [5:0]
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.tlb_ram_data_result (tlb_ram_data_result), //input [49:0]
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.tlb_ram_data_missed (tlb_ram_data_missed), //input
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328 |
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//
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330 |
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.exception_start (exception_start), //output
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331 |
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.exception_start_pc (exception_start_pc), //output [31:0]
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332 |
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//
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334 |
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.micro_flush_do (micro_flush_do), //output
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335 |
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.entryhi_asid (entryhi_asid), //output [5:0]
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336 |
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337 |
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//
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338 |
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.data_address_next (data_address_next), //input [31:0]
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339 |
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.data_address (data_address), //input [31:0]
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340 |
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//
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342 |
|
|
.data_cache_read_address (data_cache_read_address), //output [8:0]
|
343 |
|
|
.data_cache_q (data_cache_q), //input [53:0]
|
344 |
|
|
|
345 |
|
|
.data_cache_write_address (data_cache_write_address), //output [8:0]
|
346 |
|
|
.data_cache_write_enable (data_cache_write_enable), //output
|
347 |
|
|
.data_cache_data (data_cache_data), //output [53:0]
|
348 |
|
|
|
349 |
|
|
//
|
350 |
|
|
.ram_fifo_wrreq (ram_fifo_wrreq), //output
|
351 |
|
|
.ram_fifo_data (ram_fifo_data), //output [66:0]
|
352 |
|
|
.ram_fifo_full (ram_fifo_full), //input
|
353 |
|
|
|
354 |
|
|
//
|
355 |
|
|
.ram_result_address (ram_result_address), //input [31:0]
|
356 |
|
|
.ram_result_valid (ram_result_valid), //input
|
357 |
|
|
.ram_result_is_read_instr (ram_result_is_read_instr), //input
|
358 |
|
|
.ram_result_burstcount (ram_result_burstcount), //input [2:0]
|
359 |
|
|
.ram_result (ram_result) //input [31:0]
|
360 |
|
|
);
|
361 |
|
|
|
362 |
|
|
//------------------------------------------------------------------------------
|
363 |
|
|
|
364 |
|
|
wire [53:0] fetch_cache_q;
|
365 |
|
|
|
366 |
|
|
wire [53:0] data_cache_q;
|
367 |
|
|
|
368 |
|
|
wire ram_fifo_empty;
|
369 |
|
|
wire ram_fifo_full;
|
370 |
|
|
wire [66:0] ram_fifo_q;
|
371 |
|
|
|
372 |
|
|
wire [4:0] write_buffer_counter;
|
373 |
|
|
|
374 |
|
|
memory_ram memory_ram_inst(
|
375 |
|
|
.clk (clk),
|
376 |
|
|
.rst_n (rst_n),
|
377 |
|
|
|
378 |
|
|
//
|
379 |
|
|
.config_switch_caches (config_switch_caches), //input
|
380 |
|
|
|
381 |
|
|
//
|
382 |
|
|
.fetch_cache_read_address (fetch_cache_read_address), //input [8:0]
|
383 |
|
|
.fetch_cache_q (fetch_cache_q), //input [53:0]
|
384 |
|
|
|
385 |
|
|
.fetch_cache_write_address (fetch_cache_write_address),//input [8:0]
|
386 |
|
|
.fetch_cache_write_enable (fetch_cache_write_enable), //input
|
387 |
|
|
.fetch_cache_data (fetch_cache_data), //input [53:0]
|
388 |
|
|
|
389 |
|
|
//
|
390 |
|
|
.data_cache_read_address (data_cache_read_address), //input [8:0]
|
391 |
|
|
.data_cache_q (data_cache_q), //output [53:0]
|
392 |
|
|
|
393 |
|
|
.data_cache_write_address (data_cache_write_address), //input [8:0]
|
394 |
|
|
.data_cache_write_enable (data_cache_write_enable), //input
|
395 |
|
|
.data_cache_data (data_cache_data), //input [53:0]
|
396 |
|
|
|
397 |
|
|
//ram_fifo
|
398 |
|
|
.ram_fifo_rdreq (ram_fifo_rdreq), //input
|
399 |
|
|
.ram_fifo_wrreq (ram_fifo_wrreq), //input
|
400 |
|
|
.ram_fifo_data (ram_fifo_data), //input [66:0]
|
401 |
|
|
|
402 |
|
|
.ram_fifo_empty (ram_fifo_empty), //output
|
403 |
|
|
.ram_fifo_full (ram_fifo_full), //output
|
404 |
|
|
.ram_fifo_q (ram_fifo_q), //output [66:0]
|
405 |
|
|
|
406 |
|
|
.write_buffer_counter (write_buffer_counter) //output [4:0]
|
407 |
|
|
);
|
408 |
|
|
|
409 |
|
|
//------------------------------------------------------------------------------
|
410 |
|
|
|
411 |
|
|
wire tlb_ram_read_result_ready;
|
412 |
|
|
wire [49:0] tlb_ram_read_result;
|
413 |
|
|
|
414 |
|
|
wire tlb_ram_data_hit;
|
415 |
|
|
wire [5:0] tlb_ram_data_index;
|
416 |
|
|
wire [49:0] tlb_ram_data_result;
|
417 |
|
|
wire tlb_ram_data_missed;
|
418 |
|
|
|
419 |
|
|
wire tlb_ram_fetch_hit;
|
420 |
|
|
wire [49:0] tlb_ram_fetch_result;
|
421 |
|
|
wire tlb_ram_fetch_missed;
|
422 |
|
|
|
423 |
|
|
memory_tlb_ram memory_tlb_ram_inst(
|
424 |
|
|
.clk (clk),
|
425 |
|
|
.rst_n (rst_n),
|
426 |
|
|
|
427 |
|
|
//
|
428 |
|
|
.tlb_ram_read_do (tlb_ram_read_do), //input
|
429 |
|
|
.tlb_ram_read_index (tlb_ram_read_index), //input [5:0]
|
430 |
|
|
.tlb_ram_read_result_ready (tlb_ram_read_result_ready),//output
|
431 |
|
|
.tlb_ram_read_result (tlb_ram_read_result), //output [49:0]
|
432 |
|
|
|
433 |
|
|
//
|
434 |
|
|
.tlb_ram_write_do (tlb_ram_write_do), //input
|
435 |
|
|
.tlb_ram_write_index (tlb_ram_write_index), //input [5:0]
|
436 |
|
|
.tlb_ram_write_value (tlb_ram_write_value), //input [49:0]
|
437 |
|
|
|
438 |
|
|
//
|
439 |
|
|
.entryhi_asid (entryhi_asid), //input [5:0]
|
440 |
|
|
|
441 |
|
|
//
|
442 |
|
|
.tlb_ram_data_start (tlb_ram_data_start), //input
|
443 |
|
|
.tlb_ram_data_vpn (tlb_ram_data_vpn), //input [19:0]
|
444 |
|
|
.tlb_ram_data_hit (tlb_ram_data_hit), //output
|
445 |
|
|
.tlb_ram_data_index (tlb_ram_data_index), //output [5:0]
|
446 |
|
|
.tlb_ram_data_result (tlb_ram_data_result), //output [49:0]
|
447 |
|
|
.tlb_ram_data_missed (tlb_ram_data_missed), //output
|
448 |
|
|
|
449 |
|
|
//
|
450 |
|
|
.tlb_ram_fetch_start (tlb_ram_fetch_start), //input
|
451 |
|
|
.tlb_ram_fetch_vpn (tlb_ram_fetch_vpn), //input [19:0]
|
452 |
|
|
.tlb_ram_fetch_hit (tlb_ram_fetch_hit), //output
|
453 |
|
|
.tlb_ram_fetch_result (tlb_ram_fetch_result), //output [49:0]
|
454 |
|
|
.tlb_ram_fetch_missed (tlb_ram_fetch_missed) //output
|
455 |
|
|
);
|
456 |
|
|
|
457 |
|
|
//------------------------------------------------------------------------------
|
458 |
|
|
|
459 |
|
|
wire ram_fifo_rdreq;
|
460 |
|
|
|
461 |
|
|
wire [31:0] ram_result_address;
|
462 |
|
|
wire ram_result_valid;
|
463 |
|
|
wire ram_result_is_read_instr;
|
464 |
|
|
wire [2:0] ram_result_burstcount;
|
465 |
|
|
wire [31:0] ram_result;
|
466 |
|
|
|
467 |
|
|
wire ram_instr_ack;
|
468 |
|
|
|
469 |
|
|
memory_avalon memory_avalon_inst(
|
470 |
|
|
.clk (clk),
|
471 |
|
|
.rst_n (rst_n),
|
472 |
|
|
|
473 |
|
|
.ram_fifo_q (ram_fifo_q), //input [66:0]
|
474 |
|
|
.ram_fifo_empty (ram_fifo_empty), //input
|
475 |
|
|
.ram_fifo_rdreq (ram_fifo_rdreq), //output
|
476 |
|
|
|
477 |
|
|
//
|
478 |
|
|
.ram_instr_address (ram_instr_address), //input [31:0]
|
479 |
|
|
.ram_instr_req (ram_instr_req), //input
|
480 |
|
|
.ram_instr_ack (ram_instr_ack), //output
|
481 |
|
|
|
482 |
|
|
.ram_result_address (ram_result_address), //output [31:0]
|
483 |
|
|
.ram_result_valid (ram_result_valid), //output
|
484 |
|
|
.ram_result_is_read_instr (ram_result_is_read_instr), //output
|
485 |
|
|
.ram_result_burstcount (ram_result_burstcount), //output [2:0]
|
486 |
|
|
.ram_result (ram_result), //output [31:0]
|
487 |
|
|
|
488 |
|
|
//
|
489 |
|
|
.avm_address (avm_address), //output [31:0]
|
490 |
|
|
.avm_writedata (avm_writedata), //output [31:0]
|
491 |
|
|
.avm_byteenable (avm_byteenable), //output [3:0]
|
492 |
|
|
.avm_burstcount (avm_burstcount), //output [2:0]
|
493 |
|
|
.avm_write (avm_write), //output
|
494 |
|
|
.avm_read (avm_read), //output
|
495 |
|
|
|
496 |
|
|
.avm_waitrequest (avm_waitrequest), //input
|
497 |
|
|
.avm_readdatavalid (avm_readdatavalid), //input
|
498 |
|
|
.avm_readdata (avm_readdata) //input [31:0]
|
499 |
|
|
);
|
500 |
|
|
|
501 |
|
|
//------------------------------------------------------------------------------
|
502 |
|
|
|
503 |
|
|
endmodule
|