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[/] [aor3000/] [trunk/] [rtl/] [aoR3000.v] - Blame information for rev 2

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1 2 alfik
/*
2
 * This file is subject to the terms and conditions of the BSD License. See
3
 * the file "LICENSE" in the main directory of this archive for more details.
4
 *
5
 * Copyright (C) 2014 Aleksander Osman
6
 */
7
 
8
`include "defines.v"
9
 
10
module aoR3000(
11
    input               clk,
12
    input               rst_n,
13
 
14
    //
15
    input       [5:0]   interrupt_vector,
16
 
17
    //
18
    output      [31:0]  avm_address,
19
    output      [31:0]  avm_writedata,
20
    output      [3:0]   avm_byteenable,
21
    output      [2:0]   avm_burstcount,
22
    output              avm_write,
23
    output              avm_read,
24
 
25
    input               avm_waitrequest,
26
    input               avm_readdatavalid,
27
    input       [31:0]  avm_readdata
28
);
29
 
30
//------------------------------------------------------------------------------
31
 
32
wire        if_exc_address_error;
33
wire        if_exc_tlb_inv;
34
wire        if_exc_tlb_miss;
35
 
36
wire        if_ready;
37
wire [31:0] if_instr;
38
wire [31:0] if_pc;
39
 
40
wire [8:0]  fetch_cache_read_address;
41
wire [8:0]  fetch_cache_write_address;
42
wire        fetch_cache_write_enable;
43
wire [53:0] fetch_cache_data;
44
 
45
wire        tlb_ram_fetch_start;
46
wire [19:0] tlb_ram_fetch_vpn;
47
 
48
wire [31:0] ram_instr_address;
49
wire        ram_instr_req;
50
 
51
 
52
pipeline_if pipeline_if_inst(
53
    .clk                        (clk),
54
    .rst_n                      (rst_n),
55
 
56
    //
57
    .config_kernel_mode         (config_kernel_mode),       //input
58
    .entryhi_asid               (entryhi_asid),             //input [5:0]
59
 
60
    //
61
    .micro_flush_do             (micro_flush_do),           //input
62
 
63
    //
64
    .exception_start            (exception_start),          //input
65
    .exception_start_pc         (exception_start_pc),       //input [31:0]
66
 
67
    //
68
    .mem_stall                  (mem_stall),                //input
69
 
70
    //
71
    .if_exc_address_error       (if_exc_address_error),     //output
72
    .if_exc_tlb_inv             (if_exc_tlb_inv),           //output
73
    .if_exc_tlb_miss            (if_exc_tlb_miss),          //output
74
    .if_ready                   (if_ready),                 //output
75
    .if_instr                   (if_instr),                 //output [31:0]
76
    .if_pc                      (if_pc),                    //output [31:0]
77
 
78
    //
79
    .branch_start               (branch_start),             //input
80
    .branch_address             (branch_address),           //input [31:0]
81
 
82
    //
83
    .fetch_cache_read_address   (fetch_cache_read_address), //output [8:0]
84
    .fetch_cache_q              (fetch_cache_q),            //input [53:0]
85
 
86
    .fetch_cache_write_address  (fetch_cache_write_address),//output [8:0]
87
    .fetch_cache_write_enable   (fetch_cache_write_enable), //output
88
    .fetch_cache_data           (fetch_cache_data),         //output [53:0]
89
 
90
 
91
    //
92
    .tlb_ram_fetch_start        (tlb_ram_fetch_start),      //output
93
    .tlb_ram_fetch_vpn          (tlb_ram_fetch_vpn),        //output [19:0]
94
    .tlb_ram_fetch_hit          (tlb_ram_fetch_hit),        //input
95
    .tlb_ram_fetch_result       (tlb_ram_fetch_result),     //input [49:0]
96
    .tlb_ram_fetch_missed       (tlb_ram_fetch_missed),     //input
97
 
98
    //
99
    .ram_instr_address          (ram_instr_address),        //output [31:0]
100
    .ram_instr_req              (ram_instr_req),            //output
101
    .ram_instr_ack              (ram_instr_ack),            //input
102
 
103
    //
104
    .ram_result_address         (ram_result_address),       //input [31:0]
105
    .ram_result_valid           (ram_result_valid),         //input
106
    .ram_result_is_read_instr   (ram_result_is_read_instr), //input
107
    .ram_result_burstcount      (ram_result_burstcount),    //input [2:0]
108
    .ram_result                 (ram_result)                //input [31:0]
109
);
110
 
111
 
112
//------------------------------------------------------------------------------
113
 
114
wire [6:0]  rf_cmd;
115
wire [31:0] rf_instr;
116
wire [31:0] rf_pc_plus4;
117
wire [31:0] rf_badvpn;
118
wire [31:0] rf_a;
119
wire [31:0] rf_b;
120
 
121
pipeline_rf pipeline_rf_inst(
122
    .clk                        (clk),
123
    .rst_n                      (rst_n),
124
 
125
    //
126
    .exception_start            (exception_start),      //input
127
 
128
    //
129
    .if_exc_address_error       (if_exc_address_error), //input
130
    .if_exc_tlb_inv             (if_exc_tlb_inv),       //input
131
    .if_exc_tlb_miss            (if_exc_tlb_miss),      //input
132
    .if_ready                   (if_ready),             //input
133
    .if_instr                   (if_instr),             //input [31:0]
134
    .if_pc                      (if_pc),                //input [31:0]
135
 
136
    //
137
    .rf_cmd                     (rf_cmd),               //output [6:0]
138
    .rf_instr                   (rf_instr),             //output [31:0]
139
    .rf_pc_plus4                (rf_pc_plus4),          //output [31:0]
140
    .rf_badvpn                  (rf_badvpn),            //output [31:0]
141
    .rf_a                       (rf_a),                 //output [31:0]
142
    .rf_b                       (rf_b),                 //output [31:0]
143
 
144
    //
145
    .mem_stall                  (mem_stall),            //input
146
 
147
    //
148
    .exe_result_index           (exe_result_index),     //input [4:0]
149
    .exe_result                 (exe_result),           //input [31:0]
150
 
151
    .mem_result_index           (mem_result_index),     //input [4:0]
152
    .mem_result                 (mem_result),           //input [31:0]
153
 
154
    .muldiv_result_index        (muldiv_result_index),  //input [4:0]
155
    .muldiv_result              (muldiv_result)         //input [31:0]
156
);
157
 
158
//------------------------------------------------------------------------------
159
 
160
wire [6:0]  exe_cmd;
161
wire [31:0] exe_instr;
162
wire [31:0] exe_pc_plus4;
163
wire        exe_pc_user_seg;
164
wire [31:0] exe_badvpn;
165
wire [31:0] exe_a;
166
wire [31:0] exe_b;
167
wire [1:0]  exe_branched;
168
wire [31:0] exe_branch_address;
169
wire        exe_cmd_cp0;
170
wire        exe_cmd_load;
171
wire        exe_cmd_store;
172
 
173
wire [4:0]  exe_result_index;
174
wire [31:0] exe_result;
175
 
176
wire [31:0] data_address_next;
177
wire [31:0] data_address;
178
 
179
wire        branch_start;
180
wire [31:0] branch_address;
181
 
182
pipeline_exe pipeline_exe_inst(
183
    .clk                        (clk),
184
    .rst_n                      (rst_n),
185
 
186
    //
187
    .config_kernel_mode         (config_kernel_mode),       //input
188
 
189
    //
190
    .exception_start            (exception_start),          //input
191
 
192
    //
193
    .mem_stall                  (mem_stall),                //input
194
 
195
    //
196
    .rf_cmd                     (rf_cmd),                   //input [6:0]
197
    .rf_instr                   (rf_instr),                 //input [31:0]
198
    .rf_pc_plus4                (rf_pc_plus4),              //input [31:0]
199
    .rf_badvpn                  (rf_badvpn),                //input [31:0]
200
    .rf_a                       (rf_a),                     //input [31:0]
201
    .rf_b                       (rf_b),                     //input [31:0]
202
 
203
    //
204
    .exe_cmd                    (exe_cmd),                  //output [6:0]
205
    .exe_instr                  (exe_instr),                //output [31:0]
206
    .exe_pc_plus4               (exe_pc_plus4),             //output [31:0]
207
    .exe_pc_user_seg            (exe_pc_user_seg),          //output
208
    .exe_badvpn                 (exe_badvpn),               //output [31:0]
209
    .exe_a                      (exe_a),                    //output [31:0]
210
    .exe_b                      (exe_b),                    //output [31:0]
211
    .exe_branched               (exe_branched),             //output [1:0]
212
    .exe_branch_address         (exe_branch_address),       //output [31:0]
213
    .exe_cmd_cp0                (exe_cmd_cp0),              //output
214
    .exe_cmd_load               (exe_cmd_load),             //output
215
    .exe_cmd_store              (exe_cmd_store),            //output
216
 
217
    //
218
    .exe_result_index           (exe_result_index),         //output [4:0]
219
    .exe_result                 (exe_result),               //output [31:0]
220
 
221
    //
222
    .data_address_next          (data_address_next),        //output [31:0]
223
    .data_address               (data_address),             //output [31:0]
224
 
225
    //
226
    .branch_start               (branch_start),             //output
227
    .branch_address             (branch_address),           //output [31:0]
228
 
229
    //
230
    .write_buffer_counter       (write_buffer_counter)      //input [4:0]
231
);
232
 
233
//------------------------------------------------------------------------------
234
 
235
wire        mem_stall;
236
 
237
wire        config_kernel_mode;
238
wire        config_switch_caches;
239
 
240
wire [4:0]  mem_result_index;
241
wire [31:0] mem_result;
242
 
243
wire        tlb_ram_read_do;
244
wire [5:0]  tlb_ram_read_index;
245
 
246
wire        tlb_ram_write_do;
247
wire [5:0]  tlb_ram_write_index;
248
wire [49:0] tlb_ram_write_value;
249
 
250
wire        tlb_ram_data_start;
251
wire [19:0] tlb_ram_data_vpn;
252
 
253
wire        micro_flush_do;
254
wire [5:0]  entryhi_asid;
255
 
256
wire        exception_start;
257
wire [31:0] exception_start_pc;
258
 
259
wire [8:0]  data_cache_read_address;
260
wire [8:0]  data_cache_write_address;
261
wire        data_cache_write_enable;
262
wire [53:0] data_cache_data;
263
 
264
wire        ram_fifo_wrreq;
265
wire [66:0] ram_fifo_data;
266
 
267
wire [4:0]  muldiv_result_index;
268
wire [31:0] muldiv_result;
269
 
270
pipeline_mem pipeline_mem_inst(
271
    .clk                        (clk),
272
    .rst_n                      (rst_n),
273
 
274
    //
275
    .interrupt_vector           (interrupt_vector),         //input [5:0]
276
 
277
    //
278
    .mem_stall                  (mem_stall),                //output
279
 
280
    //
281
    .config_kernel_mode         (config_kernel_mode),       //output
282
    .config_switch_caches       (config_switch_caches),     //output
283
 
284
    //
285
    .exe_cmd                    (exe_cmd),                  //input [6:0]
286
    .exe_instr                  (exe_instr),                //input [31:0]
287
    .exe_pc_plus4               (exe_pc_plus4),             //input [31:0]
288
    .exe_pc_user_seg            (exe_pc_user_seg),          //input
289
    .exe_badvpn                 (exe_badvpn),               //input [31:0]
290
    .exe_a                      (exe_a),                    //input [31:0]
291
    .exe_b                      (exe_b),                    //input [31:0]
292
    .exe_branched               (exe_branched),             //input [1:0]
293
    .exe_branch_address         (exe_branch_address),       //input [31:0]
294
    .exe_cmd_cp0                (exe_cmd_cp0),              //input
295
    .exe_cmd_load               (exe_cmd_load),             //input
296
    .exe_cmd_store              (exe_cmd_store),            //input
297
 
298
    //
299
    .exe_result_index           (exe_result_index),         //input [4:0]
300
    .exe_result                 (exe_result),               //input [31:0]
301
 
302
    //
303
    .mem_result_index           (mem_result_index),         //output [4:0]
304
    .mem_result                 (mem_result),               //output [31:0]
305
 
306
    //
307
    .muldiv_result_index        (muldiv_result_index),      //output [4:0]
308
    .muldiv_result              (muldiv_result),            //output [31:0]
309
 
310
    //
311
    .tlb_ram_read_do            (tlb_ram_read_do),          //output
312
    .tlb_ram_read_index         (tlb_ram_read_index),       //output [5:0]
313
    .tlb_ram_read_result_ready  (tlb_ram_read_result_ready),//input
314
    .tlb_ram_read_result        (tlb_ram_read_result),      //input [49:0]
315
 
316
    //
317
    .tlb_ram_write_do           (tlb_ram_write_do),         //output
318
    .tlb_ram_write_index        (tlb_ram_write_index),      //output [5:0]
319
    .tlb_ram_write_value        (tlb_ram_write_value),      //output [49:0]
320
 
321
    //
322
    .tlb_ram_data_start         (tlb_ram_data_start),       //output
323
    .tlb_ram_data_vpn           (tlb_ram_data_vpn),         //output [19:0]
324
    .tlb_ram_data_hit           (tlb_ram_data_hit),         //input
325
    .tlb_ram_data_index         (tlb_ram_data_index),       //input [5:0]
326
    .tlb_ram_data_result        (tlb_ram_data_result),      //input [49:0]
327
    .tlb_ram_data_missed        (tlb_ram_data_missed),      //input
328
 
329
    //
330
    .exception_start            (exception_start),          //output
331
    .exception_start_pc         (exception_start_pc),       //output [31:0]
332
 
333
    //
334
    .micro_flush_do             (micro_flush_do),           //output
335
    .entryhi_asid               (entryhi_asid),             //output [5:0]
336
 
337
    //
338
    .data_address_next          (data_address_next),        //input [31:0]
339
    .data_address               (data_address),             //input [31:0]
340
 
341
    //
342
    .data_cache_read_address    (data_cache_read_address),  //output [8:0]
343
    .data_cache_q               (data_cache_q),             //input [53:0]
344
 
345
    .data_cache_write_address   (data_cache_write_address), //output [8:0]
346
    .data_cache_write_enable    (data_cache_write_enable),  //output
347
    .data_cache_data            (data_cache_data),          //output [53:0]
348
 
349
    //
350
    .ram_fifo_wrreq             (ram_fifo_wrreq),           //output
351
    .ram_fifo_data              (ram_fifo_data),            //output [66:0]
352
    .ram_fifo_full              (ram_fifo_full),            //input
353
 
354
    //
355
    .ram_result_address         (ram_result_address),       //input [31:0]
356
    .ram_result_valid           (ram_result_valid),         //input
357
    .ram_result_is_read_instr   (ram_result_is_read_instr), //input
358
    .ram_result_burstcount      (ram_result_burstcount),    //input [2:0]
359
    .ram_result                 (ram_result)                //input [31:0]
360
);
361
 
362
//------------------------------------------------------------------------------
363
 
364
wire [53:0] fetch_cache_q;
365
 
366
wire [53:0] data_cache_q;
367
 
368
wire        ram_fifo_empty;
369
wire        ram_fifo_full;
370
wire [66:0] ram_fifo_q;
371
 
372
wire [4:0]  write_buffer_counter;
373
 
374
memory_ram memory_ram_inst(
375
    .clk                        (clk),
376
    .rst_n                      (rst_n),
377
 
378
    //
379
    .config_switch_caches       (config_switch_caches),     //input
380
 
381
    //
382
    .fetch_cache_read_address   (fetch_cache_read_address), //input [8:0]
383
    .fetch_cache_q              (fetch_cache_q),            //input [53:0]
384
 
385
    .fetch_cache_write_address  (fetch_cache_write_address),//input [8:0]
386
    .fetch_cache_write_enable   (fetch_cache_write_enable), //input
387
    .fetch_cache_data           (fetch_cache_data),         //input [53:0]
388
 
389
    //
390
    .data_cache_read_address    (data_cache_read_address),  //input [8:0]
391
    .data_cache_q               (data_cache_q),             //output [53:0]
392
 
393
    .data_cache_write_address   (data_cache_write_address), //input [8:0]
394
    .data_cache_write_enable    (data_cache_write_enable),  //input
395
    .data_cache_data            (data_cache_data),          //input [53:0]
396
 
397
    //ram_fifo
398
    .ram_fifo_rdreq             (ram_fifo_rdreq),           //input
399
    .ram_fifo_wrreq             (ram_fifo_wrreq),           //input
400
    .ram_fifo_data              (ram_fifo_data),            //input [66:0]
401
 
402
    .ram_fifo_empty             (ram_fifo_empty),           //output
403
    .ram_fifo_full              (ram_fifo_full),            //output
404
    .ram_fifo_q                 (ram_fifo_q),               //output [66:0]
405
 
406
    .write_buffer_counter       (write_buffer_counter)      //output [4:0]
407
);
408
 
409
//------------------------------------------------------------------------------
410
 
411
wire        tlb_ram_read_result_ready;
412
wire [49:0] tlb_ram_read_result;
413
 
414
wire        tlb_ram_data_hit;
415
wire [5:0]  tlb_ram_data_index;
416
wire [49:0] tlb_ram_data_result;
417
wire        tlb_ram_data_missed;
418
 
419
wire        tlb_ram_fetch_hit;
420
wire [49:0] tlb_ram_fetch_result;
421
wire        tlb_ram_fetch_missed;
422
 
423
memory_tlb_ram memory_tlb_ram_inst(
424
    .clk                        (clk),
425
    .rst_n                      (rst_n),
426
 
427
    //
428
    .tlb_ram_read_do            (tlb_ram_read_do),          //input
429
    .tlb_ram_read_index         (tlb_ram_read_index),       //input [5:0]
430
    .tlb_ram_read_result_ready  (tlb_ram_read_result_ready),//output
431
    .tlb_ram_read_result        (tlb_ram_read_result),      //output [49:0]
432
 
433
    //
434
    .tlb_ram_write_do           (tlb_ram_write_do),         //input
435
    .tlb_ram_write_index        (tlb_ram_write_index),      //input [5:0]
436
    .tlb_ram_write_value        (tlb_ram_write_value),      //input [49:0]
437
 
438
    //
439
    .entryhi_asid               (entryhi_asid),             //input [5:0]
440
 
441
    //
442
    .tlb_ram_data_start         (tlb_ram_data_start),       //input
443
    .tlb_ram_data_vpn           (tlb_ram_data_vpn),         //input [19:0]
444
    .tlb_ram_data_hit           (tlb_ram_data_hit),         //output
445
    .tlb_ram_data_index         (tlb_ram_data_index),       //output [5:0]
446
    .tlb_ram_data_result        (tlb_ram_data_result),      //output [49:0]
447
    .tlb_ram_data_missed        (tlb_ram_data_missed),      //output
448
 
449
    //
450
    .tlb_ram_fetch_start        (tlb_ram_fetch_start),      //input
451
    .tlb_ram_fetch_vpn          (tlb_ram_fetch_vpn),        //input [19:0]
452
    .tlb_ram_fetch_hit          (tlb_ram_fetch_hit),        //output
453
    .tlb_ram_fetch_result       (tlb_ram_fetch_result),     //output [49:0]
454
    .tlb_ram_fetch_missed       (tlb_ram_fetch_missed)      //output
455
);
456
 
457
//------------------------------------------------------------------------------
458
 
459
wire        ram_fifo_rdreq;
460
 
461
wire [31:0] ram_result_address;
462
wire        ram_result_valid;
463
wire        ram_result_is_read_instr;
464
wire [2:0]  ram_result_burstcount;
465
wire [31:0] ram_result;
466
 
467
wire        ram_instr_ack;
468
 
469
memory_avalon memory_avalon_inst(
470
    .clk                        (clk),
471
    .rst_n                      (rst_n),
472
 
473
    .ram_fifo_q                 (ram_fifo_q),               //input [66:0]
474
    .ram_fifo_empty             (ram_fifo_empty),           //input
475
    .ram_fifo_rdreq             (ram_fifo_rdreq),           //output
476
 
477
    //
478
    .ram_instr_address          (ram_instr_address),        //input [31:0]
479
    .ram_instr_req              (ram_instr_req),            //input
480
    .ram_instr_ack              (ram_instr_ack),            //output
481
 
482
    .ram_result_address         (ram_result_address),       //output [31:0]
483
    .ram_result_valid           (ram_result_valid),         //output
484
    .ram_result_is_read_instr   (ram_result_is_read_instr), //output
485
    .ram_result_burstcount      (ram_result_burstcount),    //output [2:0]
486
    .ram_result                 (ram_result),               //output [31:0]
487
 
488
    //
489
    .avm_address                (avm_address),              //output [31:0]
490
    .avm_writedata              (avm_writedata),            //output [31:0]
491
    .avm_byteenable             (avm_byteenable),           //output [3:0]
492
    .avm_burstcount             (avm_burstcount),           //output [2:0]
493
    .avm_write                  (avm_write),                //output
494
    .avm_read                   (avm_read),                 //output
495
 
496
    .avm_waitrequest            (avm_waitrequest),          //input
497
    .avm_readdatavalid          (avm_readdatavalid),        //input
498
    .avm_readdata               (avm_readdata)              //input [31:0]
499
);
500
 
501
//------------------------------------------------------------------------------
502
 
503
endmodule

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