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alfik |
/*
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* This file is subject to the terms and conditions of the BSD License. See
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* the file "LICENSE" in the main directory of this archive for more details.
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*
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* Copyright (C) 2014 Aleksander Osman
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*/
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`include "defines.v"
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module block_cp0(
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input clk,
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input rst_n,
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//
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output reg config_switch_caches,
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output reg config_isolate_cache,
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output config_coproc0_usable,
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output config_coproc1_usable,
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output config_kernel_mode,
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//
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input exe_cmd_mtc0,
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input [31:0] exe_instr,
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input [31:0] exe_b,
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input exe_cmd_rfe,
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input exe_cmd_tlbr,
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input exe_cmd_tlbwi,
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input exe_cmd_tlbwr,
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//
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output [31:0] coproc0_output,
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//
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output [5:0] tlbw_index,
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output [49:0] tlbw_value,
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//
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output reg [5:0] tlbr_index,
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input tlb_ram_read_result_ready,
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input [49:0] tlb_ram_read_result,
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//
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input tlbp_update,
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input tlbp_hit,
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input [5:0] tlbp_index,
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//
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output micro_flush_do,
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output reg [5:0] entryhi_asid,
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//
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input sr_cm_set,
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input sr_cm_clear,
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//
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input [5:0] interrupt_vector,
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//
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output exception_start,
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output [31:0] exception_start_pc,
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//
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input mem_stalled,
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input [6:0] mem_cmd,
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input [31:0] mem_instr,
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input [31:0] mem_pc_plus4,
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input [1:0] mem_branched,
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input [31:0] mem_branch_address,
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input [31:0] mem_badvpn
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); /* verilator public_module */
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//------------------------------------------------------------------------------
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reg [5:0] sr_ku_ie; //kernel/user and interrupt enable
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reg sr_bev; //boot exception vector
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reg sr_cm; //last d-cache load hit; used in d-cache isolated
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reg [7:0] sr_im; //interrupt mask
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reg [3:0] sr_coproc_usable; //coprocessor usable
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reg sr_reverse_endian;
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reg sr_tlb_shutdown;
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reg sr_parity_error;
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reg sr_parity_zero;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sr_ku_ie <= 6'b0;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_ku_ie <= exe_b[5:0];
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else if(exe_cmd_rfe) sr_ku_ie <= { sr_ku_ie[5:4], sr_ku_ie[5:2] };
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else if(exception_start) sr_ku_ie <= { sr_ku_ie[3:0], 2'b00 };
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) sr_cm <= `FALSE;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_cm <= exe_b[19];
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else if(sr_cm_clear) sr_cm <= `FALSE; //first sr_cm_clear important
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else if(sr_cm_set) sr_cm <= `TRUE;
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end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) sr_coproc_usable <= 4'b0; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_coproc_usable <= exe_b[31:28]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) sr_reverse_endian <= `FALSE; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_reverse_endian <= exe_b[25]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) sr_bev <= `TRUE; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_bev <= exe_b[22]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) sr_tlb_shutdown <= `FALSE; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_tlb_shutdown <= exe_b[21]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) sr_parity_error <= `FALSE; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_parity_error <= exe_b[20]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) sr_parity_zero <= `FALSE; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_parity_zero <= exe_b[18]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) config_switch_caches <= `FALSE; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) config_switch_caches <= exe_b[17]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) config_isolate_cache <= `FALSE; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) config_isolate_cache <= exe_b[16]; end
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always @(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) sr_im <= 8'h00; else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd12) sr_im <= exe_b[15:8]; end
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assign config_kernel_mode = ~(sr_ku_ie[1]);
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assign config_coproc0_usable = sr_coproc_usable[0];
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assign config_coproc1_usable = sr_coproc_usable[1];
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//------------------------------------------------------------------------------
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reg cause_bd; //branch delay
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reg [1:0] cause_ce; //coproc error
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reg [1:0] cause_ip_writable; //interrupt pending ([1:0] writable)
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reg [4:0] cause_exccode; //exccode
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reg [31:0] epc;
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reg [31:0] badvaddr;
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reg [5:0] interrupt_vector_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) interrupt_vector_reg <= 6'd0;
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else interrupt_vector_reg <= interrupt_vector;
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end
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wire [7:0] cause_ip = { interrupt_vector_reg, cause_ip_writable };
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) cause_bd <= `FALSE;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd13) cause_bd <= exe_b[31];
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else if(exception_start) cause_bd <= (exception_not_interrupt && mem_branched == 2'd2) || (exception_interrupt && mem_branched == 2'd1);
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) cause_ce <= 2'd0;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd13) cause_ce <= exe_b[29:28];
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else if(exception_coprocessor_error) cause_ce <= mem_instr[27:26];
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else if(exception_start) cause_ce <= 2'd0;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) cause_ip_writable <= 2'd0;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd13) cause_ip_writable <= exe_b[9:8];
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else if(exception_start) cause_ip_writable <= 2'd0;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) cause_exccode <= 5'd31;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd13) cause_exccode <= exe_b[6:2];
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else if(exception_start) cause_exccode <= exception_cause;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) epc <= 32'd0;
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else if(exception_start) epc <= exception_epc;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) badvaddr <= 32'd0;
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else if(exception_badvaddr_update) badvaddr <= mem_badvpn;
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end
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//------------------------------------------------------------------------------
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reg tlb_probe;
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reg [5:0] tlb_random;
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reg [10:0] tlb_ptebase;
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reg [18:0] tlb_badvpn;
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reg [19:0] entryhi_vpn;
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reg [19:0] entrylo_pfn;
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reg entrylo_n;
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reg entrylo_d;
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reg entrylo_v;
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reg entrylo_g;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entryhi_vpn <= 20'd0;
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else if(exception_badvaddr_update) entryhi_vpn <= mem_badvpn[31:12];
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd10) entryhi_vpn <= exe_b[31:12];
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else if(tlb_ram_read_result_ready) entryhi_vpn <= tlb_ram_read_result[19:0];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entryhi_asid <= 6'd0;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd10) entryhi_asid <= exe_b[11:6];
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else if(tlb_ram_read_result_ready) entryhi_asid <= tlb_ram_read_result[45:40];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entrylo_pfn <= 20'd0;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd2) entrylo_pfn <= exe_b[31:12];
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else if(tlb_ram_read_result_ready) entrylo_pfn <= tlb_ram_read_result[39:20];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entrylo_n <= `FALSE;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd2) entrylo_n <= exe_b[11];
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else if(tlb_ram_read_result_ready) entrylo_n <= tlb_ram_read_result[46];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entrylo_d <= `FALSE;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd2) entrylo_d <= exe_b[10];
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else if(tlb_ram_read_result_ready) entrylo_d <= tlb_ram_read_result[47];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entrylo_v <= `FALSE;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd2) entrylo_v <= exe_b[9];
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else if(tlb_ram_read_result_ready) entrylo_v <= tlb_ram_read_result[48];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entrylo_g <= `FALSE;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd2) entrylo_g <= exe_b[8];
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else if(tlb_ram_read_result_ready) entrylo_g <= tlb_ram_read_result[49];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) tlb_ptebase <= 11'd0;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd4) tlb_ptebase <= exe_b[31:21];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) tlb_badvpn <= 19'd0;
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else if(exception_badvaddr_update) tlb_badvpn <= mem_badvpn[30:12];
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) tlbr_index <= 6'd0;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd0) tlbr_index <= exe_b[13:8];
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else if(tlbp_update) tlbr_index <= (tlbp_hit)? tlbp_index : 6'd0;
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) tlb_probe <= `FALSE;
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else if(exe_cmd_mtc0 && exe_instr[15:11] == 5'd0) tlb_probe <= exe_b[31];
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else if(tlbp_update) tlb_probe <= ~(tlbp_hit);
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end
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) tlb_random <= 6'd63;
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else if(exe_cmd_tlbwr) tlb_random <= (tlb_random <= 6'd08)? 6'd63 : tlb_random - 6'd1;
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end
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reg [5:0] entryhi_asid_last;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) entryhi_asid_last <= 6'd0;
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else entryhi_asid_last <= entryhi_asid;
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end
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assign micro_flush_do = (entryhi_asid_last != entryhi_asid) || exe_cmd_tlbwi || exe_cmd_tlbwr;
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assign tlbw_index = (exe_cmd_tlbwi)? tlbr_index : tlb_random;
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assign tlbw_value = (tlb_ram_read_result_ready)?
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{ tlb_ram_read_result[49], tlb_ram_read_result[48], tlb_ram_read_result[47], tlb_ram_read_result[46], tlb_ram_read_result[45:40], tlb_ram_read_result[39:20], tlb_ram_read_result[19:0] } :
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{ entrylo_g, entrylo_v, entrylo_d, entrylo_n, entryhi_asid, entrylo_pfn, entryhi_vpn };
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//------------------------------------------------------------------------------
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assign coproc0_output =
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(tlb_ram_read_result_ready && exe_instr[15:11] == 5'd2)?
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{ tlb_ram_read_result[39:20], tlb_ram_read_result[46], tlb_ram_read_result[47], tlb_ram_read_result[48], tlb_ram_read_result[49], 8'd0 } : //entry low just after tlbr
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(tlb_ram_read_result_ready && exe_instr[15:11] == 5'd10)?
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{ tlb_ram_read_result[19:0], tlb_ram_read_result[45:40], 6'd0 } : //entry high just after tlbr
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(exe_instr[15:11] == 5'd0)? { tlb_probe, 17'd0, tlbr_index, 8'd0 } : //tlb index
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(exe_instr[15:11] == 5'd1)? { 18'd0, tlb_random, 8'd0 } : //tlb random
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(exe_instr[15:11] == 5'd2)? { entrylo_pfn, entrylo_n, entrylo_d, entrylo_v, entrylo_g, 8'd0 } : //entry low
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(exe_instr[15:11] == 5'd4)? { tlb_ptebase, tlb_badvpn, 2'b0 } : //tlb context
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(exe_instr[15:11] == 5'd8)? badvaddr : //bad vaddr
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(exe_instr[15:11] == 5'd10)? { entryhi_vpn, entryhi_asid, 6'd0 } : //entry high
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(exe_instr[15:11] == 5'd12)? { sr_coproc_usable, 2'b0, sr_reverse_endian, 2'b0, sr_bev, sr_tlb_shutdown, sr_parity_error, sr_cm, sr_parity_zero,
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271 |
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config_switch_caches, config_isolate_cache, sr_im, 2'b0, sr_ku_ie } : //SR
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272 |
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(exe_instr[15:11] == 5'd13)? { cause_bd, 1'b0, cause_ce, 12'd0, cause_ip, 1'b0, cause_exccode, 2'b0 } : //cause
|
273 |
|
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(exe_instr[15:11] == 5'd14)? epc : //epc
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274 |
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(exe_instr[15:11] == 5'd15)? { 16'd0, 8'h02, 8'h30 } : //PRId
|
275 |
|
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32'd0;
|
276 |
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|
277 |
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//------------------------------------------------------------------------------
|
278 |
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|
279 |
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//input [6:0] mem_cmd,
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280 |
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|
//input mem_branched,
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281 |
|
|
//input [31:0] mem_badvpn
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282 |
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|
283 |
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|
reg mem_stalled_last;
|
284 |
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always @(posedge clk or negedge rst_n) begin
|
285 |
|
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if(rst_n == 1'b0) mem_stalled_last <= `FALSE;
|
286 |
|
|
else mem_stalled_last <= mem_stalled;
|
287 |
|
|
end
|
288 |
|
|
|
289 |
|
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wire exception_interrupt = sr_ku_ie[0] && (cause_ip & sr_im) != 8'd0 && (mem_cmd != `CMD_null || (mem_stalled_last && ~(mem_stalled))) && ~(exception_not_interrupt) && ~(mem_stalled);
|
290 |
|
|
wire exception_badvaddr_update = mem_cmd == `CMD_exc_load_tlb || mem_cmd == `CMD_exc_store_tlb || mem_cmd == `CMD_exc_tlb_load_miss || mem_cmd == `CMD_exc_tlb_store_miss || mem_cmd == `CMD_exc_tlb_modif;
|
291 |
|
|
wire exception_coprocessor_error = mem_cmd == `CMD_exc_coproc_unusable;
|
292 |
|
|
|
293 |
|
|
wire exception_not_interrupt = exception_coprocessor_error || exception_badvaddr_update || mem_cmd == `CMD_exc_int_overflow || mem_cmd == `CMD_break || mem_cmd == `CMD_syscall ||
|
294 |
|
|
mem_cmd == `CMD_exc_load_addr_err || mem_cmd == `CMD_exc_store_addr_err || mem_cmd == `CMD_exc_reserved_instr;
|
295 |
|
|
|
296 |
|
|
assign exception_start = exception_not_interrupt || exception_interrupt;
|
297 |
|
|
|
298 |
|
|
wire [31:0] exception_epc =
|
299 |
|
|
(exception_interrupt && mem_branched == 2'd2)? mem_branch_address :
|
300 |
|
|
(exception_interrupt && mem_branched == 2'd0)? mem_pc_plus4 :
|
301 |
|
|
(mem_branched == 2'd2)? mem_pc_plus4 - 32'd8 :
|
302 |
|
|
mem_pc_plus4 - 32'd4;
|
303 |
|
|
|
304 |
|
|
wire [4:0] exception_cause =
|
305 |
|
|
(mem_cmd == `CMD_exc_tlb_modif)? 5'd1 :
|
306 |
|
|
(mem_cmd == `CMD_exc_load_tlb || mem_cmd == `CMD_exc_tlb_load_miss)? 5'd2 :
|
307 |
|
|
(mem_cmd == `CMD_exc_store_tlb || mem_cmd == `CMD_exc_tlb_store_miss)? 5'd3 :
|
308 |
|
|
(mem_cmd == `CMD_exc_load_addr_err)? 5'd4 :
|
309 |
|
|
(mem_cmd == `CMD_exc_store_addr_err)? 5'd5 :
|
310 |
|
|
(mem_cmd == `CMD_syscall)? 5'd8 :
|
311 |
|
|
(mem_cmd == `CMD_break)? 5'd9 :
|
312 |
|
|
(mem_cmd == `CMD_exc_reserved_instr)? 5'd10 :
|
313 |
|
|
(mem_cmd == `CMD_exc_coproc_unusable)? 5'd11 :
|
314 |
|
|
(mem_cmd == `CMD_exc_int_overflow)? 5'd12 :
|
315 |
|
|
5'd0; //interrupt
|
316 |
|
|
|
317 |
|
|
assign exception_start_pc =
|
318 |
|
|
(sr_bev && (mem_cmd == `CMD_exc_tlb_load_miss || mem_cmd == `CMD_exc_tlb_store_miss))? 32'hBFC00100 :
|
319 |
|
|
(mem_cmd == `CMD_exc_tlb_load_miss || mem_cmd == `CMD_exc_tlb_store_miss)? 32'h80000000 :
|
320 |
|
|
(sr_bev)? 32'hBFC00180 :
|
321 |
|
|
32'h80000080;
|
322 |
|
|
|
323 |
|
|
//------------------------------------------------------------------------------
|
324 |
|
|
// synthesis translate_off
|
325 |
|
|
wire _unused_ok = &{ 1'b0, exe_instr[31:16], exe_instr[10:0], exe_cmd_tlbr, exe_cmd_tlbwr, mem_instr[31:28], mem_instr[25:0], 1'b0 };
|
326 |
|
|
// synthesis translate_on
|
327 |
|
|
//------------------------------------------------------------------------------
|
328 |
|
|
|
329 |
|
|
endmodule
|