1 |
2 |
alfik |
/*
|
2 |
|
|
* This file is subject to the terms and conditions of the BSD License. See
|
3 |
|
|
* the file "LICENSE" in the main directory of this archive for more details.
|
4 |
|
|
*
|
5 |
|
|
* Copyright (C) 2014 Aleksander Osman
|
6 |
|
|
*/
|
7 |
|
|
|
8 |
|
|
module block_long_div(
|
9 |
|
|
input clk,
|
10 |
|
|
input rst_n,
|
11 |
|
|
|
12 |
|
|
input start,
|
13 |
|
|
input [32:0] dividend,
|
14 |
|
|
input [32:0] divisor,
|
15 |
|
|
|
16 |
|
|
output ready,
|
17 |
|
|
output [31:0] quotient,
|
18 |
|
|
output [31:0] remainder
|
19 |
|
|
);
|
20 |
|
|
|
21 |
|
|
//------------------------------------------------------------------------------
|
22 |
|
|
|
23 |
|
|
reg [5:0] div_counter;
|
24 |
|
|
always @(posedge clk or negedge rst_n) begin
|
25 |
|
|
if(rst_n == 1'b0) div_counter <= 6'd0;
|
26 |
|
|
else if(start) div_counter <= 6'd33;
|
27 |
|
|
else if(div_counter != 6'd0) div_counter <= div_counter - 6'd1;
|
28 |
|
|
end
|
29 |
|
|
|
30 |
|
|
wire div_working = div_counter > 6'd1;
|
31 |
|
|
|
32 |
|
|
wire [64:0] div_diff = { 32'd0, div_dividend } - div_divisor;
|
33 |
|
|
|
34 |
|
|
reg [31:0] div_dividend;
|
35 |
|
|
always @(posedge clk or negedge rst_n) begin
|
36 |
|
|
if(rst_n == 1'b0) div_dividend <= 32'd0;
|
37 |
|
|
else if(start && dividend[32] == 1'b0) div_dividend <= dividend[31:0];
|
38 |
|
|
else if(start && dividend[32] == 1'b1) div_dividend <= -dividend[31:0];
|
39 |
|
|
else if(div_working && div_diff[64] == 1'b0) div_dividend <= div_diff[31:0];
|
40 |
|
|
end
|
41 |
|
|
|
42 |
|
|
wire [32:0] divisor_neg = -divisor;
|
43 |
|
|
|
44 |
|
|
reg [63:0] div_divisor;
|
45 |
|
|
always @(posedge clk or negedge rst_n) begin
|
46 |
|
|
if(rst_n == 1'b0) div_divisor <= 64'd0;
|
47 |
|
|
else if(start && divisor[32] == 1'b0) div_divisor <= { 1'b0, divisor[31:0], 31'd0 };
|
48 |
|
|
else if(start && divisor[32] == 1'b1) div_divisor <= { 1'b0, divisor_neg[31:0], 31'd0 };
|
49 |
|
|
else if(div_working) div_divisor <= { 1'b0, div_divisor[63:1] };
|
50 |
|
|
end
|
51 |
|
|
|
52 |
|
|
reg [31:0] div_quotient;
|
53 |
|
|
always @(posedge clk or negedge rst_n) begin
|
54 |
|
|
if(rst_n == 1'b0) div_quotient <= 32'd0;
|
55 |
|
|
else if(start) div_quotient <= 32'd0;
|
56 |
|
|
else if(div_working && div_diff[64] == 1'b0) div_quotient <= { div_quotient[30:0], 1'b1 };
|
57 |
|
|
else if(div_working && div_diff[64] == 1'b1) div_quotient <= { div_quotient[30:0], 1'b0 };
|
58 |
|
|
end
|
59 |
|
|
|
60 |
|
|
reg div_quotient_neg;
|
61 |
|
|
always @(posedge clk or negedge rst_n) begin
|
62 |
|
|
if(rst_n == 1'b0) div_quotient_neg <= 1'b0;
|
63 |
|
|
else if(start) div_quotient_neg <= dividend[32] ^ divisor[32];
|
64 |
|
|
end
|
65 |
|
|
|
66 |
|
|
reg div_remainder_neg;
|
67 |
|
|
always @(posedge clk or negedge rst_n) begin
|
68 |
|
|
if(rst_n == 1'b0) div_remainder_neg <= 1'b0;
|
69 |
|
|
else if(start) div_remainder_neg <= dividend[32];
|
70 |
|
|
end
|
71 |
|
|
|
72 |
|
|
assign ready = div_counter == 6'd1;
|
73 |
|
|
assign quotient = (div_quotient_neg)? -div_quotient[31:0] : div_quotient[31:0];
|
74 |
|
|
assign remainder = (div_remainder_neg)? -div_dividend[31:0] : div_dividend[31:0];
|
75 |
|
|
|
76 |
|
|
//------------------------------------------------------------------------------
|
77 |
|
|
// synthesis translate_off
|
78 |
|
|
wire _unused_ok = &{ 1'b0, div_diff[63:32], divisor_neg[32], 1'b0 };
|
79 |
|
|
// synthesis translate_on
|
80 |
|
|
//------------------------------------------------------------------------------
|
81 |
|
|
|
82 |
|
|
endmodule
|