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alfik |
/*
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* This file is subject to the terms and conditions of the BSD License. See
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* the file "LICENSE" in the main directory of this archive for more details.
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*
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* Copyright (C) 2014 Aleksander Osman
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*/
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module block_long_div(
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input clk,
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input rst_n,
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input start,
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input [32:0] dividend,
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input [32:0] divisor,
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output ready,
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output [31:0] quotient,
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output [31:0] remainder
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);
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//------------------------------------------------------------------------------
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reg [5:0] div_counter;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) div_counter <= 6'd0;
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else if(start) div_counter <= 6'd33;
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else if(div_counter != 6'd0) div_counter <= div_counter - 6'd1;
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end
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wire div_working = div_counter > 6'd1;
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wire [64:0] div_diff = { 32'd0, div_dividend } - div_divisor;
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reg [31:0] div_dividend;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) div_dividend <= 32'd0;
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else if(start && dividend[32] == 1'b0) div_dividend <= dividend[31:0];
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else if(start && dividend[32] == 1'b1) div_dividend <= -dividend[31:0];
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else if(div_working && div_diff[64] == 1'b0) div_dividend <= div_diff[31:0];
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end
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wire [32:0] divisor_neg = -divisor;
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reg [63:0] div_divisor;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) div_divisor <= 64'd0;
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else if(start && divisor[32] == 1'b0) div_divisor <= { 1'b0, divisor[31:0], 31'd0 };
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else if(start && divisor[32] == 1'b1) div_divisor <= { 1'b0, divisor_neg[31:0], 31'd0 };
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else if(div_working) div_divisor <= { 1'b0, div_divisor[63:1] };
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end
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reg [31:0] div_quotient;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) div_quotient <= 32'd0;
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else if(start) div_quotient <= 32'd0;
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else if(div_working && div_diff[64] == 1'b0) div_quotient <= { div_quotient[30:0], 1'b1 };
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else if(div_working && div_diff[64] == 1'b1) div_quotient <= { div_quotient[30:0], 1'b0 };
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end
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reg div_quotient_neg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) div_quotient_neg <= 1'b0;
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else if(start) div_quotient_neg <= dividend[32] ^ divisor[32];
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end
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reg div_remainder_neg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) div_remainder_neg <= 1'b0;
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else if(start) div_remainder_neg <= dividend[32];
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end
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assign ready = div_counter == 6'd1;
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assign quotient = (div_quotient_neg)? -div_quotient[31:0] : div_quotient[31:0];
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assign remainder = (div_remainder_neg)? -div_dividend[31:0] : div_dividend[31:0];
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//------------------------------------------------------------------------------
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// synthesis translate_off
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wire _unused_ok = &{ 1'b0, div_diff[63:32], divisor_neg[32], 1'b0 };
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// synthesis translate_on
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//------------------------------------------------------------------------------
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endmodule
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