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/*
 * This file is subject to the terms and conditions of the BSD License. See
 * the file "LICENSE" in the main directory of this archive for more details.
 *
 * Copyright (C) 2014 Aleksander Osman
 */
 
module model_fifo(
    input                       clk,
    input                       rst_n,
    input                       sclr,
 
    input                       rdreq,
    input                       wrreq,
    input       [width-1:0]     data,
 
    output                      empty,
    output reg                  full,
    output      [width-1:0]     q,
    output reg  [widthu-1:0]    usedw
);
 
parameter width     = 2;
parameter widthu    = 2;
 
reg [width-1:0] mem [(2**widthu)-1:0];
 
reg [widthu-1:0] rd_index = 0;
reg [widthu-1:0] wr_index = 0;
 
assign q    = mem[rd_index];
assign empty= usedw == 0 && ~(full);
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)           rd_index <= 0;
    else if(sclr)               rd_index <= 0;
    else if(rdreq && ~(empty))  rd_index <= rd_index + { {widthu-1{1'b0}}, 1'b1 };
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                       wr_index <= 0;
    else if(sclr)                           wr_index <= 0;
    else if(wrreq && (~(full) || rdreq))    wr_index <= wr_index + { {widthu-1{1'b0}}, 1'b1 };
end
 
always @(posedge clk) begin
    if(wrreq && (~(full) || rdreq)) mem[wr_index] <= data;
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                                               full <= 1'b0;
    else if(sclr)                                                   full <= 1'b0;
    else if(rdreq && ~(wrreq) && full)                              full <= 1'b0;
    else if(~(rdreq) && wrreq && ~(full) && usedw == (2**widthu)-1) full <= 1'b1;
end
 
always @(posedge clk or negedge rst_n) begin
    if(rst_n == 1'b0)                       usedw <= 0;
    else if(sclr)                           usedw <= 0;
    else if(rdreq && ~(wrreq) && ~(empty))  usedw <= usedw - { {widthu-1{1'b0}}, 1'b1 };
    else if(~(rdreq) && wrreq && ~(full))   usedw <= usedw + { {widthu-1{1'b0}}, 1'b1 };
    else if(rdreq && wrreq && empty)        usedw <= { {widthu-1{1'b0}}, 1'b1 };
end
 
endmodule

Line No.	Rev	Author	Line
1	2	alfik	`/*`
2			`* This file is subject to the terms and conditions of the BSD License. See`
3			`* the file "LICENSE" in the main directory of this archive for more details.`
4			`*`
5			`* Copyright (C) 2014 Aleksander Osman`
6			`*/`
7
8			`module model_fifo(`
9			`input clk,`
10			`input rst_n,`
11			`input sclr,`
12
13			`input rdreq,`
14			`input wrreq,`
15			`input [width-1:0] data,`
16
17			`output empty,`
18			`output reg full,`
19			`output [width-1:0] q,`
20			`output reg [widthu-1:0] usedw`
21			`);`
22
23			`parameter width = 2;`
24			`parameter widthu = 2;`
25
26			`reg [width-1:0] mem [(2**widthu)-1:0];`
27
28			`reg [widthu-1:0] rd_index = 0;`
29			`reg [widthu-1:0] wr_index = 0;`
30
31			`assign q = mem[rd_index];`
32			`assign empty= usedw == 0 && ~(full);`
33
34			`always @(posedge clk or negedge rst_n) begin`
35			`if(rst_n == 1'b0) rd_index <= 0;`
36			`else if(sclr) rd_index <= 0;`
37			`else if(rdreq && ~(empty)) rd_index <= rd_index + { {widthu-1{1'b0}}, 1'b1 };`
38			`end`
39
40			`always @(posedge clk or negedge rst_n) begin`
41			`if(rst_n == 1'b0) wr_index <= 0;`
42			`else if(sclr) wr_index <= 0;`
43			`else if(wrreq && (~(full) \|\| rdreq)) wr_index <= wr_index + { {widthu-1{1'b0}}, 1'b1 };`
44			`end`
45
46			`always @(posedge clk) begin`
47			`if(wrreq && (~(full) \|\| rdreq)) mem[wr_index] <= data;`
48			`end`
49
50			`always @(posedge clk or negedge rst_n) begin`
51			`if(rst_n == 1'b0) full <= 1'b0;`
52			`else if(sclr) full <= 1'b0;`
53			`else if(rdreq && ~(wrreq) && full) full <= 1'b0;`
54			`else if(~(rdreq) && wrreq && ~(full) && usedw == (2**widthu)-1) full <= 1'b1;`
55			`end`
56
57			`always @(posedge clk or negedge rst_n) begin`
58			`if(rst_n == 1'b0) usedw <= 0;`
59			`else if(sclr) usedw <= 0;`
60			`else if(rdreq && ~(wrreq) && ~(empty)) usedw <= usedw - { {widthu-1{1'b0}}, 1'b1 };`
61			`else if(~(rdreq) && wrreq && ~(full)) usedw <= usedw + { {widthu-1{1'b0}}, 1'b1 };`
62			`else if(rdreq && wrreq && empty) usedw <= { {widthu-1{1'b0}}, 1'b1 };`
63			`end`
64
65			`endmodule`

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[/] [aor3000/] [trunk/] [rtl/] [model/] [model_fifo.v] - Blame information for rev 2