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alfik |
/*
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* This file is subject to the terms and conditions of the BSD License. See
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* the file "LICENSE" in the main directory of this archive for more details.
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*
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* Copyright (C) 2014 Aleksander Osman
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*/
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`include "defines.v"
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module pipeline_mem(
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input clk,
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input rst_n,
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//
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input [5:0] interrupt_vector,
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//
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output mem_stall,
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//
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output config_kernel_mode,
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output config_switch_caches,
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//
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input [6:0] exe_cmd,
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input [31:0] exe_instr,
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input [31:0] exe_pc_plus4,
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input exe_pc_user_seg,
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input [31:0] exe_badvpn,
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input [31:0] exe_a,
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input [31:0] exe_b,
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input [1:0] exe_branched,
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input [31:0] exe_branch_address,
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input exe_cmd_cp0,
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input exe_cmd_load,
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input exe_cmd_store,
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//
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input [4:0] exe_result_index,
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input [31:0] exe_result,
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//
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output reg [4:0] mem_result_index,
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output [31:0] mem_result,
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//
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output [4:0] muldiv_result_index,
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output [31:0] muldiv_result,
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//
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output tlb_ram_read_do,
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output [5:0] tlb_ram_read_index,
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input tlb_ram_read_result_ready,
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input [49:0] tlb_ram_read_result,
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//
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output tlb_ram_write_do,
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output [5:0] tlb_ram_write_index,
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output [49:0] tlb_ram_write_value,
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//
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output tlb_ram_data_start,
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output [19:0] tlb_ram_data_vpn,
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input tlb_ram_data_hit,
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input [5:0] tlb_ram_data_index,
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input [49:0] tlb_ram_data_result,
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input tlb_ram_data_missed,
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//
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output exception_start,
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output [31:0] exception_start_pc,
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//
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output micro_flush_do,
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output [5:0] entryhi_asid,
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//
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input [31:0] data_address_next,
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input [31:0] data_address,
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//
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output [8:0] data_cache_read_address,
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input [53:0] data_cache_q,
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output [8:0] data_cache_write_address,
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output data_cache_write_enable,
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output [53:0] data_cache_data,
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//
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output ram_fifo_wrreq,
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output [66:0] ram_fifo_data,
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input ram_fifo_full,
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//
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input [31:0] ram_result_address,
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input ram_result_valid,
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input ram_result_is_read_instr,
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input [2:0] ram_result_burstcount,
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input [31:0] ram_result
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); /* verilator public_module */
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//------------------------------------------------------------------------------ pipeline stall
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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assign mem_stall = ~(exception_start) && (
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muldiv_busy ||
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exe_cmd_tlbp || (tlbp_in_progress && ~(tlbp_update)) ||
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load_idle_tlb_ok_cache_bad_fifo_ok || load_idle_tlb_ok_cache_bad_fifo_bad || load_idle_tlb_wait || load_state != LOAD_IDLE ||
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store_idle_tlb_ok_fifo_bad || store_idle_tlb_wait || store_state != STORE_IDLE
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);
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reg mem_stalled;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_stalled <= `FALSE;
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else mem_stalled <= mem_stall;
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end
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//------------------------------------------------------------------------------ instruction decoding
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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wire [4:0] exe_instr_rt = exe_instr[20:16];
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wire [4:0] exe_instr_rd = exe_instr[15:11];
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wire mem_exc_coproc0_unusable = ~(config_coproc0_usable) && ~(config_kernel_mode) && exe_cmd_cp0;
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wire exe_cmd_mtc0 = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_mtc0;
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wire exe_cmd_rfe = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_rfe;
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wire exe_cmd_tlbr = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbr;
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wire exe_cmd_tlbp = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbp;
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wire exe_cmd_tlbwi = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbwi;
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wire exe_cmd_tlbwr = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbwr;
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wire exe_cmd_load_do = ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd_load;
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wire exe_cmd_store_do = ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd_store;
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//------------------------------------------------------------------------------ next pipeline stage
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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reg config_kernel_mode_last;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) config_kernel_mode_last <= `TRUE;
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else config_kernel_mode_last <= config_kernel_mode;
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end
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reg config_kernel_mode_changed;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) config_kernel_mode_changed <= `FALSE;
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else if(config_kernel_mode) config_kernel_mode_changed <= `FALSE;
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else if(config_kernel_mode_exc_wait) config_kernel_mode_changed <= `TRUE;
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else if(exe_cmd != `CMD_null) config_kernel_mode_changed <= `FALSE;
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end
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wire config_kernel_mode_exc_now = (config_kernel_mode_changed || (config_kernel_mode_last && ~(config_kernel_mode))) && exe_cmd != `CMD_null && exe_pc_user_seg;
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wire config_kernel_mode_exc_wait = ~(config_kernel_mode_changed) && config_kernel_mode_last && ~(config_kernel_mode) && exe_cmd == `CMD_null;
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//------------------------------------------------------------------------------
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wire [4:0] mem_result_index_next =
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(exception_start || config_kernel_mode_exc_now)? 5'd0 :
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(exe_cmd == `CMD_cfc1_detect && config_coproc1_usable)? exe_instr_rt :
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(data_finished && load_idle_tlb_ok_finished)? exe_instr_rt :
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(data_finished)? load_instr_rt_reg :
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(muldiv_result_index != 5'd0)? muldiv_result_index :
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(exe_cmd == `CMD_mfc0 && ~(mem_exc_coproc0_unusable))? exe_instr_rt :
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exe_result_index;
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wire [31:0] mem_result_next =
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(exe_cmd == `CMD_cfc1_detect && config_coproc1_usable)? 32'd0 :
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(muldiv_result_index != 5'd0)? muldiv_result :
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(exe_cmd == `CMD_mfc0 && ~(mem_exc_coproc0_unusable))? coproc0_output :
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exe_result;
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wire [6:0] mem_cmd_next =
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(exception_start)? `CMD_null :
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(config_kernel_mode_exc_now)? `CMD_exc_load_addr_err :
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(exe_cmd == `CMD_cfc1_detect && ~(config_coproc1_usable))? `CMD_exc_coproc_unusable :
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(mem_exc_coproc0_unusable)? `CMD_exc_coproc_unusable :
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(store_idle_tlb_bad_exc_modif || store_tlb_tlb_bad_exc_modif)? `CMD_exc_tlb_modif :
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(load_idle_tlb_bad_exc_inv || load_tlb_tlb_bad_exc_inv || (load_tlb_tlb_bad_exc_miss && data_address_reg[31] == 1'b1))? `CMD_exc_load_tlb :
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(store_idle_tlb_bad_exc_inv || store_tlb_tlb_bad_exc_inv || (store_tlb_tlb_bad_exc_miss && data_address_reg[31] == 1'b1))? `CMD_exc_store_tlb :
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(load_tlb_tlb_bad_exc_miss && data_address_reg[31] == 1'b0)? `CMD_exc_tlb_load_miss :
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(store_tlb_tlb_bad_exc_miss && data_address_reg[31] == 1'b0)? `CMD_exc_tlb_store_miss :
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exe_cmd;
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wire [31:0] mem_badvpn_next =
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(exe_cmd_load_do || exe_cmd_store_do)? { data_address[31:2], ((exe_instr[27:26] == 2'b10)? 2'b00 : data_address[1:0]) } :
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(load_state != LOAD_IDLE || store_state != STORE_IDLE)? { data_address_reg[31:2], ((mem_left_right == 2'b10)? 2'b00 : data_address_reg[1:0]) } :
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exe_badvpn;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_result_index <= 5'd0;
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else mem_result_index <= mem_result_index_next;
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end
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reg [31:0] mem_result_nodata;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_result_nodata <= 32'd0;
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else mem_result_nodata <= mem_result_next;
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end
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reg [31:0] mem_result_data;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_result_data <= 32'd0;
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else mem_result_data <= data_finished_value;
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end
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reg mem_data_finished;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_data_finished <= `FALSE;
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else mem_data_finished <= data_finished;
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end
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assign mem_result = (mem_data_finished)? mem_result_data : mem_result_nodata;
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//------------------------------------------------------------------------------
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reg [6:0] mem_cmd;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_cmd <= `CMD_null;
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else mem_cmd <= mem_cmd_next;
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end
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reg [31:0] mem_branch_address;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_branch_address <= 32'd0;
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else mem_branch_address <= exe_branch_address;
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end
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reg [31:0] mem_instr;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_instr <= 32'd0;
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else mem_instr <= exe_instr;
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end
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reg [31:0] mem_badvpn;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_badvpn <= 32'd0;
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else mem_badvpn <= mem_badvpn_next;
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end
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reg [1:0] mem_branched;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_branched <= 2'd0;
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else if(~(mem_stalled)) mem_branched <= exe_branched;
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end
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reg [31:0] mem_pc_plus4;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) mem_pc_plus4 <= 32'd0;
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else if(~(mem_stalled)) mem_pc_plus4 <= exe_pc_plus4;
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end
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//------------------------------------------------------------------------------ tlb
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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//input tlb_ram_data_hit,
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//input [5:0] tlb_ram_data_index,
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//input [49:0] tlb_ram_data_result,
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//input tlb_ram_data_missed
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assign tlb_ram_write_do = exe_cmd_tlbwi || exe_cmd_tlbwr;
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assign tlb_ram_write_index = tlbw_index;
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assign tlb_ram_write_value = tlbw_value;
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assign tlb_ram_read_do = exe_cmd_tlbr;
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assign tlb_ram_read_index = tlbr_index;
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assign tlb_ram_data_start = exe_cmd_tlbp || exe_cmd_load_do || exe_cmd_store_do;
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assign tlb_ram_data_vpn =
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(exe_cmd_tlbp || tlbp_in_progress)? tlbw_value[19:0] :
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(exe_cmd_load_do || exe_cmd_store_do)? data_address[31:12] :
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data_address_reg[31:12];
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//------------------------------------------------------------------------------ tlb probe
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281 |
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reg tlbp_in_progress;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) tlbp_in_progress <= `FALSE;
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else if(exe_cmd_tlbp) tlbp_in_progress <= `TRUE;
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else if(tlbp_update) tlbp_in_progress <= `FALSE;
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end
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wire tlbp_update = tlbp_in_progress && (tlb_ram_data_hit || tlb_ram_data_missed);
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wire tlbp_hit = tlb_ram_data_hit;
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wire [5:0] tlbp_index = tlb_ram_data_index;
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//------------------------------------------------------------------------------ load / store common
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293 |
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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wire tlb_use_at_idle = (exe_cmd_load_do || exe_cmd_store_do) && (data_address[31] == 1'b0 || data_address[31:30] == 2'b11);
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wire [19:0] pfn_at_idle =
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(~(tlb_use_at_idle))? { 3'b0, data_address[28:12] } :
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(micro_check_matched)? micro_check_result[39:20] :
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tlb_ram_data_result[39:20];
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reg [19:0] pfn_reg;
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always @(posedge clk or negedge rst_n) begin
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if(rst_n == 1'b0) pfn_reg <= 20'd0;
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|
|
else if(exe_cmd_load_do || exe_cmd_store_do) pfn_reg <= pfn_at_idle;
|
307 |
|
|
else if(load_tlb_tlb_ok_cache_bad || store_tlb_tlb_ok) pfn_reg <= tlb_ram_data_result[39:20];
|
308 |
|
|
end
|
309 |
|
|
|
310 |
|
|
wire n_at_idle =
|
311 |
|
|
(~(tlb_use_at_idle))? data_address[31:29] == 3'b101 :
|
312 |
|
|
(micro_check_matched)? micro_check_result[46] :
|
313 |
|
|
tlb_ram_data_result[46];
|
314 |
|
|
|
315 |
|
|
reg n_reg;
|
316 |
|
|
always @(posedge clk or negedge rst_n) begin
|
317 |
|
|
if(rst_n == 1'b0) n_reg <= `FALSE;
|
318 |
|
|
else if(exe_cmd_load_do || exe_cmd_store_do) n_reg <= n_at_idle;
|
319 |
|
|
else if(load_tlb_tlb_ok_cache_bad || store_tlb_tlb_ok) n_reg <= tlb_ram_data_result[46];
|
320 |
|
|
end
|
321 |
|
|
|
322 |
|
|
wire [3:0] byte_byteenable =
|
323 |
|
|
(data_address[1:0] == 2'b00)? 4'b0001 :
|
324 |
|
|
(data_address[1:0] == 2'b01)? 4'b0010 :
|
325 |
|
|
(data_address[1:0] == 2'b10)? 4'b0100 :
|
326 |
|
|
4'b1000;
|
327 |
|
|
wire [3:0] halfword_byteenable =
|
328 |
|
|
(data_address[1:0] == 2'b00)? 4'b0011 :
|
329 |
|
|
4'b1100;
|
330 |
|
|
wire [3:0] lwl_byteenable =
|
331 |
|
|
(data_address[1:0] == 2'b00)? 4'b0001 :
|
332 |
|
|
(data_address[1:0] == 2'b01)? 4'b0011 :
|
333 |
|
|
(data_address[1:0] == 2'b10)? 4'b0111 :
|
334 |
|
|
4'b1111;
|
335 |
|
|
wire [3:0] lwr_byteenable =
|
336 |
|
|
(data_address[1:0] == 2'b00)? 4'b1111 :
|
337 |
|
|
(data_address[1:0] == 2'b01)? 4'b1110 :
|
338 |
|
|
(data_address[1:0] == 2'b10)? 4'b1100 :
|
339 |
|
|
4'b1000;
|
340 |
|
|
wire [3:0] data_byteenable =
|
341 |
|
|
(load_idle_cmd_lb || load_idle_cmd_lbu || load_idle_cmd_sb)? byte_byteenable :
|
342 |
|
|
(load_idle_cmd_lh || load_idle_cmd_lhu || load_idle_cmd_sh)? halfword_byteenable :
|
343 |
|
|
(load_idle_cmd_lwl || load_idle_cmd_swl)? lwl_byteenable :
|
344 |
|
|
(load_idle_cmd_lwr || load_idle_cmd_swr)? lwr_byteenable :
|
345 |
|
|
4'b1111;
|
346 |
|
|
|
347 |
|
|
reg [3:0] data_byteenable_reg;
|
348 |
|
|
always @(posedge clk or negedge rst_n) begin
|
349 |
|
|
if(rst_n == 1'b0) data_byteenable_reg <= 4'b0;
|
350 |
|
|
else if(exe_cmd_load_do) data_byteenable_reg <= load_idle_byteenable;
|
351 |
|
|
else if(exe_cmd_store_do) data_byteenable_reg <= data_byteenable;
|
352 |
|
|
end
|
353 |
|
|
|
354 |
|
|
reg [53:0] data_cache_q_reg;
|
355 |
|
|
always @(posedge clk or negedge rst_n) begin
|
356 |
|
|
if(rst_n == 1'b0) data_cache_q_reg <= 54'd0;
|
357 |
|
|
else if(exe_cmd_load_do) data_cache_q_reg <= data_cache_q;
|
358 |
|
|
else if(exe_cmd_store_do) data_cache_q_reg <= { data_cache_q[53:32], store_idle_data };
|
359 |
|
|
end
|
360 |
|
|
|
361 |
|
|
reg [31:0] data_address_reg;
|
362 |
|
|
always @(posedge clk or negedge rst_n) begin
|
363 |
|
|
if(rst_n == 1'b0) data_address_reg <= 32'b0;
|
364 |
|
|
else if(exe_cmd_load_do || exe_cmd_store_do) data_address_reg <= data_address;
|
365 |
|
|
end
|
366 |
|
|
|
367 |
|
|
reg [1:0] mem_left_right;
|
368 |
|
|
always @(posedge clk or negedge rst_n) begin
|
369 |
|
|
if(rst_n == 1'b0) mem_left_right <= 2'b0;
|
370 |
|
|
else if(exe_cmd_load_do || exe_cmd_store_do) mem_left_right <= exe_instr[27:26];
|
371 |
|
|
end
|
372 |
|
|
|
373 |
|
|
//------------------------------------------------------------------------------ load
|
374 |
|
|
//------------------------------------------------------------------------------
|
375 |
|
|
//------------------------------------------------------------------------------
|
376 |
|
|
|
377 |
|
|
localparam [1:0] LOAD_IDLE = 2'd0;
|
378 |
|
|
localparam [1:0] LOAD_TLB = 2'd1;
|
379 |
|
|
localparam [1:0] LOAD_FIFO = 2'd2;
|
380 |
|
|
localparam [1:0] LOAD_RESULT = 2'd3;
|
381 |
|
|
|
382 |
|
|
reg [1:0] load_state;
|
383 |
|
|
always @(posedge clk or negedge rst_n) begin
|
384 |
|
|
if(rst_n == 1'b0) load_state <= LOAD_IDLE;
|
385 |
|
|
else if(load_idle_tlb_ok_cache_bad_fifo_ok) load_state <= LOAD_RESULT;
|
386 |
|
|
else if(load_idle_tlb_ok_cache_bad_fifo_bad) load_state <= LOAD_FIFO;
|
387 |
|
|
else if(load_idle_tlb_wait) load_state <= LOAD_TLB;
|
388 |
|
|
else if(load_tlb_tlb_ok_finished) load_state <= LOAD_IDLE;
|
389 |
|
|
else if(load_tlb_tlb_bad_exc_inv || load_tlb_tlb_bad_exc_miss) load_state <= LOAD_IDLE;
|
390 |
|
|
else if(load_tlb_tlb_ok_cache_bad_fifo_ok) load_state <= LOAD_RESULT;
|
391 |
|
|
else if(load_tlb_tlb_ok_cache_bad_fifo_bad) load_state <= LOAD_FIFO;
|
392 |
|
|
else if(load_fifo_end) load_state <= LOAD_RESULT;
|
393 |
|
|
else if(load_state == LOAD_RESULT && ram_result_valid && ~(ram_result_is_read_instr) && ram_result_burstcount == 3'd1) load_state <= LOAD_IDLE;
|
394 |
|
|
end
|
395 |
|
|
|
396 |
|
|
wire sr_cm_clear = config_isolate_cache && (load_idle_tlb_ok_cache_ok || load_tlb_tlb_ok_cache_ok);
|
397 |
|
|
wire sr_cm_set = config_isolate_cache && (load_idle_tlb_ok_cache_isolate || load_tlb_tlb_ok_cache_isolate);
|
398 |
|
|
|
399 |
|
|
wire data_finished = load_idle_tlb_ok_finished || load_tlb_tlb_ok_finished || (ram_result_valid && ~(ram_result_is_read_instr) && ram_result_address[31:2] == { pfn_reg, data_address_reg[11:2] });
|
400 |
|
|
wire [31:0] data_finished_value = (load_idle_tlb_ok_finished)? load_idle_result[31:0] : load_result_value;
|
401 |
|
|
|
402 |
|
|
//------------------------------------------------------------------------------ state IDLE
|
403 |
|
|
|
404 |
|
|
wire load_idle_cmd_lb = exe_instr[28:26] == 3'b000;
|
405 |
|
|
wire load_idle_cmd_lbu = exe_instr[28:26] == 3'b100;
|
406 |
|
|
wire load_idle_cmd_lh = exe_instr[28:26] == 3'b001;
|
407 |
|
|
wire load_idle_cmd_lhu = exe_instr[28:26] == 3'b101;
|
408 |
|
|
wire load_idle_cmd_lw = exe_instr[28:26] == 3'b011;
|
409 |
|
|
wire load_idle_cmd_lwl = exe_instr[28:26] == 3'b010;
|
410 |
|
|
wire load_idle_cmd_lwr = exe_instr[28:26] == 3'b110;
|
411 |
|
|
|
412 |
|
|
wire load_idle_cmd_sb = exe_instr[28:26] == 3'b000;
|
413 |
|
|
wire load_idle_cmd_sh = exe_instr[28:26] == 3'b001;
|
414 |
|
|
//not used: wire load_idle_cmd_sw = exe_instr[28:26] == 3'b011;
|
415 |
|
|
wire load_idle_cmd_swl = exe_instr[28:26] == 3'b010;
|
416 |
|
|
wire load_idle_cmd_swr = exe_instr[28:26] == 3'b110;
|
417 |
|
|
|
418 |
|
|
wire [31:0] load_idle_rt = (exe_instr_rt == mem_result_index)? mem_result : exe_b;
|
419 |
|
|
|
420 |
|
|
wire [7:0] load_idle_byte =
|
421 |
|
|
(data_address[1:0] == 2'd0)? data_cache_q[7:0] :
|
422 |
|
|
(data_address[1:0] == 2'd1)? data_cache_q[15:8] :
|
423 |
|
|
(data_address[1:0] == 2'd2)? data_cache_q[23:16] :
|
424 |
|
|
data_cache_q[31:24];
|
425 |
|
|
wire [15:0] load_idle_halfword =
|
426 |
|
|
(data_address[1:0] == 2'd0)? data_cache_q[15:0] :
|
427 |
|
|
data_cache_q[31:16];
|
428 |
|
|
|
429 |
|
|
wire [31:0] load_idle_lwl =
|
430 |
|
|
(data_address[1:0] == 2'd0)? { data_cache_q[7:0], load_idle_rt[23:0] } :
|
431 |
|
|
(data_address[1:0] == 2'd1)? { data_cache_q[15:0], load_idle_rt[15:0] } :
|
432 |
|
|
(data_address[1:0] == 2'd2)? { data_cache_q[23:0], load_idle_rt[7:0] } :
|
433 |
|
|
data_cache_q[31:0];
|
434 |
|
|
|
435 |
|
|
wire [31:0] load_idle_lwr =
|
436 |
|
|
(data_address[1:0] == 2'd0)? data_cache_q[31:0] :
|
437 |
|
|
(data_address[1:0] == 2'd1)? { load_idle_rt[31:24], data_cache_q[31:8] } :
|
438 |
|
|
(data_address[1:0] == 2'd2)? { load_idle_rt[31:16], data_cache_q[31:16] } :
|
439 |
|
|
{ load_idle_rt[31:8], data_cache_q[31:24] };
|
440 |
|
|
|
441 |
|
|
wire [31:0] load_idle_result =
|
442 |
|
|
(load_idle_cmd_lb)? { {24{load_idle_byte[7]}}, load_idle_byte } :
|
443 |
|
|
(load_idle_cmd_lbu)? { 24'd0, load_idle_byte } :
|
444 |
|
|
(load_idle_cmd_lh)? { {16{load_idle_halfword[15]}}, load_idle_halfword } :
|
445 |
|
|
(load_idle_cmd_lhu)? { 16'd0, load_idle_halfword } :
|
446 |
|
|
(load_idle_cmd_lw)? data_cache_q[31:0] :
|
447 |
|
|
(load_idle_cmd_lwl)? load_idle_lwl :
|
448 |
|
|
load_idle_lwr;
|
449 |
|
|
|
450 |
|
|
wire [3:0] load_idle_byteenable = (~(n_at_idle))? 4'hF : data_byteenable;
|
451 |
|
|
|
452 |
|
|
reg [2:0] load_cmd_reg;
|
453 |
|
|
always @(posedge clk or negedge rst_n) begin
|
454 |
|
|
if(rst_n == 1'b0) load_cmd_reg <= 3'b0;
|
455 |
|
|
else if(exe_cmd_load_do) load_cmd_reg <= exe_instr[28:26];
|
456 |
|
|
end
|
457 |
|
|
|
458 |
|
|
reg [4:0] load_instr_rt_reg;
|
459 |
|
|
always @(posedge clk or negedge rst_n) begin
|
460 |
|
|
if(rst_n == 1'b0) load_instr_rt_reg <= 5'b0;
|
461 |
|
|
else if(exe_cmd_load_do) load_instr_rt_reg <= exe_instr_rt;
|
462 |
|
|
end
|
463 |
|
|
|
464 |
|
|
reg [31:0] load_rt_reg;
|
465 |
|
|
always @(posedge clk or negedge rst_n) begin
|
466 |
|
|
if(rst_n == 1'b0) load_rt_reg <= 32'd0;
|
467 |
|
|
else if(exe_cmd_load_do) load_rt_reg <= load_idle_rt;
|
468 |
|
|
end
|
469 |
|
|
|
470 |
|
|
wire load_idle_tlb_ok_cache_ok = exe_cmd_load_do && data_cache_q[53] && ~(n_at_idle) && (
|
471 |
|
|
(~(tlb_use_at_idle) && data_cache_q[52:32] == { pfn_at_idle, data_address[11] }) || //tlb not in use
|
472 |
|
|
(tlb_use_at_idle && micro_check_matched && micro_check_result[48] && data_cache_q[52:32] == {micro_check_result[39:20], data_address[11]}) //tlb in micro
|
473 |
|
|
);
|
474 |
|
|
|
475 |
|
|
wire load_idle_tlb_ok_cache_isolate = exe_cmd_load_do && config_isolate_cache && (
|
476 |
|
|
~(tlb_use_at_idle) || //tlb not in use
|
477 |
|
|
(tlb_use_at_idle && micro_check_matched && micro_check_result[48]) //tlb in micro
|
478 |
|
|
);
|
479 |
|
|
|
480 |
|
|
wire load_idle_tlb_ok_finished = load_idle_tlb_ok_cache_ok || load_idle_tlb_ok_cache_isolate;
|
481 |
|
|
|
482 |
|
|
wire load_idle_tlb_bad_exc_inv = exe_cmd_load_do && tlb_use_at_idle && (
|
483 |
|
|
(micro_check_matched && ~(micro_check_result[48])) //tlb in micro
|
484 |
|
|
);
|
485 |
|
|
|
486 |
|
|
wire load_idle_tlb_ok_cache_bad = exe_cmd_load_do && (
|
487 |
|
|
(~(tlb_use_at_idle) && (~(data_cache_q[53]) || n_at_idle || data_cache_q[52:32] != { pfn_at_idle, data_address[11] })) || //tlb not in use
|
488 |
|
|
(tlb_use_at_idle && micro_check_matched && micro_check_result[48] && (~(data_cache_q[53]) || n_at_idle || data_cache_q[52:32] != { micro_check_result[39:20], data_address[11] })) //tlb in micro
|
489 |
|
|
);
|
490 |
|
|
wire load_idle_tlb_ok_cache_bad_fifo_ok = load_idle_tlb_ok_cache_bad && ~(ram_fifo_full);
|
491 |
|
|
wire load_idle_tlb_ok_cache_bad_fifo_bad = load_idle_tlb_ok_cache_bad && ram_fifo_full;
|
492 |
|
|
|
493 |
|
|
wire load_idle_tlb_wait = exe_cmd_load_do && tlb_use_at_idle && ~(micro_check_matched);
|
494 |
|
|
|
495 |
|
|
//------------------------------------------------------------------------------ state TLB
|
496 |
|
|
|
497 |
|
|
wire load_tlb_tlb_ok_cache_ok = load_state == LOAD_TLB && tlb_ram_data_hit && tlb_ram_data_result[48] && data_cache_q_reg[53] && data_cache_q_reg[52:32] == { tlb_ram_data_result[39:20], data_address_reg[11] };
|
498 |
|
|
wire load_tlb_tlb_ok_cache_isolate = load_state == LOAD_TLB && tlb_ram_data_hit && tlb_ram_data_result[48] && config_isolate_cache;
|
499 |
|
|
|
500 |
|
|
wire load_tlb_tlb_ok_finished = load_tlb_tlb_ok_cache_ok || load_tlb_tlb_ok_cache_isolate;
|
501 |
|
|
|
502 |
|
|
wire load_tlb_tlb_bad_exc_inv = load_state == LOAD_TLB && tlb_ram_data_hit && ~(tlb_ram_data_result[48]);
|
503 |
|
|
wire load_tlb_tlb_bad_exc_miss= load_state == LOAD_TLB && ~(tlb_ram_data_hit) && tlb_ram_data_missed;
|
504 |
|
|
|
505 |
|
|
wire load_tlb_tlb_ok_cache_bad =
|
506 |
|
|
load_state == LOAD_TLB && tlb_ram_data_hit && tlb_ram_data_result[48] && (~(data_cache_q_reg[53]) || data_cache_q_reg[52:32] != { tlb_ram_data_result[39:20], data_address_reg[11] });
|
507 |
|
|
|
508 |
|
|
wire load_tlb_tlb_ok_cache_bad_fifo_ok = load_tlb_tlb_ok_cache_bad && ~(ram_fifo_full);
|
509 |
|
|
wire load_tlb_tlb_ok_cache_bad_fifo_bad = load_tlb_tlb_ok_cache_bad && ram_fifo_full;
|
510 |
|
|
|
511 |
|
|
//------------------------------------------------------------------------------ state FIFO
|
512 |
|
|
|
513 |
|
|
wire load_fifo_end = load_state == LOAD_FIFO && ~(ram_fifo_full);
|
514 |
|
|
|
515 |
|
|
//------------------------------------------------------------------------------ state TLB or RESULT
|
516 |
|
|
|
517 |
|
|
wire load_result_cmd_lb = load_cmd_reg == 3'b000;
|
518 |
|
|
wire load_result_cmd_lbu = load_cmd_reg == 3'b100;
|
519 |
|
|
wire load_result_cmd_lh = load_cmd_reg == 3'b001;
|
520 |
|
|
wire load_result_cmd_lhu = load_cmd_reg == 3'b101;
|
521 |
|
|
wire load_result_cmd_lw = load_cmd_reg == 3'b011;
|
522 |
|
|
wire load_result_cmd_lwl = load_cmd_reg == 3'b010;
|
523 |
|
|
//not used: wire load_result_cmd_lwr = load_cmd_reg == 3'b110;
|
524 |
|
|
|
525 |
|
|
wire [31:0] load_result_data = (load_state == LOAD_TLB)? data_cache_q_reg[31:0] : ram_result;
|
526 |
|
|
|
527 |
|
|
wire [7:0] load_result_byte =
|
528 |
|
|
(data_address_reg[1:0] == 2'd0)? load_result_data[7:0] :
|
529 |
|
|
(data_address_reg[1:0] == 2'd1)? load_result_data[15:8] :
|
530 |
|
|
(data_address_reg[1:0] == 2'd2)? load_result_data[23:16] :
|
531 |
|
|
load_result_data[31:24];
|
532 |
|
|
wire [15:0] load_result_halfword =
|
533 |
|
|
(data_address_reg[1:0] == 2'd0)? load_result_data[15:0] :
|
534 |
|
|
load_result_data[31:16];
|
535 |
|
|
|
536 |
|
|
wire [31:0] load_result_lwl =
|
537 |
|
|
(data_address_reg[1:0] == 2'd0)? { load_result_data[7:0], load_rt_reg[23:0] } :
|
538 |
|
|
(data_address_reg[1:0] == 2'd1)? { load_result_data[15:0], load_rt_reg[15:0] } :
|
539 |
|
|
(data_address_reg[1:0] == 2'd2)? { load_result_data[23:0], load_rt_reg[7:0] } :
|
540 |
|
|
load_result_data;
|
541 |
|
|
|
542 |
|
|
wire [31:0] load_result_lwr =
|
543 |
|
|
(data_address_reg[1:0] == 2'd0)? load_result_data :
|
544 |
|
|
(data_address_reg[1:0] == 2'd1)? { load_rt_reg[31:24], load_result_data[31:8] } :
|
545 |
|
|
(data_address_reg[1:0] == 2'd2)? { load_rt_reg[31:16], load_result_data[31:16] } :
|
546 |
|
|
{ load_rt_reg[31:8], load_result_data[31:24] };
|
547 |
|
|
|
548 |
|
|
wire [31:0] load_result_value =
|
549 |
|
|
(load_result_cmd_lb)? { {24{load_result_byte[7]}}, load_result_byte } :
|
550 |
|
|
(load_result_cmd_lbu)? { 24'd0, load_result_byte } :
|
551 |
|
|
(load_result_cmd_lh)? { {16{load_result_halfword[15]}}, load_result_halfword } :
|
552 |
|
|
(load_result_cmd_lhu)? { 16'd0, load_result_halfword } :
|
553 |
|
|
(load_result_cmd_lw)? load_result_data :
|
554 |
|
|
(load_result_cmd_lwl)? load_result_lwl :
|
555 |
|
|
load_result_lwr;
|
556 |
|
|
|
557 |
|
|
//------------------------------------------------------------------------------ store
|
558 |
|
|
//------------------------------------------------------------------------------
|
559 |
|
|
//------------------------------------------------------------------------------
|
560 |
|
|
|
561 |
|
|
/*
|
562 |
|
|
Possible store states:
|
563 |
|
|
|
564 |
|
|
State STORE_IDLE:
|
565 |
|
|
- store_idle_tlb_ok_fifo_ok -> stay at IDLE; write fifo / cache / micro
|
566 |
|
|
- store_idle_tlb_exc -> stay at IDLE; exception
|
567 |
|
|
- store_idle_tlb_ok_fifo_bad -> goto FIFO; write micro
|
568 |
|
|
- store_idle_tlb_wait -> goto TLB
|
569 |
|
|
|
570 |
|
|
State STORE_FIFO:
|
571 |
|
|
- store_fifo_end -> goto IDLE; write fifo / cache
|
572 |
|
|
|
573 |
|
|
State STORE_TLB:
|
574 |
|
|
- store_tlb_tlb_ok_fifo_ok -> goto IDLE; write fifo / cache / micro
|
575 |
|
|
- store_tlb_tlb_ok_fifo_bad -> goto FIFO; write micro
|
576 |
|
|
*/
|
577 |
|
|
|
578 |
|
|
localparam [1:0] STORE_IDLE = 2'd0;
|
579 |
|
|
localparam [1:0] STORE_FIFO = 2'd1;
|
580 |
|
|
localparam [1:0] STORE_TLB = 2'd2;
|
581 |
|
|
|
582 |
|
|
reg [1:0] store_state;
|
583 |
|
|
always @(posedge clk or negedge rst_n) begin
|
584 |
|
|
if(rst_n == 1'b0) store_state <= STORE_IDLE;
|
585 |
|
|
else if(store_idle_tlb_ok_fifo_bad) store_state <= STORE_FIFO;
|
586 |
|
|
else if(store_fifo_end) store_state <= STORE_IDLE;
|
587 |
|
|
else if(store_idle_tlb_wait) store_state <= STORE_TLB;
|
588 |
|
|
else if(store_tlb_tlb_ok_fifo_ok) store_state <= STORE_IDLE;
|
589 |
|
|
else if(store_tlb_tlb_ok_fifo_bad) store_state <= STORE_FIFO;
|
590 |
|
|
else if(store_tlb_tlb_bad_exc_miss || store_tlb_tlb_bad_exc_modif || store_tlb_tlb_bad_exc_inv) store_state <= STORE_IDLE;
|
591 |
|
|
end
|
592 |
|
|
|
593 |
|
|
//------------------------------------------------------------------------------ IDLE state
|
594 |
|
|
|
595 |
|
|
wire store_idle_tlb_ok = exe_cmd_store_do && (
|
596 |
|
|
~(tlb_use_at_idle) || //tlb not in use
|
597 |
|
|
(tlb_use_at_idle && micro_check_matched && micro_check_result[48:47] == 2'b11) //tlb in micro
|
598 |
|
|
);
|
599 |
|
|
|
600 |
|
|
wire store_idle_tlb_ok_fifo_ok = store_idle_tlb_ok && ~(ram_fifo_full);
|
601 |
|
|
wire store_idle_tlb_ok_fifo_bad= store_idle_tlb_ok && ram_fifo_full;
|
602 |
|
|
|
603 |
|
|
wire [31:0] store_idle_data_zero =
|
604 |
|
|
(load_idle_cmd_swl && data_address[1:0] == 2'b00)? { 24'd0, exe_b[31:24] } :
|
605 |
|
|
(load_idle_cmd_swl && data_address[1:0] == 2'b01)? { 16'd0, exe_b[31:16] } :
|
606 |
|
|
(load_idle_cmd_swl && data_address[1:0] == 2'b10)? { 8'd0, exe_b[31:8] } :
|
607 |
|
|
(load_idle_cmd_swl && data_address[1:0] == 2'b11)? exe_b :
|
608 |
|
|
(load_idle_cmd_swr && data_address[1:0] == 2'b00)? exe_b :
|
609 |
|
|
(load_idle_cmd_swr && data_address[1:0] == 2'b01)? { exe_b[23:0], 8'd0 } :
|
610 |
|
|
(load_idle_cmd_swr && data_address[1:0] == 2'b10)? { exe_b[15:0], 16'd0 } :
|
611 |
|
|
(load_idle_cmd_swr && data_address[1:0] == 2'b11)? { exe_b[7:0], 24'd0 } :
|
612 |
|
|
(data_address[1:0] == 2'b00)? exe_b :
|
613 |
|
|
(data_address[1:0] == 2'b01)? { exe_b[23:0], 8'd0 } :
|
614 |
|
|
(data_address[1:0] == 2'b10)? { exe_b[15:0], 16'd0 } :
|
615 |
|
|
{ exe_b[7:0], 24'd0 };
|
616 |
|
|
|
617 |
|
|
wire [31:0] store_idle_data = {
|
618 |
|
|
({8{data_byteenable[3]}} & store_idle_data_zero[31:24]) | (~({8{data_byteenable[3]}}) & data_cache_q[31:24]),
|
619 |
|
|
({8{data_byteenable[2]}} & store_idle_data_zero[23:16]) | (~({8{data_byteenable[2]}}) & data_cache_q[23:16]),
|
620 |
|
|
({8{data_byteenable[1]}} & store_idle_data_zero[15:8]) | (~({8{data_byteenable[1]}}) & data_cache_q[15:8]),
|
621 |
|
|
({8{data_byteenable[0]}} & store_idle_data_zero[7:0]) | (~({8{data_byteenable[0]}}) & data_cache_q[7:0])
|
622 |
|
|
};
|
623 |
|
|
|
624 |
|
|
wire store_idle_tlb_bad_exc_modif =
|
625 |
|
|
exe_cmd_store_do && tlb_use_at_idle && micro_check_matched && micro_check_result[48:47] == 2'b10;
|
626 |
|
|
wire store_idle_tlb_bad_exc_inv =
|
627 |
|
|
exe_cmd_store_do && tlb_use_at_idle && micro_check_matched && micro_check_result[48] == 1'b0;
|
628 |
|
|
|
629 |
|
|
wire store_idle_tlb_wait = exe_cmd_store_do && tlb_use_at_idle && ~(micro_check_matched);
|
630 |
|
|
|
631 |
|
|
//------------------------------------------------------------------------------ FIFO state
|
632 |
|
|
|
633 |
|
|
wire store_fifo_end = store_state == STORE_FIFO && ~(ram_fifo_full);
|
634 |
|
|
|
635 |
|
|
//------------------------------------------------------------------------------ TLB state
|
636 |
|
|
|
637 |
|
|
wire store_tlb_tlb_ok = store_state == STORE_TLB && tlb_ram_data_hit && tlb_ram_data_result[48:47] == 2'b11;
|
638 |
|
|
|
639 |
|
|
wire store_tlb_tlb_ok_fifo_ok = store_tlb_tlb_ok && ~(ram_fifo_full);
|
640 |
|
|
wire store_tlb_tlb_ok_fifo_bad= store_tlb_tlb_ok && ram_fifo_full;
|
641 |
|
|
|
642 |
|
|
wire store_tlb_tlb_bad_exc_miss = store_state == STORE_TLB && ~(tlb_ram_data_hit) && tlb_ram_data_missed;
|
643 |
|
|
wire store_tlb_tlb_bad_exc_modif = store_state == STORE_TLB && tlb_ram_data_hit && tlb_ram_data_result[48:47] == 2'b10;
|
644 |
|
|
wire store_tlb_tlb_bad_exc_inv = store_state == STORE_TLB && tlb_ram_data_hit && tlb_ram_data_result[48] == 1'b0;
|
645 |
|
|
|
646 |
|
|
//------------------------------------------------------------------------------ cache
|
647 |
|
|
//------------------------------------------------------------------------------
|
648 |
|
|
//------------------------------------------------------------------------------
|
649 |
|
|
|
650 |
|
|
//input [31:0] data_address_next,
|
651 |
|
|
//input [31:0] data_address,
|
652 |
|
|
|
653 |
|
|
//input [31:0] ram_result_address,
|
654 |
|
|
//input ram_result_valid,
|
655 |
|
|
//input ram_result_is_read_instr,
|
656 |
|
|
//input [2:0] ram_result_burstcount,
|
657 |
|
|
//input [31:0] ram_result,
|
658 |
|
|
|
659 |
|
|
//input [53:0] data_cache_q,
|
660 |
|
|
|
661 |
|
|
assign data_cache_write_enable =
|
662 |
|
|
(~(n_reg) && ram_result_valid && ~(ram_result_is_read_instr)) ||
|
663 |
|
|
(store_idle_tlb_ok_fifo_ok && ~(n_at_idle) && (data_byteenable == 4'hF || (data_cache_q[53] && data_cache_q[52:32] == { pfn_at_idle, data_address[11]}))) ||
|
664 |
|
|
(store_fifo_end && ~(n_reg) && (data_byteenable_reg == 4'hF || (data_cache_q_reg[53] && data_cache_q_reg[52:32] == { pfn_reg, data_address_reg[11]}))) ||
|
665 |
|
|
(store_tlb_tlb_ok_fifo_ok && ~(tlb_ram_data_result[46]) && (data_byteenable_reg == 4'hF || (data_cache_q_reg[53] && data_cache_q_reg[52:32] == { tlb_ram_data_result[39:20], data_address_reg[11]})));
|
666 |
|
|
|
667 |
|
|
assign data_cache_write_address = (store_idle_tlb_ok_fifo_ok)? data_address[10:2] : data_address_reg[10:2];
|
668 |
|
|
|
669 |
|
|
assign data_cache_read_address = data_address_next[10:2];
|
670 |
|
|
|
671 |
|
|
/*
|
672 |
|
|
[53] valid
|
673 |
|
|
[52:32] tag
|
674 |
|
|
[31:0] data
|
675 |
|
|
*/
|
676 |
|
|
assign data_cache_data =
|
677 |
|
|
(store_idle_tlb_ok_fifo_ok)? { ~(config_isolate_cache) || data_byteenable == 4'hF, pfn_at_idle, data_address[11], store_idle_data } :
|
678 |
|
|
(store_fifo_end)? { ~(config_isolate_cache) || data_byteenable_reg == 4'hF, pfn_reg, data_address_reg[11], data_cache_q_reg[31:0] } :
|
679 |
|
|
(store_tlb_tlb_ok_fifo_ok)? { ~(config_isolate_cache) || data_byteenable_reg == 4'hF, tlb_ram_data_result[39:20], data_address_reg[11], data_cache_q_reg[31:0] } :
|
680 |
|
|
{ 1'b1, pfn_reg, data_address_reg[11], ram_result }; //load
|
681 |
|
|
|
682 |
|
|
//------------------------------------------------------------------------------ data fifo
|
683 |
|
|
//------------------------------------------------------------------------------
|
684 |
|
|
//------------------------------------------------------------------------------
|
685 |
|
|
|
686 |
|
|
//input ram_fifo_full,
|
687 |
|
|
|
688 |
|
|
assign ram_fifo_wrreq =
|
689 |
|
|
load_idle_tlb_ok_cache_bad_fifo_ok || load_tlb_tlb_ok_cache_bad_fifo_ok || load_fifo_end ||
|
690 |
|
|
(~(config_isolate_cache) && (store_idle_tlb_ok_fifo_ok || store_tlb_tlb_ok_fifo_ok || store_fifo_end));
|
691 |
|
|
|
692 |
|
|
//{ [66] 1'b is_write, [65:36] 30'b address, [35:4] 32'b value, [3:0] 4'b byteena (4'b0000 - can burst 4 words) }
|
693 |
|
|
assign ram_fifo_data =
|
694 |
|
|
(load_idle_tlb_ok_cache_bad_fifo_ok)? { 1'b0, pfn_at_idle, data_address[11:2], 32'd0, load_idle_byteenable } :
|
695 |
|
|
(load_tlb_tlb_ok_cache_bad_fifo_ok)? { 1'b0, tlb_ram_data_result[39:20], data_address_reg[11:2], 32'd0, data_byteenable_reg } :
|
696 |
|
|
(load_fifo_end)? { 1'b0, pfn_reg, data_address_reg[11:2], 32'd0, data_byteenable_reg } :
|
697 |
|
|
(store_idle_tlb_ok_fifo_ok)? { 1'b1, pfn_at_idle, data_address[11:2], store_idle_data, data_byteenable } :
|
698 |
|
|
(store_fifo_end)? { 1'b1, pfn_reg, data_address_reg[11:2], data_cache_q_reg[31:0], data_byteenable_reg } :
|
699 |
|
|
{ 1'b1, tlb_ram_data_result[39:20], data_address_reg[11:2], data_cache_q_reg[31:0], data_byteenable_reg }; //store_tlb_tlb_ok_fifo_ok
|
700 |
|
|
|
701 |
|
|
//------------------------------------------------------------------------------ micro tlb
|
702 |
|
|
//------------------------------------------------------------------------------
|
703 |
|
|
//------------------------------------------------------------------------------
|
704 |
|
|
|
705 |
|
|
//input micro_check_matched,
|
706 |
|
|
/*
|
707 |
|
|
[19:0] vpn
|
708 |
|
|
[39:20] pfn
|
709 |
|
|
[45:40] asid
|
710 |
|
|
[46] n noncachable
|
711 |
|
|
[47] d dirty = write-enable
|
712 |
|
|
[48] v valid
|
713 |
|
|
[49] g global
|
714 |
|
|
*/
|
715 |
|
|
//input [49:0] micro_check_result,
|
716 |
|
|
|
717 |
|
|
wire micro_check_do = tlb_use_at_idle;
|
718 |
|
|
wire [19:0] micro_check_vpn = data_address[31:12];
|
719 |
|
|
wire [5:0] micro_check_asid = entryhi_asid;
|
720 |
|
|
|
721 |
|
|
wire micro_write_do = tlb_ram_data_hit && (load_state == LOAD_TLB || store_state == STORE_TLB);
|
722 |
|
|
|
723 |
|
|
wire [49:0] micro_write_value = tlb_ram_data_result;
|
724 |
|
|
|
725 |
|
|
wire micro_check_matched;
|
726 |
|
|
wire [49:0] micro_check_result;
|
727 |
|
|
|
728 |
|
|
memory_data_tlb_micro memory_data_tlb_micro_inst(
|
729 |
|
|
.clk (clk),
|
730 |
|
|
.rst_n (rst_n),
|
731 |
|
|
|
732 |
|
|
//
|
733 |
|
|
.micro_flush_do (micro_flush_do), //input
|
734 |
|
|
|
735 |
|
|
//
|
736 |
|
|
.micro_write_do (micro_write_do), //input
|
737 |
|
|
.micro_write_value (micro_write_value), //input [49:0]
|
738 |
|
|
|
739 |
|
|
//
|
740 |
|
|
.micro_check_do (micro_check_do), //input
|
741 |
|
|
.micro_check_vpn (micro_check_vpn), //input [19:0]
|
742 |
|
|
.micro_check_asid (micro_check_asid), //input [5:0]
|
743 |
|
|
.micro_check_matched(micro_check_matched), //output
|
744 |
|
|
.micro_check_result (micro_check_result) //output [49:0]
|
745 |
|
|
);
|
746 |
|
|
|
747 |
|
|
//------------------------------------------------------------------------------ muldiv
|
748 |
|
|
//------------------------------------------------------------------------------
|
749 |
|
|
//------------------------------------------------------------------------------
|
750 |
|
|
|
751 |
|
|
wire muldiv_busy;
|
752 |
|
|
|
753 |
|
|
wire [6:0] exe_cmd_for_muldiv = (exception_start || config_kernel_mode_exc_now)? `CMD_null : exe_cmd;
|
754 |
|
|
|
755 |
|
|
block_muldiv block_muldiv_inst(
|
756 |
|
|
.clk (clk),
|
757 |
|
|
.rst_n (rst_n),
|
758 |
|
|
|
759 |
|
|
.exe_cmd_for_muldiv (exe_cmd_for_muldiv), //input [6:0]
|
760 |
|
|
.exe_a (exe_a), //input [31:0]
|
761 |
|
|
.exe_b (exe_b), //input [31:0]
|
762 |
|
|
.exe_instr_rd (exe_instr_rd), //input [4:0]
|
763 |
|
|
|
764 |
|
|
.muldiv_busy (muldiv_busy), //output
|
765 |
|
|
|
766 |
|
|
.muldiv_result_index(muldiv_result_index), //output [4:0]
|
767 |
|
|
.muldiv_result (muldiv_result) //output [31:0]
|
768 |
|
|
);
|
769 |
|
|
|
770 |
|
|
//------------------------------------------------------------------------------ coprocessor 0
|
771 |
|
|
//------------------------------------------------------------------------------
|
772 |
|
|
//------------------------------------------------------------------------------
|
773 |
|
|
|
774 |
|
|
wire [31:0] coproc0_output;
|
775 |
|
|
|
776 |
|
|
wire config_isolate_cache;
|
777 |
|
|
wire config_coproc0_usable;
|
778 |
|
|
wire config_coproc1_usable;
|
779 |
|
|
|
780 |
|
|
wire [5:0] tlbw_index;
|
781 |
|
|
wire [49:0] tlbw_value;
|
782 |
|
|
wire [5:0] tlbr_index;
|
783 |
|
|
|
784 |
|
|
block_cp0 block_cp0_inst(
|
785 |
|
|
.clk (clk),
|
786 |
|
|
.rst_n (rst_n),
|
787 |
|
|
|
788 |
|
|
//
|
789 |
|
|
.config_switch_caches (config_switch_caches), //output
|
790 |
|
|
.config_isolate_cache (config_isolate_cache), //output
|
791 |
|
|
.config_coproc0_usable (config_coproc0_usable), //output
|
792 |
|
|
.config_coproc1_usable (config_coproc1_usable), //output
|
793 |
|
|
.config_kernel_mode (config_kernel_mode), //output
|
794 |
|
|
|
795 |
|
|
//
|
796 |
|
|
.exe_cmd_mtc0 (exe_cmd_mtc0), //input
|
797 |
|
|
.exe_instr (exe_instr), //input [31:0]
|
798 |
|
|
.exe_b (exe_b), //input [31:0]
|
799 |
|
|
|
800 |
|
|
.exe_cmd_rfe (exe_cmd_rfe), //input
|
801 |
|
|
.exe_cmd_tlbr (exe_cmd_tlbr), //input
|
802 |
|
|
.exe_cmd_tlbwi (exe_cmd_tlbwi), //input
|
803 |
|
|
.exe_cmd_tlbwr (exe_cmd_tlbwr), //input
|
804 |
|
|
|
805 |
|
|
//
|
806 |
|
|
.coproc0_output (coproc0_output), //output [31:0]
|
807 |
|
|
|
808 |
|
|
//
|
809 |
|
|
.tlbw_index (tlbw_index), //output [5:0]
|
810 |
|
|
.tlbw_value (tlbw_value), //output [49:0]
|
811 |
|
|
|
812 |
|
|
//
|
813 |
|
|
.tlbr_index (tlbr_index), //output [5:0]
|
814 |
|
|
.tlb_ram_read_result_ready (tlb_ram_read_result_ready), //input
|
815 |
|
|
.tlb_ram_read_result (tlb_ram_read_result), //input [49:0]
|
816 |
|
|
|
817 |
|
|
//
|
818 |
|
|
.tlbp_update (tlbp_update), //input
|
819 |
|
|
.tlbp_hit (tlbp_hit), //input
|
820 |
|
|
.tlbp_index (tlbp_index), //input [5:0]
|
821 |
|
|
|
822 |
|
|
//
|
823 |
|
|
.micro_flush_do (micro_flush_do), //output
|
824 |
|
|
.entryhi_asid (entryhi_asid), //output [5:0]
|
825 |
|
|
|
826 |
|
|
//
|
827 |
|
|
.sr_cm_set (sr_cm_set), //input
|
828 |
|
|
.sr_cm_clear (sr_cm_clear), //input
|
829 |
|
|
|
830 |
|
|
//
|
831 |
|
|
.interrupt_vector (interrupt_vector), //input [5:0]
|
832 |
|
|
|
833 |
|
|
//
|
834 |
|
|
.exception_start (exception_start), //output
|
835 |
|
|
.exception_start_pc (exception_start_pc), //output [31:0]
|
836 |
|
|
|
837 |
|
|
//
|
838 |
|
|
.mem_stalled (mem_stalled), //input
|
839 |
|
|
.mem_cmd (mem_cmd), //input [6:0]
|
840 |
|
|
.mem_instr (mem_instr), //input [31:0]
|
841 |
|
|
.mem_pc_plus4 (mem_pc_plus4), //input [31:0]
|
842 |
|
|
.mem_branched (mem_branched), //input [1:0]
|
843 |
|
|
.mem_branch_address (mem_branch_address), //input [31:0]
|
844 |
|
|
.mem_badvpn (mem_badvpn) //input [31:0]
|
845 |
|
|
);
|
846 |
|
|
|
847 |
|
|
//------------------------------------------------------------------------------
|
848 |
|
|
// synthesis translate_off
|
849 |
|
|
wire _unused_ok = &{ 1'b0, data_address_next[31:11], data_address_next[1:0], ram_result_address[1:0], micro_check_result[49], micro_check_result[45:40], micro_check_result[19:0], 1'b0 };
|
850 |
|
|
// synthesis translate_on
|
851 |
|
|
//------------------------------------------------------------------------------
|
852 |
|
|
|
853 |
|
|
endmodule
|