| 1 |
2 |
alfik |
/*
|
| 2 |
|
|
* This file is subject to the terms and conditions of the BSD License. See
|
| 3 |
|
|
* the file "LICENSE" in the main directory of this archive for more details.
|
| 4 |
|
|
*
|
| 5 |
|
|
* Copyright (C) 2014 Aleksander Osman
|
| 6 |
|
|
*/
|
| 7 |
|
|
|
| 8 |
|
|
#include <cstdio>
|
| 9 |
|
|
#include <cstdlib>
|
| 10 |
|
|
|
| 11 |
|
|
#include <sys/mman.h>
|
| 12 |
|
|
#include <sys/types.h>
|
| 13 |
|
|
#include <sys/stat.h>
|
| 14 |
|
|
#include <fcntl.h>
|
| 15 |
|
|
#include <unistd.h>
|
| 16 |
|
|
|
| 17 |
|
|
#include "VaoR3000.h"
|
| 18 |
|
|
#include "VaoR3000_aoR3000.h"
|
| 19 |
|
|
#include "VaoR3000_pipeline_rf.h"
|
| 20 |
|
|
#include "VaoR3000_pipeline_if.h"
|
| 21 |
|
|
#include "VaoR3000_pipeline_mem.h"
|
| 22 |
|
|
#include "VaoR3000_block_muldiv.h"
|
| 23 |
|
|
#include "VaoR3000_memory_tlb_ram.h"
|
| 24 |
|
|
#include "VaoR3000_block_cp0.h"
|
| 25 |
|
|
#include "VaoR3000_pipeline_exe.h"
|
| 26 |
|
|
#include "VaoR3000_model_true_dual_ram__W32_WB4.h"
|
| 27 |
|
|
#include "VaoR3000_model_simple_dual_ram__W20_WB5.h"
|
| 28 |
|
|
|
| 29 |
|
|
#include "verilated.h"
|
| 30 |
|
|
#include "verilated_vcd_c.h"
|
| 31 |
|
|
|
| 32 |
|
|
#include "shared_mem.h"
|
| 33 |
|
|
|
| 34 |
|
|
//------------------------------------------------------------------------------
|
| 35 |
|
|
|
| 36 |
|
|
volatile shared_mem_t *shared_ptr = NULL;
|
| 37 |
|
|
|
| 38 |
|
|
//------------------------------------------------------------------------------
|
| 39 |
|
|
|
| 40 |
|
|
void usleep_or_finish() {
|
| 41 |
|
|
if(shared_ptr->test_finished) {
|
| 42 |
|
|
printf("Finishing.\n");
|
| 43 |
|
|
exit(0);
|
| 44 |
|
|
}
|
| 45 |
|
|
usleep(1);
|
| 46 |
|
|
}
|
| 47 |
|
|
|
| 48 |
|
|
//128MB
|
| 49 |
|
|
#define MAX_MEMORY 0x08000000
|
| 50 |
|
|
#define RESET_VECTOR 0x1FC00000
|
| 51 |
|
|
|
| 52 |
|
|
//------------------------------------------------------------------------------
|
| 53 |
|
|
|
| 54 |
|
|
int main(int argc, char **argv) {
|
| 55 |
|
|
|
| 56 |
|
|
//map shared memory
|
| 57 |
|
|
int fd = open("./../tester/shared_mem.dat", O_RDWR, S_IRUSR | S_IWUSR);
|
| 58 |
|
|
|
| 59 |
|
|
if(fd == -1) {
|
| 60 |
|
|
perror("open() failed for shared_mem.dat");
|
| 61 |
|
|
return -1;
|
| 62 |
|
|
}
|
| 63 |
|
|
|
| 64 |
|
|
shared_ptr = (shared_mem_t *)mmap(NULL, sizeof(shared_mem_t), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
|
| 65 |
|
|
|
| 66 |
|
|
if(shared_ptr == MAP_FAILED) {
|
| 67 |
|
|
perror("mmap() failed");
|
| 68 |
|
|
close(fd);
|
| 69 |
|
|
return -2;
|
| 70 |
|
|
}
|
| 71 |
|
|
|
| 72 |
|
|
//--------------------------------------------------------------------------
|
| 73 |
|
|
|
| 74 |
|
|
Verilated::commandArgs(argc, argv);
|
| 75 |
|
|
|
| 76 |
|
|
Verilated::traceEverOn(true);
|
| 77 |
|
|
VerilatedVcdC* tracer = new VerilatedVcdC;
|
| 78 |
|
|
|
| 79 |
|
|
VaoR3000 *top = new VaoR3000();
|
| 80 |
|
|
top->trace (tracer, 99);
|
| 81 |
|
|
//tracer->rolloverMB(1000000);
|
| 82 |
|
|
tracer->open("aoR3000.vcd");
|
| 83 |
|
|
|
| 84 |
|
|
bool dump_enabled = false;
|
| 85 |
|
|
|
| 86 |
|
|
//reset
|
| 87 |
|
|
vluint64_t halfcycle = 0;
|
| 88 |
|
|
|
| 89 |
|
|
top->clk = 0; top->rst_n = 1; top->eval(); if(dump_enabled) { tracer->dump(halfcycle); } halfcycle++;
|
| 90 |
|
|
top->clk = 0; top->rst_n = 0; top->eval(); if(dump_enabled) { tracer->dump(halfcycle); } halfcycle++;
|
| 91 |
|
|
top->rst_n = 1;
|
| 92 |
|
|
|
| 93 |
|
|
printf("Waiting for initialize..."); fflush(stdout);
|
| 94 |
|
|
while(shared_ptr->proc_ao.initialize_do == false) usleep_or_finish();
|
| 95 |
|
|
|
| 96 |
|
|
shared_ptr->proc_ao.initialize_do = false;
|
| 97 |
|
|
printf("done\n");
|
| 98 |
|
|
|
| 99 |
|
|
//--------------------------------------------------------------------------
|
| 100 |
|
|
|
| 101 |
|
|
uint32 event_counter = 0;
|
| 102 |
|
|
|
| 103 |
|
|
struct read_t {
|
| 104 |
|
|
uint32 count;
|
| 105 |
|
|
uint32 byteenable;
|
| 106 |
|
|
uint32 address;
|
| 107 |
|
|
};
|
| 108 |
|
|
read_t read[5];
|
| 109 |
|
|
uint32 read_list_count = sizeof(read) / sizeof(read_t);
|
| 110 |
|
|
memset(read, 0, sizeof(read));
|
| 111 |
|
|
|
| 112 |
|
|
bool stall_wait = false;
|
| 113 |
|
|
bool stall_state = false;
|
| 114 |
|
|
|
| 115 |
|
|
bool is_exception_waiting = false;
|
| 116 |
|
|
|
| 117 |
|
|
while(!Verilated::gotFinish()) {
|
| 118 |
|
|
|
| 119 |
|
|
//---------------------------------------------------------------------- avalon master
|
| 120 |
|
|
|
| 121 |
|
|
top->avm_waitrequest = 0;
|
| 122 |
|
|
top->avm_readdatavalid = 0;
|
| 123 |
|
|
top->avm_readdata = 0;
|
| 124 |
|
|
|
| 125 |
|
|
if(top->avm_read) {
|
| 126 |
|
|
bool found = false;
|
| 127 |
|
|
for(uint32 i=0; i<read_list_count; i++) {
|
| 128 |
|
|
if(read[i].count == 0) {
|
| 129 |
|
|
read[i].address = top->avm_address & 0xFFFFFFFC;
|
| 130 |
|
|
read[i].byteenable = top->avm_byteenable;
|
| 131 |
|
|
read[i].count = top->avm_burstcount;
|
| 132 |
|
|
|
| 133 |
|
|
found = true;
|
| 134 |
|
|
break;
|
| 135 |
|
|
}
|
| 136 |
|
|
}
|
| 137 |
|
|
if(found == false) {
|
| 138 |
|
|
printf("[aoR3000]: read fatal error: too many reads.\n");
|
| 139 |
|
|
exit(-1);
|
| 140 |
|
|
}
|
| 141 |
|
|
}
|
| 142 |
|
|
else if(read[0].count > 0) {
|
| 143 |
|
|
top->avm_readdatavalid = 1;
|
| 144 |
|
|
|
| 145 |
|
|
if(read[0].address < MAX_MEMORY) {
|
| 146 |
|
|
top->avm_readdata = shared_ptr->mem.ints[read[0].address/4];
|
| 147 |
|
|
}
|
| 148 |
|
|
else if(read[0].address >= RESET_VECTOR && read[0].address < RESET_VECTOR + sizeof(shared_ptr->reset_vector)) {
|
| 149 |
|
|
top->avm_readdata = shared_ptr->reset_vector[(read[0].address - RESET_VECTOR)/4];
|
| 150 |
|
|
}
|
| 151 |
|
|
else {
|
| 152 |
|
|
shared_ptr->proc_ao.read_address = read[0].address & 0xFFFFFFFC;
|
| 153 |
|
|
shared_ptr->proc_ao.read_byteenable = read[0].byteenable;
|
| 154 |
|
|
shared_ptr->proc_ao.read_do = true;
|
| 155 |
|
|
|
| 156 |
|
|
while(shared_ptr->proc_ao.read_do) usleep_or_finish();
|
| 157 |
|
|
|
| 158 |
|
|
top->avm_readdata = shared_ptr->proc_ao.read_data;
|
| 159 |
|
|
}
|
| 160 |
|
|
read[0].address += 4;
|
| 161 |
|
|
read[0].count--;
|
| 162 |
|
|
|
| 163 |
|
|
if(read[0].count == 0) {
|
| 164 |
|
|
memmove(&read[0], &read[1], sizeof(read) - sizeof(read_t));
|
| 165 |
|
|
}
|
| 166 |
|
|
}
|
| 167 |
|
|
|
| 168 |
|
|
//----------------------------------------------------------------------
|
| 169 |
|
|
|
| 170 |
|
|
if(stall_state == true) stall_state = ((top->v->pipeline_mem_inst->__PVT__mem_stall & 1) == 0)? false : true;
|
| 171 |
|
|
|
| 172 |
|
|
uint32 cmd = top->v->pipeline_mem_inst->__PVT__mem_cmd & 0x7F;
|
| 173 |
|
|
|
| 174 |
|
|
bool stall_start = cmd != 0 && stall_state == true;
|
| 175 |
|
|
bool stall_end = stall_wait && stall_state == false;
|
| 176 |
|
|
|
| 177 |
|
|
uint32 was_instruction = ((cmd != 0) && stall_state == false) || stall_end;
|
| 178 |
|
|
uint32 was_pc = top->v->pipeline_mem_inst->__PVT__mem_pc_plus4;
|
| 179 |
|
|
|
| 180 |
|
|
if(stall_start) {
|
| 181 |
|
|
stall_wait = true;
|
| 182 |
|
|
}
|
| 183 |
|
|
else if(stall_end) {
|
| 184 |
|
|
stall_wait = false;
|
| 185 |
|
|
}
|
| 186 |
|
|
|
| 187 |
|
|
if(stall_state == false) stall_state = ((top->v->pipeline_mem_inst->__PVT__mem_stall & 1) == 0)? false : true;
|
| 188 |
|
|
|
| 189 |
|
|
//----------------------------------------------------------------------
|
| 190 |
|
|
|
| 191 |
|
|
bool dump_enabled = false; //event_counter > 40565500;
|
| 192 |
|
|
|
| 193 |
|
|
//---------------------------------------------------------------------- interrupt
|
| 194 |
|
|
|
| 195 |
|
|
bool irq2_enable = ((was_instruction && stall_end == false && (event_counter + 1) == shared_ptr->irq2_at_event)) || ((event_counter + 1) > shared_ptr->irq2_at_event);
|
| 196 |
|
|
bool irq3_enable = ((was_instruction && stall_end == false && (event_counter + 1) == shared_ptr->irq3_at_event)) || ((event_counter + 1) > shared_ptr->irq3_at_event);
|
| 197 |
|
|
top->interrupt_vector = ((irq2_enable)? 1 : 0) | ((irq3_enable)? 2 : 0);
|
| 198 |
|
|
|
| 199 |
|
|
if(dump_enabled) {
|
| 200 |
|
|
printf("[%d]: ena2: %d ena3: %d cmd: %d at2: %d at3: %d stall_state: %d stall_start: %d stall_end: %d\n",
|
| 201 |
|
|
event_counter, (uint32)irq2_enable, (uint32)irq3_enable, cmd, shared_ptr->irq2_at_event, shared_ptr->irq3_at_event, stall_state, (uint32)stall_start, (uint32)stall_end);
|
| 202 |
|
|
fflush(stdout);
|
| 203 |
|
|
}
|
| 204 |
|
|
|
| 205 |
|
|
//---------------------------------------------------------------------- clock
|
| 206 |
|
|
top->clk = 0;
|
| 207 |
|
|
top->eval();
|
| 208 |
|
|
|
| 209 |
|
|
if(dump_enabled) tracer->dump(halfcycle);
|
| 210 |
|
|
halfcycle++;
|
| 211 |
|
|
|
| 212 |
|
|
top->clk = 1;
|
| 213 |
|
|
top->eval();
|
| 214 |
|
|
|
| 215 |
|
|
if(dump_enabled) tracer->dump(halfcycle);
|
| 216 |
|
|
halfcycle++;
|
| 217 |
|
|
|
| 218 |
|
|
tracer->flush();
|
| 219 |
|
|
|
| 220 |
|
|
//----------------------------------------------------------------------
|
| 221 |
|
|
if(top->avm_write) {
|
| 222 |
|
|
if(top->avm_burstcount != 1) {
|
| 223 |
|
|
printf("[avalon master error]: top->avm_burstcount(%d) != 1\n", top->avm_burstcount);
|
| 224 |
|
|
exit(-1);
|
| 225 |
|
|
}
|
| 226 |
|
|
|
| 227 |
|
|
uint32 mask = 0;
|
| 228 |
|
|
uint32 byteena = top->avm_byteenable;
|
| 229 |
|
|
for(uint32 i=0; i<4; i++) {
|
| 230 |
|
|
if(byteena & 1) mask |= (0xFF << (i*8));
|
| 231 |
|
|
byteena >>= 1;
|
| 232 |
|
|
}
|
| 233 |
|
|
|
| 234 |
|
|
shared_ptr->proc_ao.write_address = top->avm_address & 0xFFFFFFFC;
|
| 235 |
|
|
shared_ptr->proc_ao.write_byteenable = top->avm_byteenable;
|
| 236 |
|
|
shared_ptr->proc_ao.write_data = top->avm_writedata & mask;
|
| 237 |
|
|
shared_ptr->proc_ao.write_do = true;
|
| 238 |
|
|
|
| 239 |
|
|
while(shared_ptr->proc_ao.write_do) usleep_or_finish();
|
| 240 |
|
|
}
|
| 241 |
|
|
|
| 242 |
|
|
uint32 is_exception = (top->v->pipeline_if_inst->__PVT__exc_waiting & 1);
|
| 243 |
|
|
|
| 244 |
|
|
//interrupt after stalled instruction ignored
|
| 245 |
|
|
|
| 246 |
|
|
if((is_exception && was_instruction && (event_counter > 0 || halfcycle >= (4*2))) || was_instruction) {
|
| 247 |
|
|
|
| 248 |
|
|
if(dump_enabled) { printf("inc: %d, exception: %d\n", event_counter, is_exception); fflush(stdout); }
|
| 249 |
|
|
|
| 250 |
|
|
shared_ptr->proc_ao.report.counter = event_counter;
|
| 251 |
|
|
|
| 252 |
|
|
if(shared_ptr->check_at_event == event_counter) {
|
| 253 |
|
|
shared_ptr->proc_ao.check_do = true;
|
| 254 |
|
|
|
| 255 |
|
|
while(shared_ptr->proc_ao.check_do) usleep_or_finish();
|
| 256 |
|
|
}
|
| 257 |
|
|
|
| 258 |
|
|
event_counter++;
|
| 259 |
|
|
}
|
| 260 |
|
|
|
| 261 |
|
|
is_exception_waiting = is_exception;
|
| 262 |
|
|
}
|
| 263 |
|
|
|
| 264 |
|
|
top->final();
|
| 265 |
|
|
delete top;
|
| 266 |
|
|
return 0;
|
| 267 |
|
|
}
|
| 268 |
|
|
|
| 269 |
|
|
//------------------------------------------------------------------------------
|
| 270 |
|
|
|
| 271 |
|
|
/*
|
| 272 |
|
|
module aoR3000(
|
| 273 |
|
|
input clk,
|
| 274 |
|
|
input rst_n,
|
| 275 |
|
|
|
| 276 |
|
|
//
|
| 277 |
|
|
input [5:0] interrupt_vector,
|
| 278 |
|
|
|
| 279 |
|
|
//
|
| 280 |
|
|
output [31:0] avm_address,
|
| 281 |
|
|
output [31:0] avm_writedata,
|
| 282 |
|
|
output [3:0] avm_byteenable,
|
| 283 |
|
|
output [2:0] avm_burstcount,
|
| 284 |
|
|
output avm_write,
|
| 285 |
|
|
output avm_read,
|
| 286 |
|
|
|
| 287 |
|
|
input avm_waitrequest,
|
| 288 |
|
|
input avm_readdatavalid,
|
| 289 |
|
|
input [31:0] avm_readdata
|
| 290 |
|
|
);
|
| 291 |
|
|
*/
|
| 292 |
|
|
|
| 293 |
|
|
//------------------------------------------------------------------------------
|