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[/] [aor3000/] [trunk/] [sim/] [tester/] [test_data.cpp] - Blame information for rev 2

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1 2 alfik
/*
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 * This file is subject to the terms and conditions of the BSD License. See
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 * the file "LICENSE" in the main directory of this archive for more details.
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 *
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 * Copyright (C) 2014 Aleksander Osman
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 */
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#include <cstdio>
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#include <cstdlib>
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#include "tests.h"
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//------------------------------------------------------------------------------
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void data_till_exc_init(tst_t *tst, shared_mem_t *shared_ptr) {
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    for(int i=1; i<32; i++) shared_ptr->initial.reg[i-1] = rand_uint32();
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    shared_ptr->initial.pc = 0xA0001000;
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    //tlb left zero
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    shared_ptr->initial.index_p             = rand() & 0x1;
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    shared_ptr->initial.index_index         = rand() & 0x3F;
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    shared_ptr->initial.random              = rand() & 0x3F;
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    shared_ptr->initial.entrylo_pfn         = rand() & 0xFFFFF;
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    shared_ptr->initial.entrylo_n           = rand() & 0x1;
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    shared_ptr->initial.entrylo_d           = rand() & 0x1;
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    shared_ptr->initial.entrylo_v           = rand() & 0x1;
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    shared_ptr->initial.entrylo_g           = rand() & 0x1;
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    shared_ptr->initial.context_ptebase     = rand() & 0x7FF;
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    shared_ptr->initial.context_badvpn      = rand() & 0x7FFFF;
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    shared_ptr->initial.bad_vaddr           = rand_uint32();
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    shared_ptr->initial.entryhi_vpn         = rand() & 0xFFFFF;
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    shared_ptr->initial.entryhi_asid        = rand() & 0x3F;
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    shared_ptr->initial.sr_cp_usable        = rand() & 0xF;
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    shared_ptr->initial.sr_rev_endian       = rand() & 0x1;
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    shared_ptr->initial.sr_bootstrap_vec    = rand() & 0x1;
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    shared_ptr->initial.sr_tlb_shutdown     = rand() & 0x1;
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    shared_ptr->initial.sr_parity_err       = rand() & 0x1;
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    shared_ptr->initial.sr_cache_miss       = rand() & 0x1;
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    shared_ptr->initial.sr_parity_zero      = rand() & 0x1;
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    shared_ptr->initial.sr_switch_cache     = 0; //rand() & 0x1;
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    shared_ptr->initial.sr_isolate_cache    = 0; //rand() & 0x1;
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    shared_ptr->initial.sr_irq_mask         = rand() & 0xFF;
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    shared_ptr->initial.sr_ku_ie            = rand() & 0x3F;
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    shared_ptr->initial.cause_branch_delay  = rand() & 0x1;
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    shared_ptr->initial.cause_cp_error      = rand() & 0x3;
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    shared_ptr->initial.cause_irq_pending   = 0;
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    shared_ptr->initial.cause_exc_code      = rand() & 0x1F;
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    shared_ptr->initial.epc                 = rand_uint32();
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    //
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    shared_ptr->irq2_at_event = 0xFFFFFFFF;
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    shared_ptr->irq3_at_event = 0xFFFFFFFF;
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    //
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    uint32 *ptr = &shared_ptr->mem.ints[(shared_ptr->initial.pc & 0x1FFFFFFF) / 4];
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    bool cacheable = rand() % 2;
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    uint32 base = (cacheable)? 0x81000000 : 0xA1000000;
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    uint32 scope = (cacheable)? 10 : 65536;
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    uint32 loading_reg = 0;
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    shared_ptr->initial.reg[0] = base;
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    for(int operation=0; operation<100; operation++) {
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        uint32 type = rand() % 12;
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        uint32 storing_reg = 2 + (rand() % 30);
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        while(storing_reg == loading_reg) storing_reg = 2 + (rand() % 30);
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        if(type == 0) { //LB
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            loading_reg = 2 + (rand() % 30);
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            (*ptr) = (0b100000 << 26) | (1 << 21) | (loading_reg << 16) | (rand() % scope);
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            ptr++;
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        }
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        else if(type == 1) { //LBU
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            loading_reg = 2 + (rand() % 30);
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            (*ptr) = (0b100100 << 26) | (1 << 21) | (loading_reg << 16) | (rand() % scope);
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            ptr++;
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        }
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        else if(type == 2) { //LH
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            loading_reg = 2 + (rand() % 30);
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            (*ptr) = (0b100001 << 26) | (1 << 21) | (loading_reg << 16) | ((rand() % scope) & 0xFFFE) | (((rand() % 5) == 0)? 1 : 0);
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            ptr++;
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        }
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        else if(type == 3) { //LHU
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            loading_reg = 2 + (rand() % 30);
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            (*ptr) = (0b100101 << 26) | (1 << 21) | (loading_reg << 16) | ((rand() % scope) & 0xFFFE) | (((rand() % 5) == 0)? 1 : 0);
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            ptr++;
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        }
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        else if(type == 4) { //LW
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            loading_reg = 2 + (rand() % 30);
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            (*ptr) = (0b100011 << 26) | (1 << 21) | (loading_reg << 16) | ((rand() % scope) & 0xFFFC) | (((rand() % 5) == 0)? (1 + (rand() % 3)) : 0);
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            ptr++;
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        }
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        else if(type == 5) { //LWL
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            loading_reg = 2 + (rand() % 30);
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            (*ptr) = (0b100010 << 26) | (1 << 21) | (loading_reg << 16) | (rand() % scope);
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            ptr++;
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        }
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        else if(type == 6) { //LWR
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            loading_reg = 2 + (rand() % 30);
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            (*ptr) = (0b100110 << 26) | (1 << 21) | (loading_reg << 16) | (rand() % scope);
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            ptr++;
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        }
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        else if(type == 7) { //SB
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            loading_reg = 0;
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            (*ptr) = (0b101000 << 26) | (1 << 21) | (storing_reg << 16) | (rand() % scope);
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            ptr++;
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        }
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        else if(type == 8) { //SH
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            loading_reg = 0;
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            (*ptr) = (0b101001 << 26) | (1 << 21) | (storing_reg << 16) | ((rand() % scope) & 0xFFFE) | (((rand() % 5) == 0)? 1 : 0);
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            ptr++;
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        }
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        else if(type == 9) { //SW
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            loading_reg = 0;
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            (*ptr) = (0b101011 << 26) | (1 << 21) | (storing_reg << 16) | ((rand() % scope) & 0xFFFC) | (((rand() % 5) == 0)? (1 + (rand() % 3)) : 0);
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            ptr++;
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        }
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        else if(type == 10) { //SWL
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            loading_reg = 0;
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            (*ptr) = (0b101010 << 26) | (1 << 21) | (storing_reg << 16) | (rand() % scope);
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            ptr++;
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        }
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        else if(type == 11) { //SWR
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            loading_reg = 0;
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            (*ptr) = (0b101110 << 26) | (1 << 21) | (storing_reg << 16) | (rand() % scope);
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            ptr++;
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        }
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    }
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    base &= 0x1FFFFFFF;
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    for(uint32 i=base - 32768; i<base + 32768; i++) {
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        shared_ptr->mem.ints[i/4] = rand_uint32();
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    }
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    (*ptr) = rand() & 0x03FFFFC0;
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    (*ptr) |= 0b001100; //SYSCALL
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    ptr++;
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}
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//------------------------------------------------------------------------------

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