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[/] [aor3000/] [trunk/] [sim/] [tester/] [tests.h] - Blame information for rev 2

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1 2 alfik 
/*
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 * This file is subject to the terms and conditions of the BSD License. See
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 * the file "LICENSE" in the main directory of this archive for more details.
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 *
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 * Copyright (C) 2014 Aleksander Osman
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 */
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#ifndef __TESTS_H
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#define __TESTS_H
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#include "shared_mem.h"
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//------------------------------------------------------------------------------
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struct tst_t;
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typedef void   (*func_init) (tst_t *tst, shared_mem_t *shared_ptr);
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struct tst_t {
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    func_init  init;
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};
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//------------------------------------------------------------------------------
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uint32 rand_uint32();
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//------------------------------------------------------------------------------
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void arith_logic_till_exc_init  (tst_t *tst, shared_mem_t *shared_ptr);
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void exception_till_exc_init    (tst_t *tst, shared_mem_t *shared_ptr);
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void tlb_commands_till_exc_init (tst_t *tst, shared_mem_t *shared_ptr);
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void branch_till_exc_init       (tst_t *tst, shared_mem_t *shared_ptr);
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void data_till_exc_init         (tst_t *tst, shared_mem_t *shared_ptr);
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void interrupt_till_exc_init    (tst_t *tst, shared_mem_t *shared_ptr);
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void tlb_fetch_till_exc_init    (tst_t *tst, shared_mem_t *shared_ptr);
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void tlb_data_till_exc_init     (tst_t *tst, shared_mem_t *shared_ptr);
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//------------------------------------------------------------------------------
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/*
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000000  . SPECIAL
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    [5:0]
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    000000 SLL
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    000001
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    000010 SRL
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    000011 SRA
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    000100 SLLV
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    000101
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    000110 SRLV
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    000111 SRAV
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    001000 JR
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    001001 JALR
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    001010
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    001011
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    001100 SYSCALL
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    001101 BREAK
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    001110
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    001111
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    010000 MFHI
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    010001 MTHI
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    010010 MFLO
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    010011 MTLO
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    010100
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    010101
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    010110
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    010111
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    011000 MULT
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    011001 MULTU
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    011010 DIV
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    011011 DIVU
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    011100
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    011101
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    011110
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    011111
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    100000 ADD
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    100001 ADDU
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    100010 SUB
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    100011 SUBU
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    100100 AND
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    100101 OR
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    100110 XOR
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    100111 NOR
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    101000
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    101001
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    101010 SLT
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    101011 SLTU
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    101100
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    101101
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    101110
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    101111
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    110000
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    110001
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    110010
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    110011
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    110100
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    110101
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    110110
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    110111
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    111000
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    111001
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    111010
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    111011
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    111100
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    111101
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    111110
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    111111
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000001  .
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    [20:16]
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    00000 BLTZ
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    00001 BGEZ
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    10000 BLTZAL
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    10001 BGEZAL
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000010 J
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000011 JAL
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000100 BEQ
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000101 BNE
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000110 BLEZ rt must be 0
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000111 BGTZ rt must be 0
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001000 ADDI
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001001 ADDIU
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001010 SLTI
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001011 SLTIU
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001100 ANDI
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001101 ORI
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001110 XORI
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001111 LUI
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010000  .
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010001  .
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010010  .
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010011  .
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    [25:21]
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    00000 MFCz
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    00001
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    00010 CFCz
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    00011
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    00100 MTCz
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    00101
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    00110 CTCz
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    00111
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    01000   . BC0
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        [20:16]
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        00000 BC0F
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        00001 BC0T
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        00010 ign
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        00011 ign
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        other Reserved Instruction
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    01001
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    01010
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    01011
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    01100
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    01101
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    01110
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    01111
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    10000   .
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    10001   .
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    10010   .
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    10011   .
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    10100   .
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    10101   .
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    10110   .
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    10111   .
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    11000   .
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    11001   .
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    11010   .
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    11011   .
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    11100   .
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    11101   .
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    11110   .
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    11111   .
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        COPz
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        [5:0] for COP0
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        000001 TLBR
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        000010 TLBWI
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        000110 TLBWR
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        001000 TLBP
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        010000 RFE
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        other Reserved Instruction
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010100
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010101
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010110
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010111
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011000
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011001
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011010
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011011
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011100
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011101
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011110
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011111
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100000 LB
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100001 LH
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100010 LWL
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100011 LW
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100100 LBU
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100101 LHU
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100110 LWR
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100111
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101000 SB
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101001 SH
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101010 SWL
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101011 SW
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101100
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101101
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101110 SWR
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101111
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110000  .
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110001  .
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110010  .
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110011  .
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    LWCz
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110100
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110101
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110110
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110111
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111000  .
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111001  .
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111010  .
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111011  .
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    SWCz
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111100
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111101
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111110
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111111
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*/
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//------------------------------------------------------------------------------
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#endif //__TESTS_H

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