Subversion Repositories aor3000

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#

# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.

# Your use of Altera Corporation's design tools, logic functions

# and other software and tools, and its AMPP partner logic

# functions, and any output files from any of the foregoing

# (including device programming or simulation files), and any

# associated documentation or information are expressly subject

# to the terms and conditions of the Altera Program License

# Subscription Agreement, the Altera Quartus II License Agreement,

# the Altera MegaCore Function License Agreement, or other

# applicable license agreement, including, without limitation,

# that your use is for the sole purpose of programming logic

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# -------------------------------------------------------------------------- #

#

# Quartus II 64-Bit

# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition

# Date created = 20:51:00  July 29, 2014

#

# -------------------------------------------------------------------------- #

#

# Notes:

#

# 1) The default values for assignments are stored in the file:

#               aoR3000_assignment_defaults.qdf

#    If this file doesn't exist, see file:

#               assignment_defaults.qdf

#

# 2) Altera recommends that you do not modify this file. This

#    file is updated automatically by the Quartus II software

#    and any changes you make may be lost or overwritten.

#

# -------------------------------------------------------------------------- #

set_global_assignment -name FAMILY "Cyclone IV E"

set_global_assignment -name DEVICE EP4CE115F29C7

set_global_assignment -name TOP_LEVEL_ENTITY aoR3000

set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0

set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:51:00  JULY 29, 2014"

set_global_assignment -name LAST_QUARTUS_VERSION 14.0

set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files

set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0

set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top

set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top

set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"

set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_data_tlb_micro.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_instr_tlb_micro.v

set_global_assignment -name VERILOG_FILE ../../rtl/block/block_shift.v

set_global_assignment -name VERILOG_FILE ../../rtl/block/block_muldiv.v

set_global_assignment -name VERILOG_FILE ../../rtl/block/block_cp0.v

set_global_assignment -name VERILOG_FILE ../../rtl/block/block_long_div.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_tlb_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/memory/memory_avalon.v

set_global_assignment -name VERILOG_FILE ../../rtl/model/model_true_dual_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/model/model_simple_dual_ram.v

set_global_assignment -name VERILOG_FILE ../../rtl/model/model_mult.v

set_global_assignment -name VERILOG_FILE ../../rtl/model/model_fifo.v

set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/pipeline_rf.v

set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/pipeline_mem.v

set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/pipeline_if.v

set_global_assignment -name VERILOG_FILE ../../rtl/pipeline/pipeline_exe.v

set_global_assignment -name VERILOG_FILE ../../rtl/defines.v

set_global_assignment -name VERILOG_FILE ../../rtl/aoR3000.v

set_global_assignment -name SDC_FILE aoR3000.sdc

set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED

set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON

set_global_assignment -name SEARCH_PATH /home/alek/aktualne/github/aoR3000/rtl

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top