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[/] [apb2spi/] [trunk/] [rtl/] [APB_SLAVE.v] - Blame information for rev 14

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//////////////////////////////////////////////////////////////////////
////                                                              ////
//// APB- SPI 0.1 IP Core                                         ////
////                                                              ////
//// This file is part of the APB- SPI 0.1 IP Core project        ////
//// http://www.opencores.org/cores/APB- SPI 0.1 IP Core/         ////
////                                                              ////
//// Description                                                  ////
//// Implementation of XXX IP core according to                   ////
//// XXX IP core specification document.                          ////
////                                                              ////
//// To Do:                                                       ////
//// -                                                            ////
////                                                              ////
//// Author(s):                                                   ////
//// - Lakshmi Narayanan Vernugopal, email@opencores.org          ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              //// ///
///////////////////////////////////////////////////////////////////
`define APB_DATA_WIDTH  8
`define SPI_REG_WIDTH   8
`define APB_ADDR_WIDTH  3
//`define CLK_DIV_WIDTH 16
//`timescale 1ns/1ps
module APB_SLAVE
(
 // APB SLAVE PORT INTERFACE 
 input                             PCLK,
 input                             PRESETn,
 input [`APB_ADDR_WIDTH-1:0 ]      PADDR,
 input                             PWRITE,
 input                             PSEL,
 input                             PENABLE,
 input [`APB_DATA_WIDTH-1:0 ]      PWDATA,
 output reg [`APB_DATA_WIDTH-1:0 ] PRDATA,
 output reg                        PREADY,
 input                             TrFr,
 // SPI INTERFACE
 output reg [`SPI_REG_WIDTH-1:0]  SPI_CR_1,
 output reg [`SPI_REG_WIDTH-1:0]  SPI_CR_2,
 output reg [`SPI_REG_WIDTH-1:0]  SPI_BR_R,
 output reg [`SPI_REG_WIDTH-1:0]  SPI_ST_R,
 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_1,
 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_2,
 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_3,
 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_4
);
 
 
/////////////////////////////////////////////
//   Signal  Description                ////
/////////////////////////////////////////////
 
localparam IDLE   = 2'b00;
localparam SETUP  = 2'b01;
localparam ENABLE = 2'b10;
 
reg  [1:0]    STATE;
 
always@(posedge PCLK or negedge PRESETn)
begin
  if(!PRESETn)
  begin
    STATE <= IDLE;
    PREADY <= 0;
  end
  else
  begin
    PREADY <= 0;
    case(STATE)
     IDLE:  begin
              PREADY <= 1;
                  //if(PSEL && !PENABLE)
                  if(TrFr)
                            STATE  <= SETUP;
                          else
                STATE  <= IDLE;
                 end
         SETUP: begin
               if(PENABLE)
                            STATE  <= ENABLE;
               else
                STATE  <= IDLE;
                     end
         ENABLE:begin
               if(PENABLE)
                            STATE  <= SETUP;
               else
                STATE  <= IDLE;
             end
    endcase
  end
end
 
 
assign write_en =  PWRITE && (STATE==ENABLE);
assign read_en  = !PWRITE && (STATE==SETUP);
 
//always@(PADDR,PWDATA,write_en)
always@(posedge PCLK or negedge PRESETn)
  begin
  if(!PRESETn)
    begin
       PRDATA            <= 8'd0;
       SPI_CR_1          <= 8'd0;
       SPI_CR_2          <= 8'd0;
       SPI_BR_R          <= 8'd0;
       SPI_ST_R          <= 8'd0;
       SPI_DATA_Reg_1    <= 8'd0;
       SPI_DATA_Reg_2    <= 8'd0;
       SPI_DATA_Reg_3    <= 8'd0;
       SPI_DATA_Reg_4    <= 8'd0;
    end
  else
    begin
       if(write_en)
       begin
         case(PADDR)
            3'b000 : SPI_CR_1          <= PWDATA;
            3'b001 : SPI_CR_2          <= PWDATA;
            3'b010 : SPI_BR_R          <= PWDATA;
            3'b011 : SPI_ST_R          <= PWDATA;
            3'b100 : SPI_DATA_Reg_1    <= PWDATA;
            3'b101 : SPI_DATA_Reg_2    <= PWDATA;
            3'b110 : SPI_DATA_Reg_3    <= PWDATA;
            3'b111 : SPI_DATA_Reg_4    <= PWDATA;
            default: SPI_CR_1          <= PWDATA;
         endcase
       end
           else if(read_en && PENABLE)
           begin
         case(PADDR)
            3'b000 : PRDATA            <= SPI_CR_1      ;
            3'b001 : PRDATA            <= SPI_CR_2      ;
            3'b010 : PRDATA            <= SPI_BR_R      ;
            3'b011 : PRDATA            <= SPI_ST_R      ;
            3'b100 : PRDATA            <= SPI_DATA_Reg_1;
            3'b101 : PRDATA            <= SPI_DATA_Reg_2;
            3'b110 : PRDATA            <= SPI_DATA_Reg_3;
            3'b111 : PRDATA            <= SPI_DATA_Reg_4;
            default: PRDATA            <= SPI_CR_1;
         endcase
           end
       else
       begin
         SPI_CR_1          <= SPI_CR_1;
         SPI_CR_2          <= SPI_CR_2;
         SPI_BR_R          <= SPI_BR_R;
         SPI_ST_R          <= SPI_ST_R;
         SPI_DATA_Reg_1    <= SPI_DATA_Reg_1;
         SPI_DATA_Reg_2    <= SPI_DATA_Reg_2;
         SPI_DATA_Reg_3    <= SPI_DATA_Reg_3;
         SPI_DATA_Reg_4    <= SPI_DATA_Reg_4;
       end
    end
end
endmodule

Line No.	Rev	Author	Line
1	3	vlnaran	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// APB- SPI 0.1 IP Core ////`
4			`//// ////`
5			`//// This file is part of the APB- SPI 0.1 IP Core project ////`
6			`//// http://www.opencores.org/cores/APB- SPI 0.1 IP Core/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Implementation of XXX IP core according to ////`
10			`//// XXX IP core specification document. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Lakshmi Narayanan Vernugopal, email@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// //// ///`
43			`///////////////////////////////////////////////////////////////////`
44			`define APB_DATA_WIDTH 8
45			`define SPI_REG_WIDTH 8
46			`define APB_ADDR_WIDTH 3
47			//`define CLK_DIV_WIDTH 16
48			//`timescale 1ns/1ps
49			`module APB_SLAVE`
50			`(`
51			`// APB SLAVE PORT INTERFACE`
52			`input PCLK,`
53			`input PRESETn,`
54			input [`APB_ADDR_WIDTH-1:0 ] PADDR,
55			`input PWRITE,`
56			`input PSEL,`
57			`input PENABLE,`
58			input [`APB_DATA_WIDTH-1:0 ] PWDATA,
59			output reg [`APB_DATA_WIDTH-1:0 ] PRDATA,
60			`output reg PREADY,`
61			`input TrFr,`
62			`// SPI INTERFACE`
63			output reg [`SPI_REG_WIDTH-1:0] SPI_CR_1,
64			output reg [`SPI_REG_WIDTH-1:0] SPI_CR_2,
65			output reg [`SPI_REG_WIDTH-1:0] SPI_BR_R,
66			output reg [`SPI_REG_WIDTH-1:0] SPI_ST_R,
67			output reg [`SPI_REG_WIDTH-1:0] SPI_DATA_Reg_1,
68			output reg [`SPI_REG_WIDTH-1:0] SPI_DATA_Reg_2,
69			output reg [`SPI_REG_WIDTH-1:0] SPI_DATA_Reg_3,
70			output reg [`SPI_REG_WIDTH-1:0] SPI_DATA_Reg_4
71			`);`
72
73
74			`/////////////////////////////////////////////`
75			`// Signal Description ////`
76			`/////////////////////////////////////////////`
77
78			`localparam IDLE = 2'b00;`
79			`localparam SETUP = 2'b01;`
80			`localparam ENABLE = 2'b10;`
81
82			`reg [1:0] STATE;`
83
84			`always@(posedge PCLK or negedge PRESETn)`
85			`begin`
86			`if(!PRESETn)`
87			`begin`
88			`STATE <= IDLE;`
89			`PREADY <= 0;`
90			`end`
91			`else`
92			`begin`
93			`PREADY <= 0;`
94			`case(STATE)`
95			`IDLE: begin`
96			`PREADY <= 1;`
97			`//if(PSEL && !PENABLE)`
98			`if(TrFr)`
99			`STATE <= SETUP;`
100			`else`
101			`STATE <= IDLE;`
102			`end`
103			`SETUP: begin`
104			`if(PENABLE)`
105			`STATE <= ENABLE;`
106			`else`
107			`STATE <= IDLE;`
108			`end`
109			`ENABLE:begin`
110			`if(PENABLE)`
111			`STATE <= SETUP;`
112			`else`
113			`STATE <= IDLE;`
114			`end`
115			`endcase`
116			`end`
117			`end`
118
119
120			`assign write_en = PWRITE && (STATE==ENABLE);`
121			`assign read_en = !PWRITE && (STATE==SETUP);`
122
123			`//always@(PADDR,PWDATA,write_en)`
124			`always@(posedge PCLK or negedge PRESETn)`
125			`begin`
126			`if(!PRESETn)`
127			`begin`
128			`PRDATA <= 8'd0;`
129			`SPI_CR_1 <= 8'd0;`
130			`SPI_CR_2 <= 8'd0;`
131			`SPI_BR_R <= 8'd0;`
132			`SPI_ST_R <= 8'd0;`
133			`SPI_DATA_Reg_1 <= 8'd0;`
134			`SPI_DATA_Reg_2 <= 8'd0;`
135			`SPI_DATA_Reg_3 <= 8'd0;`
136			`SPI_DATA_Reg_4 <= 8'd0;`
137			`end`
138			`else`
139			`begin`
140			`if(write_en)`
141			`begin`
142			`case(PADDR)`
143			`3'b000 : SPI_CR_1 <= PWDATA;`
144			`3'b001 : SPI_CR_2 <= PWDATA;`
145			`3'b010 : SPI_BR_R <= PWDATA;`
146			`3'b011 : SPI_ST_R <= PWDATA;`
147			`3'b100 : SPI_DATA_Reg_1 <= PWDATA;`
148			`3'b101 : SPI_DATA_Reg_2 <= PWDATA;`
149			`3'b110 : SPI_DATA_Reg_3 <= PWDATA;`
150			`3'b111 : SPI_DATA_Reg_4 <= PWDATA;`
151			`default: SPI_CR_1 <= PWDATA;`
152			`endcase`
153			`end`
154			`else if(read_en && PENABLE)`
155			`begin`
156			`case(PADDR)`
157			`3'b000 : PRDATA <= SPI_CR_1 ;`
158			`3'b001 : PRDATA <= SPI_CR_2 ;`
159			`3'b010 : PRDATA <= SPI_BR_R ;`
160			`3'b011 : PRDATA <= SPI_ST_R ;`
161			`3'b100 : PRDATA <= SPI_DATA_Reg_1;`
162			`3'b101 : PRDATA <= SPI_DATA_Reg_2;`
163			`3'b110 : PRDATA <= SPI_DATA_Reg_3;`
164			`3'b111 : PRDATA <= SPI_DATA_Reg_4;`
165			`default: PRDATA <= SPI_CR_1;`
166			`endcase`
167			`end`
168			`else`
169			`begin`
170			`SPI_CR_1 <= SPI_CR_1;`
171			`SPI_CR_2 <= SPI_CR_2;`
172			`SPI_BR_R <= SPI_BR_R;`
173			`SPI_ST_R <= SPI_ST_R;`
174			`SPI_DATA_Reg_1 <= SPI_DATA_Reg_1;`
175			`SPI_DATA_Reg_2 <= SPI_DATA_Reg_2;`
176			`SPI_DATA_Reg_3 <= SPI_DATA_Reg_3;`
177			`SPI_DATA_Reg_4 <= SPI_DATA_Reg_4;`
178			`end`
179			`end`
180			`end`
181			`endmodule`

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[/] [apb2spi/] [trunk/] [rtl/] [APB_SLAVE.v] - Blame information for rev 14