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[/] [apb2spi/] [trunk/] [rtl/] [APB_SLAVE.v] - Blame information for rev 14

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1 3 vlnaran
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// APB- SPI 0.1 IP Core                                         ////
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////                                                              ////
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//// This file is part of the APB- SPI 0.1 IP Core project        ////
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//// http://www.opencores.org/cores/APB- SPI 0.1 IP Core/         ////
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////                                                              ////
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//// Description                                                  ////
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//// Implementation of XXX IP core according to                   ////
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//// XXX IP core specification document.                          ////
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////                                                              ////
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//// To Do:                                                       ////
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//// -                                                            ////
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Lakshmi Narayanan Vernugopal, email@opencores.org          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              //// ///
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///////////////////////////////////////////////////////////////////
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`define APB_DATA_WIDTH  8
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`define SPI_REG_WIDTH   8
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`define APB_ADDR_WIDTH  3
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//`define CLK_DIV_WIDTH 16
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//`timescale 1ns/1ps
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module APB_SLAVE
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(
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 // APB SLAVE PORT INTERFACE 
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 input                             PCLK,
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 input                             PRESETn,
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 input [`APB_ADDR_WIDTH-1:0 ]      PADDR,
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 input                             PWRITE,
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 input                             PSEL,
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 input                             PENABLE,
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 input [`APB_DATA_WIDTH-1:0 ]      PWDATA,
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 output reg [`APB_DATA_WIDTH-1:0 ] PRDATA,
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 output reg                        PREADY,
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 input                             TrFr,
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 // SPI INTERFACE
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_CR_1,
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_CR_2,
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_BR_R,
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_ST_R,
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_1,
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_2,
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_3,
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 output reg [`SPI_REG_WIDTH-1:0]  SPI_DATA_Reg_4
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);
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/////////////////////////////////////////////
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//   Signal  Description                ////
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/////////////////////////////////////////////
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localparam IDLE   = 2'b00;
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localparam SETUP  = 2'b01;
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localparam ENABLE = 2'b10;
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reg  [1:0]    STATE;
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always@(posedge PCLK or negedge PRESETn)
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begin
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  if(!PRESETn)
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  begin
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    STATE <= IDLE;
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    PREADY <= 0;
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  end
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  else
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  begin
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    PREADY <= 0;
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    case(STATE)
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     IDLE:  begin
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              PREADY <= 1;
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                  //if(PSEL && !PENABLE)
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                  if(TrFr)
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                            STATE  <= SETUP;
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                          else
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                STATE  <= IDLE;
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                 end
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         SETUP: begin
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               if(PENABLE)
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                            STATE  <= ENABLE;
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               else
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                STATE  <= IDLE;
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                     end
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         ENABLE:begin
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               if(PENABLE)
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                            STATE  <= SETUP;
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               else
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                STATE  <= IDLE;
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             end
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    endcase
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  end
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end
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assign write_en =  PWRITE && (STATE==ENABLE);
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assign read_en  = !PWRITE && (STATE==SETUP);
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//always@(PADDR,PWDATA,write_en)
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always@(posedge PCLK or negedge PRESETn)
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  begin
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  if(!PRESETn)
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    begin
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       PRDATA            <= 8'd0;
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       SPI_CR_1          <= 8'd0;
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       SPI_CR_2          <= 8'd0;
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       SPI_BR_R          <= 8'd0;
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       SPI_ST_R          <= 8'd0;
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       SPI_DATA_Reg_1    <= 8'd0;
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       SPI_DATA_Reg_2    <= 8'd0;
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       SPI_DATA_Reg_3    <= 8'd0;
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       SPI_DATA_Reg_4    <= 8'd0;
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    end
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  else
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    begin
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       if(write_en)
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       begin
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         case(PADDR)
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            3'b000 : SPI_CR_1          <= PWDATA;
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            3'b001 : SPI_CR_2          <= PWDATA;
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            3'b010 : SPI_BR_R          <= PWDATA;
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            3'b011 : SPI_ST_R          <= PWDATA;
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            3'b100 : SPI_DATA_Reg_1    <= PWDATA;
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            3'b101 : SPI_DATA_Reg_2    <= PWDATA;
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            3'b110 : SPI_DATA_Reg_3    <= PWDATA;
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            3'b111 : SPI_DATA_Reg_4    <= PWDATA;
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            default: SPI_CR_1          <= PWDATA;
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         endcase
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       end
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           else if(read_en && PENABLE)
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           begin
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         case(PADDR)
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            3'b000 : PRDATA            <= SPI_CR_1      ;
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            3'b001 : PRDATA            <= SPI_CR_2      ;
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            3'b010 : PRDATA            <= SPI_BR_R      ;
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            3'b011 : PRDATA            <= SPI_ST_R      ;
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            3'b100 : PRDATA            <= SPI_DATA_Reg_1;
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            3'b101 : PRDATA            <= SPI_DATA_Reg_2;
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            3'b110 : PRDATA            <= SPI_DATA_Reg_3;
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            3'b111 : PRDATA            <= SPI_DATA_Reg_4;
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            default: PRDATA            <= SPI_CR_1;
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         endcase
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           end
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       else
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       begin
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         SPI_CR_1          <= SPI_CR_1;
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         SPI_CR_2          <= SPI_CR_2;
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         SPI_BR_R          <= SPI_BR_R;
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         SPI_ST_R          <= SPI_ST_R;
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         SPI_DATA_Reg_1    <= SPI_DATA_Reg_1;
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         SPI_DATA_Reg_2    <= SPI_DATA_Reg_2;
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         SPI_DATA_Reg_3    <= SPI_DATA_Reg_3;
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         SPI_DATA_Reg_4    <= SPI_DATA_Reg_4;
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       end
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    end
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end
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endmodule

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