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[/] [apb2spi/] [trunk/] [tb/] [env/] [apb_agent/] [apb_slave.v] - Blame information for rev 15

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`timescale 1ns/1ps
 
module apb_slave(input [3:0] paddr,
                input pwrite,
                input [1:0] psel,
                input penable,
                output reg pready,
                input [31:0] pwdata,
                output reg [31:0] prdata,
                input pclk,
                input presetn);
 
                reg [31:0] spcr,spdr,wr_data;
 
                always@(posedge pclk or negedge presetn)
                if(!presetn)
                        pready <= 1'b0;
                else if(penable==1'b1)
                        pready <= 1'b1;
 
                always@(posedge pclk or negedge presetn)
                if(!presetn)
                        spcr <= 32'h0;
                else if(psel==2'b01 && pready && penable && pwrite && paddr==4'b0001)
                        spcr <= pwdata;
 
                always@(posedge pclk or negedge presetn)
                if(!presetn)
                        spdr <= 32'h0;
                else if(psel==2'b01 && pready && penable && pwrite && paddr==4'b0010)
                        spdr <= pwdata;
 
                always@(posedge pclk or negedge presetn)
                if(!presetn)
                        wr_data <= 32'h0;
                else if(psel==2'b01 && pready && penable && pwrite && paddr==4'b0011)
                        wr_data <= pwdata;
 
                always@(posedge pclk or negedge presetn)
                if(!presetn)
                        prdata <= 32'h0;
                else if(psel==2'b01 && pready && penable && !pwrite && paddr==4'b0001)
                        prdata <= spcr;
                else if(psel==2'b01 && pready && penable && !pwrite && paddr==4'b0010)
                        prdata <= spdr;
                else if(psel==2'b01 && pready && penable && !pwrite && paddr==4'b0011)
                        prdata <= wr_data;
 
endmodule
 

Line No.	Rev	Author	Line
1	15	vlnaran	`timescale 1ns/1ps
2
3			`module apb_slave(input [3:0] paddr,`
4			`input pwrite,`
5			`input [1:0] psel,`
6			`input penable,`
7			`output reg pready,`
8			`input [31:0] pwdata,`
9			`output reg [31:0] prdata,`
10			`input pclk,`
11			`input presetn);`
12
13			`reg [31:0] spcr,spdr,wr_data;`
14
15			`always@(posedge pclk or negedge presetn)`
16			`if(!presetn)`
17			`pready <= 1'b0;`
18			`else if(penable==1'b1)`
19			`pready <= 1'b1;`
20
21			`always@(posedge pclk or negedge presetn)`
22			`if(!presetn)`
23			`spcr <= 32'h0;`
24			`else if(psel==2'b01 && pready && penable && pwrite && paddr==4'b0001)`
25			`spcr <= pwdata;`
26
27			`always@(posedge pclk or negedge presetn)`
28			`if(!presetn)`
29			`spdr <= 32'h0;`
30			`else if(psel==2'b01 && pready && penable && pwrite && paddr==4'b0010)`
31			`spdr <= pwdata;`
32
33			`always@(posedge pclk or negedge presetn)`
34			`if(!presetn)`
35			`wr_data <= 32'h0;`
36			`else if(psel==2'b01 && pready && penable && pwrite && paddr==4'b0011)`
37			`wr_data <= pwdata;`
38
39			`always@(posedge pclk or negedge presetn)`
40			`if(!presetn)`
41			`prdata <= 32'h0;`
42			`else if(psel==2'b01 && pready && penable && !pwrite && paddr==4'b0001)`
43			`prdata <= spcr;`
44			`else if(psel==2'b01 && pready && penable && !pwrite && paddr==4'b0010)`
45			`prdata <= spdr;`
46			`else if(psel==2'b01 && pready && penable && !pwrite && paddr==4'b0011)`
47			`prdata <= wr_data;`
48
49			`endmodule`
50

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[/] [apb2spi/] [trunk/] [tb/] [env/] [apb_agent/] [apb_slave.v] - Blame information for rev 15