Supports APB and APB3 (pready and pslverr) bus protocols. Supports slave error, random wait states and fixed wait states.
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In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
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The RobustVerilog top source file is apb_slave.v, it calls the top definition file named def_apb_slave.txt.
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Changing the stub parameters should be made only in def_apb_master.txt in the src/base directory (changing address bits adding trace etc.).
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Once the Verilog files have been generated instruction on how to use the stub are at the top of apb_slave.v (tasks and parameters).